cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
}
+ cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
+
return cmd_buffer->record_result;
}
if (unlikely(cmd_buffer->device->trace_bo))
radv_cmd_buffer_trace_emit(cmd_buffer);
+ cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
+
return result;
}
if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
+ cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
+
return cmd_buffer->record_result;
}
cs_array[j] = cmd_buffer->cs;
if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
can_patch = false;
+
+ cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
}
for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
struct list_head list;
};
+enum radv_cmd_buffer_status {
+ RADV_CMD_BUFFER_STATUS_INVALID,
+ RADV_CMD_BUFFER_STATUS_INITIAL,
+ RADV_CMD_BUFFER_STATUS_RECORDING,
+ RADV_CMD_BUFFER_STATUS_EXECUTABLE,
+ RADV_CMD_BUFFER_STATUS_PENDING,
+};
+
struct radv_cmd_buffer {
VK_LOADER_DATA _loader_data;
VkCommandBufferUsageFlags usage_flags;
VkCommandBufferLevel level;
+ enum radv_cmd_buffer_status status;
struct radeon_winsys_cs *cs;
struct radv_cmd_state state;
struct radv_vertex_binding vertex_bindings[MAX_VBS];