cache_ram: Add write-enables

They will be needed by the dcache

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/cache_ram.vhdl b/cache_ram.vhdl
index e0ffd173d61255fd3a773451be175167b96a217c..346c6fe6a38cc746be22c981ea895e297d938753 100644 (file)
--- a/cache_ram.vhdl
+++ b/cache_ram.vhdl
@@ -6,7 +6,8 @@ use ieee.math_real.all;
 entity cache_ram is
     generic(
        ROW_BITS : integer := 16;
-       WIDTH    : integer := 64
+       WIDTH    : integer := 64;
+       TRACE    : boolean := false
        );
 
     port(
@@ -15,6 +16,7 @@ entity cache_ram is
        rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
        rd_data : out std_logic_vector(WIDTH - 1 downto 0);
        wr_en   : in  std_logic;
+       wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
        wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
        wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
        );
@@ -33,13 +35,32 @@ architecture rtl of cache_ram is
 
 begin
     process(clk)
+       variable lbit : integer range 0 to WIDTH - 1;
+       variable mbit : integer range 0 to WIDTH - 1;
+       variable widx : integer range 0 to SIZE - 1;
     begin
        if rising_edge(clk) then
            if wr_en = '1' then
-               ram(to_integer(unsigned(wr_addr))) <= wr_data;
+               if TRACE then
+                   report "write a:" & to_hstring(wr_addr) &
+                       " sel:" & to_hstring(wr_sel) &
+                       " dat:" & to_hstring(wr_data);
+               end if;
+               for i in 0 to WIDTH/8-1 loop
+                   lbit := i * 8;
+                   mbit := lbit + 7;
+                   widx := to_integer(unsigned(wr_addr));
+                   if wr_sel(i) = '1' then
+                       ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
+                   end if;
+               end loop;
            end if;
            if rd_en = '1' then
                rd_data <= ram(to_integer(unsigned(rd_addr)));
+               if TRACE then
+                   report "read a:" & to_hstring(rd_addr) &
+                       " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
+               end if;
            end if;
        end if;
     end process;

diff --git a/icache.vhdl b/icache.vhdl
index 89e491e1a9698d2613737ba5ce1cdc632c96b9b0..804b648554cfb0f1a7a12f7dfa5d6a41e5750f0c 100644 (file)
--- a/icache.vhdl
+++ b/icache.vhdl
@@ -290,6 +290,7 @@ begin
                rd_addr => rd_addr,
                rd_data => dout,
                wr_en   => do_write,
+               wr_sel  => (others => '1'),
                wr_addr => wr_addr,
                wr_data => wishbone_in.dat
                );