fetch_pc = Signal(32, reset=reset_vector)
self.sync += If(fetch_action != fetch_action_wait,
- output_pc.eq(fetch_pc)).
- Else( output_pc.eq(output_pc)) # hmmm...
- #self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ?
- # output_pc : fetch_pc);
+ output_pc.eq(fetch_pc))
memory_interface_fetch_address = fetch_pc[2:]
initial output_pc <= reset_vector;
initial output_state <= `fetch_output_state_empty;
- delayed_instruction = Signal(32, reset=0);
- delayed_instruction_valid = Signal(reset=0);
+ delayed_instruction = Signal(32, reset=0)
+ delayed_instruction_valid = Signal(reset=0)
self.sync += delayed_instruction.eq(output_instruction)
self.sync += output_state.eq(fetch_output_state_empty)