* metag.h: New file.
* dis-asm.h (print_insn_metag): New declaration.
* metag.h: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* configure: Regenerate.
* configure.in: Add Meta.
* disassemble.c: Add Meta support.
* metag-dis.c: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* archures.c (bfd_mach_metag): New.
* bfd-in2.h: Regenerate.
* config.bfd: Add Meta.
* configure: Regenerate.
* configure.in: Add Meta.
* cpu-metag.c: New file.
* elf-bfd.h: Add Meta.
* elf32-metag.c: New file.
* elf32-metag.h: New file.
* libbfd.h: Regenerate.
* reloc.c: Add Meta relocations.
* targets.c: Add Meta.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* config/tc-metag.c: New file.
* config/tc-metag.h: New file.
* configure.tgt: Add Meta.
* doc/Makefile.am: Add Meta.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add Meta.
* doc/as.texiinfo: Document Meta options.
* doc/c-metag.texi: New file.
* gas/metag/labelarithmetic.d: New file.
* gas/metag/labelarithmetic.s: New file.
* gas/metag/metacore12.d: New file.
* gas/metag/metacore12.s: New file.
* gas/metag/metacore21-invalid.l: New file.
* gas/metag/metacore21-invalid.s: New file.
* gas/metag/metacore21.d: New file.
* gas/metag/metacore21.s: New file.
* gas/metag/metacore21ext.d: New file.
* gas/metag/metacore21ext.s: New file.
* gas/metag/metadsp21-invalid.l: New file.
* gas/metag/metadsp21-invalid.s: New file.
* gas/metag/metadsp21.d: New file.
* gas/metag/metadsp21.s: New file.
* gas/metag/metadsp21ext.d: New file.
* gas/metag/metadsp21ext.s: New file.
* gas/metag/metafpu21.d: New file.
* gas/metag/metafpu21.s: New file.
* gas/metag/metafpu21ext.d: New file.
* gas/metag/metafpu21ext.s: New file.
* gas/metag/metag.exp: New file.
* gas/metag/tls.d: New file.
* gas/metag/tls.s: New file.
* Makefile.am: Add Meta.
* Makefile.in: Regenerate.
* configure.tgt: Add Meta.
* emulparams/elf32metag.sh: New file.
* emultempl/metagelf.em: New file.
* ld-elf/merge.d: Mark Meta as xfail.
* ld-gc/start.d: Skip this test on Meta.
* ld-gc/personality.d: Skip this test on Meta.
* ld-metag/external.s: New file.
* ld-metag/metag.exp: New file.
* ld-metag/pcrel.d: New file.
* ld-metag/pcrel.s: New file.
* ld-metag/shared.d: New file.
* ld-metag/shared.r: New file.
* ld-metag/shared.s: New file.
* ld-metag/stub.d: New file.
* ld-metag/stub.s: New file.
* ld-metag/stub_pic_app.d: New file.
* ld-metag/stub_pic_app.r: New file.
* ld-metag/stub_pic_app.s: New file.
* ld-metag/stub_pic_shared.d: New file.
* ld-metag/stub_pic_shared.s: New file.
* ld-metag/stub_shared.d: New file.
* ld-metag/stub_shared.r: New file.
* ld-metag/stub_shared.s: New file.
* binutils/readelf.c: (guess_is_rela): Add EM_METAG.
(dump_relocations): Add EM_METAG.
(get_machine_name): Correct case for Meta.
(is_32bit_abs_reloc): Add support for Meta ADDR32 reloc.
(is_none_reloc): Add support for Meta NONE reloc.
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * Makefile.am: Add Meta.
+ * Makefile.in: Regenerate.
+ * archures.c (bfd_mach_metag): New.
+ * bfd-in2.h: Regenerate.
+ * config.bfd: Add Meta.
+ * configure: Regenerate.
+ * configure.in: Add Meta.
+ * cpu-metag.c: New file.
+ * elf-bfd.h: Add Meta.
+ * elf32-metag.c: New file.
+ * elf32-metag.h: New file.
+ * libbfd.h: Regenerate.
+ * reloc.c: Add Meta relocations.
+ * targets.c: Add Meta.
+
2013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
* elf-bfd.h (elfcore_write_aarch_tls): Add prototype.
cpu-m88k.lo \
cpu-mcore.lo \
cpu-mep.lo \
+ cpu-metag.lo \
cpu-microblaze.lo \
cpu-mips.lo \
cpu-mmix.lo \
cpu-m88k.c \
cpu-mcore.c \
cpu-mep.c \
+ cpu-metag.c \
cpu-microblaze.c \
cpu-mips.c \
cpu-mmix.c \
elf32-m88k.lo \
elf32-mcore.lo \
elf32-mep.lo \
+ elf32-metag.lo \
elf32-microblaze.lo \
elf32-mips.lo \
elf32-moxie.lo \
elf32-m88k.c \
elf32-mcore.c \
elf32-mep.c \
+ elf32-metag.c \
elf32-microblaze.c \
elf32-mips.c \
elf32-moxie.c \
cpu-m88k.lo \
cpu-mcore.lo \
cpu-mep.lo \
+ cpu-metag.lo \
cpu-microblaze.lo \
cpu-mips.lo \
cpu-mmix.lo \
cpu-m88k.c \
cpu-mcore.c \
cpu-mep.c \
+ cpu-metag.c \
cpu-microblaze.c \
cpu-mips.c \
cpu-mmix.c \
elf32-m88k.lo \
elf32-mcore.lo \
elf32-mep.lo \
+ elf32-metag.lo \
elf32-microblaze.lo \
elf32-mips.lo \
elf32-moxie.lo \
elf32-m88k.c \
elf32-mcore.c \
elf32-mep.c \
+ elf32-metag.c \
elf32-microblaze.c \
elf32-mips.c \
elf32-moxie.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-m9s12xg.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-mcore.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-mep.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-metag.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-microblaze.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-mips.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-mmix.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-m88k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mcore.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mep.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-metag.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-microblaze.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mips.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-moxie.Plo@am__quote@
.#define bfd_mach_mep 1
.#define bfd_mach_mep_h1 0x6831
.#define bfd_mach_mep_c5 0x6335
+. bfd_arch_metag,
+.#define bfd_mach_metag 1
. bfd_arch_ia64, {* HP/Intel ia64 *}
.#define bfd_mach_ia64_elf64 64
.#define bfd_mach_ia64_elf32 32
extern const bfd_arch_info_type bfd_m88k_arch;
extern const bfd_arch_info_type bfd_mcore_arch;
extern const bfd_arch_info_type bfd_mep_arch;
+extern const bfd_arch_info_type bfd_metag_arch;
extern const bfd_arch_info_type bfd_mips_arch;
extern const bfd_arch_info_type bfd_microblaze_arch;
extern const bfd_arch_info_type bfd_mmix_arch;
&bfd_m88k_arch,
&bfd_mcore_arch,
&bfd_mep_arch,
+ &bfd_metag_arch,
&bfd_microblaze_arch,
&bfd_mips_arch,
&bfd_mmix_arch,
#define bfd_mach_mep 1
#define bfd_mach_mep_h1 0x6831
#define bfd_mach_mep_c5 0x6335
+ bfd_arch_metag,
+#define bfd_mach_metag 1
bfd_arch_ia64, /* HP/Intel ia64 */
#define bfd_mach_ia64_elf64 64
#define bfd_mach_ia64_elf32 32
BFD_RELOC_MEP_GNU_VTENTRY,
+/* Imagination Technologies Meta relocations. */
+ BFD_RELOC_METAG_HIADDR16,
+ BFD_RELOC_METAG_LOADDR16,
+ BFD_RELOC_METAG_RELBRANCH,
+ BFD_RELOC_METAG_GETSETOFF,
+ BFD_RELOC_METAG_HIOG,
+ BFD_RELOC_METAG_LOOG,
+ BFD_RELOC_METAG_REL8,
+ BFD_RELOC_METAG_REL16,
+ BFD_RELOC_METAG_HI16_GOTOFF,
+ BFD_RELOC_METAG_LO16_GOTOFF,
+ BFD_RELOC_METAG_GETSET_GOTOFF,
+ BFD_RELOC_METAG_GETSET_GOT,
+ BFD_RELOC_METAG_HI16_GOTPC,
+ BFD_RELOC_METAG_LO16_GOTPC,
+ BFD_RELOC_METAG_HI16_PLT,
+ BFD_RELOC_METAG_LO16_PLT,
+ BFD_RELOC_METAG_RELBRANCH_PLT,
+ BFD_RELOC_METAG_GOTOFF,
+ BFD_RELOC_METAG_PLT,
+ BFD_RELOC_METAG_COPY,
+ BFD_RELOC_METAG_JMP_SLOT,
+ BFD_RELOC_METAG_RELATIVE,
+ BFD_RELOC_METAG_GLOB_DAT,
+ BFD_RELOC_METAG_TLS_GD,
+ BFD_RELOC_METAG_TLS_LDM,
+ BFD_RELOC_METAG_TLS_LDO_HI16,
+ BFD_RELOC_METAG_TLS_LDO_LO16,
+ BFD_RELOC_METAG_TLS_LDO,
+ BFD_RELOC_METAG_TLS_IE,
+ BFD_RELOC_METAG_TLS_IENONPIC,
+ BFD_RELOC_METAG_TLS_IENONPIC_HI16,
+ BFD_RELOC_METAG_TLS_IENONPIC_LO16,
+ BFD_RELOC_METAG_TLS_TPOFF,
+ BFD_RELOC_METAG_TLS_DTPMOD,
+ BFD_RELOC_METAG_TLS_DTPOFF,
+ BFD_RELOC_METAG_TLS_LE,
+ BFD_RELOC_METAG_TLS_LE_HI16,
+ BFD_RELOC_METAG_TLS_LE_LO16,
+
/* These are relocations for the GETA instruction. */
BFD_RELOC_MMIX_GETA,
BFD_RELOC_MMIX_GETA_1,
targ_selvecs=bfd_elf32_mep_little_vec
;;
+ metag-*-*)
+ targ_defvec=bfd_elf32_metag_vec
+ targ_underscore=yes
+ ;;
+
microblazeel*-*)
targ_defvec=bfd_elf32_microblazeel_vec
targ_selvecs=bfd_elf32_microblaze_vec
bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
bfd_elf32_mep_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;;
bfd_elf32_mep_little_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;;
+ bfd_elf32_metag_vec) tb="$tb elf32-metag.lo elf32.lo $elf" ;;
bfd_elf32_microblazeel_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
bfd_elf32_microblaze_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;;
bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
bfd_elf32_mep_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;;
bfd_elf32_mep_little_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;;
+ bfd_elf32_metag_vec) tb="$tb elf32-metag.lo elf32.lo $elf" ;;
bfd_elf32_microblazeel_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
bfd_elf32_microblaze_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;;
--- /dev/null
+/* BFD support for the Imagination Technologies Meta processor.
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_metag_arch =
+{
+ 32, /* Bits per word. */
+ 32, /* Bits per address. */
+ 8, /* Bits per byte. */
+ bfd_arch_metag, /* Architecture. */
+ bfd_mach_metag, /* Machine. */
+ "metag", /* Architecture name. */
+ "metag", /* Printable name. */
+ 4, /* Section align power. */
+ TRUE, /* The default ? */
+ bfd_default_compatible, /* Architecture comparison fn. */
+ bfd_default_scan, /* String to architecture convert fn. */
+ bfd_arch_default_fill, /* Default fill. */
+ NULL /* Next in list. */
+};
M32R_ELF_DATA,
M68HC11_ELF_DATA,
M68K_ELF_DATA,
+ METAG_ELF_DATA,
MICROBLAZE_ELF_DATA,
MIPS_ELF_DATA,
MN10300_ELF_DATA,
--- /dev/null
+/* Meta support for 32-bit ELF
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf32-metag.h"
+#include "elf/metag.h"
+
+#define GOT_ENTRY_SIZE 4
+#define ELF_DYNAMIC_INTERPRETER "/lib/ld-uClibc.so.0"
+
+/* ABI version:
+ 0 - original
+ 1 - with GOT offset */
+#define METAG_ELF_ABI_VERSION 1
+
+static const unsigned int plt0_entry[] =
+ {
+ 0x02000005, /* MOVT D0Re0, #HI(GOT+4) */
+ 0x02000000, /* ADD D0Re0, D0Re0, #LO(GOT+4) */
+ 0xb70001e3, /* SETL [A0StP++], D0Re0, D1Re0 */
+ 0xc600012a, /* GETD PC, [D0Re0+#4] */
+ 0xa0fffffe /* NOP */
+ };
+
+static const unsigned int plt0_pic_entry[] =
+ {
+ 0x82900001, /* ADDT A0.2, CPC0, #0 */
+ 0x82100000, /* ADD A0.2, A0.2, #0 */
+ 0xa3100c20, /* MOV D0Re0, A0.2 */
+ 0xb70001e3, /* SETL [A0StP++], D0Re0, D1Re0 */
+ 0xc600012a, /* GETD PC, [D0Re0+#4] */
+ };
+
+static const unsigned int plt_entry[] =
+ {
+ 0x82100005, /* MOVT A0.2, #HI(GOT+off) */
+ 0x82100000, /* ADD A0.2, A0.2, #LO(GOT+off) */
+ 0xc600806a, /* GETD PC, [A0.2] */
+ 0x03000004, /* MOV D1Re0, #LO(offset) */
+ 0xa0000000 /* B PLT0 */
+ };
+
+static const unsigned int plt_pic_entry[] =
+ {
+ 0x82900001, /* ADDT A0.2, CPC0, #HI(GOT+off) */
+ 0x82100000, /* ADD A0.2, A0.2, #LO(GOT+off) */
+ 0xc600806a, /* GETD PC, [A0.2] */
+ 0x03000004, /* MOV D1Re0, #LO(offset) */
+ 0xa0000000 /* B PLT0 */
+ };
+
+/* Variable names follow a coding style.
+ Please follow this (Apps Hungarian) style:
+
+ Structure/Variable Prefix
+ elf_link_hash_table "etab"
+ elf_link_hash_entry "eh"
+
+ elf_metag_link_hash_table "htab"
+ elf_metag_link_hash_entry "hh"
+
+ bfd_link_hash_table "btab"
+ bfd_link_hash_entry "bh"
+
+ bfd_hash_table containing stubs "bstab"
+ elf_metag_stub_hash_entry "hsh"
+
+ elf_metag_dyn_reloc_entry "hdh"
+
+ Always remember to use GNU Coding Style. */
+
+#define PLT_ENTRY_SIZE sizeof(plt_entry)
+
+static reloc_howto_type elf_metag_howto_table[] =
+{
+ /* High order 16 bit absolute. */
+ HOWTO (R_METAG_HIADDR16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_HIADDR16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low order 16 bit absolute. */
+ HOWTO (R_METAG_LOADDR16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont,/* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_LOADDR16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 32 bit absolute. */
+ HOWTO (R_METAG_ADDR32, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_ADDR32", /* name */
+ FALSE, /* partial_inplace */
+ 0x00000000, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* No relocation. */
+ HOWTO (R_METAG_NONE, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_NONE", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 19 bit pc relative */
+ HOWTO (R_METAG_RELBRANCH, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 19, /* bitsize */
+ TRUE, /* pc_relative */
+ 5, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_RELBRANCH", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x00ffffe0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GET/SET offset */
+ HOWTO (R_METAG_GETSETOFF, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_GETSETOFF", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ EMPTY_HOWTO (6),
+ EMPTY_HOWTO (7),
+ EMPTY_HOWTO (8),
+ EMPTY_HOWTO (9),
+ EMPTY_HOWTO (10),
+ EMPTY_HOWTO (11),
+ EMPTY_HOWTO (12),
+ EMPTY_HOWTO (13),
+ EMPTY_HOWTO (14),
+ EMPTY_HOWTO (15),
+ EMPTY_HOWTO (16),
+ EMPTY_HOWTO (17),
+ EMPTY_HOWTO (18),
+ EMPTY_HOWTO (19),
+ EMPTY_HOWTO (20),
+ EMPTY_HOWTO (21),
+ EMPTY_HOWTO (22),
+ EMPTY_HOWTO (23),
+ EMPTY_HOWTO (24),
+ EMPTY_HOWTO (25),
+ EMPTY_HOWTO (26),
+ EMPTY_HOWTO (27),
+ EMPTY_HOWTO (28),
+ EMPTY_HOWTO (29),
+
+ HOWTO (R_METAG_GNU_VTINHERIT, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ NULL, /* special_function */
+ "R_METAG_GNU_VTINHERIT", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_GNU_VTENTRY, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_elf_rel_vtable_reloc_fn, /* special_function */
+ "R_METAG_GNU_VTENTRY", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High order 16 bit GOT offset */
+ HOWTO (R_METAG_HI16_GOTOFF, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_HI16_GOTOFF", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low order 16 bit GOT offset */
+ HOWTO (R_METAG_LO16_GOTOFF, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_LO16_GOTOFF", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GET/SET GOT offset */
+ HOWTO (R_METAG_GETSET_GOTOFF, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_GETSET_GOTOFF", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GET/SET GOT relative */
+ HOWTO (R_METAG_GETSET_GOT, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_GETSET_GOT", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High order 16 bit GOT reference */
+ HOWTO (R_METAG_HI16_GOTPC, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_HI16_GOTPC", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low order 16 bit GOT reference */
+ HOWTO (R_METAG_LO16_GOTPC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_LO16_GOTPC", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High order 16 bit PLT */
+ HOWTO (R_METAG_HI16_PLT, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_HI16_PLT", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low order 16 bit PLT */
+ HOWTO (R_METAG_LO16_PLT, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_LO16_PLT", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_RELBRANCH_PLT, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 19, /* bitsize */
+ TRUE, /* pc_relative */
+ 5, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_RELBRANCH_PLT", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x00ffffe0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Dummy relocs used by the linker internally. */
+ HOWTO (R_METAG_GOTOFF, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_GOTOFF", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_PLT, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_GOTOFF", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* This is used only by the dynamic linker. The symbol should exist
+ both in the object being run and in some shared library. The
+ dynamic linker copies the data addressed by the symbol from the
+ shared library into the object, because the object being
+ run has to have the data at some particular address. */
+ HOWTO (R_METAG_COPY, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_COPY", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Marks a procedure linkage table entry for a symbol. */
+ HOWTO (R_METAG_JMP_SLOT, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_JMP_SLOT", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Used only by the dynamic linker. When the object is run, this
+ longword is set to the load address of the object, plus the
+ addend. */
+ HOWTO (R_METAG_RELATIVE, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_RELATIVE", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_GLOB_DAT, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_GLOB_DAT", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_GD, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_GD", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_LDM, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_LDM", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_LDO_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_LDO_HI16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_LDO_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_LDO_LO16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Dummy reloc used by the linker internally. */
+ HOWTO (R_METAG_TLS_LDO, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_LDO", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_IE, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 12, /* bitsize */
+ FALSE, /* pc_relative */
+ 7, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_IE", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007ff80, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Dummy reloc used by the linker internally. */
+ HOWTO (R_METAG_TLS_IENONPIC, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_IENONPIC", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_IENONPIC_HI16,/* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_IENONPIC_HI16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_IENONPIC_LO16,/* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_IENONPIC_LO16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_TPOFF, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_TPOFF", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_DTPMOD, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_DTPMOD", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_DTPOFF, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_DTPOFF", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Dummy reloc used by the linker internally. */
+ HOWTO (R_METAG_TLS_LE, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_LE", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_LE_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_LE_HI16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_METAG_TLS_LE_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 3, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_METAG_TLS_LE_LO16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0007fff8, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+};
+
+#define BRANCH_BITS 19
+
+/* The GOT is typically accessed using a [GS]ETD instruction. The size of the
+ immediate offset which can be used in such instructions therefore limits
+ the usable size of the GOT. If the base register for the [GS]ETD (A1LbP)
+ is pointing to the base of the GOT then the size is limited to the maximum
+ 11 bits unsigned dword offset, or 2^13 = 0x2000 bytes. However the offset
+ in a [GS]ETD instruction is signed, so by setting the base address register
+ to an offset of that 0x2000 byte maximum unsigned offset from the base of
+ the GOT we can use negative offsets in addition to positive. This
+ effectively doubles the usable GOT size to 0x4000 bytes. */
+#define GOT_REG_OFFSET 0x2000
+
+struct metag_reloc_map
+{
+ bfd_reloc_code_real_type bfd_reloc_val;
+ unsigned int metag_reloc_val;
+};
+
+static const struct metag_reloc_map metag_reloc_map [] =
+ {
+ { BFD_RELOC_NONE, R_METAG_NONE },
+ { BFD_RELOC_32, R_METAG_ADDR32 },
+ { BFD_RELOC_METAG_HIADDR16, R_METAG_HIADDR16 },
+ { BFD_RELOC_METAG_LOADDR16, R_METAG_LOADDR16 },
+ { BFD_RELOC_METAG_RELBRANCH, R_METAG_RELBRANCH },
+ { BFD_RELOC_METAG_GETSETOFF, R_METAG_GETSETOFF },
+ { BFD_RELOC_VTABLE_INHERIT, R_METAG_GNU_VTINHERIT },
+ { BFD_RELOC_VTABLE_ENTRY, R_METAG_GNU_VTENTRY },
+ { BFD_RELOC_METAG_REL8, R_METAG_REL8 },
+ { BFD_RELOC_METAG_REL16, R_METAG_REL16 },
+ { BFD_RELOC_METAG_HI16_GOTOFF, R_METAG_HI16_GOTOFF },
+ { BFD_RELOC_METAG_LO16_GOTOFF, R_METAG_LO16_GOTOFF },
+ { BFD_RELOC_METAG_GETSET_GOTOFF, R_METAG_GETSET_GOTOFF },
+ { BFD_RELOC_METAG_GETSET_GOT, R_METAG_GETSET_GOT },
+ { BFD_RELOC_METAG_HI16_GOTPC, R_METAG_HI16_GOTPC },
+ { BFD_RELOC_METAG_LO16_GOTPC, R_METAG_LO16_GOTPC },
+ { BFD_RELOC_METAG_HI16_PLT, R_METAG_HI16_PLT },
+ { BFD_RELOC_METAG_LO16_PLT, R_METAG_LO16_PLT },
+ { BFD_RELOC_METAG_RELBRANCH_PLT, R_METAG_RELBRANCH_PLT },
+ { BFD_RELOC_METAG_GOTOFF, R_METAG_GOTOFF },
+ { BFD_RELOC_METAG_PLT, R_METAG_PLT },
+ { BFD_RELOC_METAG_COPY, R_METAG_COPY },
+ { BFD_RELOC_METAG_JMP_SLOT, R_METAG_JMP_SLOT },
+ { BFD_RELOC_METAG_RELATIVE, R_METAG_RELATIVE },
+ { BFD_RELOC_METAG_GLOB_DAT, R_METAG_GLOB_DAT },
+ { BFD_RELOC_METAG_TLS_GD, R_METAG_TLS_GD },
+ { BFD_RELOC_METAG_TLS_LDM, R_METAG_TLS_LDM },
+ { BFD_RELOC_METAG_TLS_LDO_HI16, R_METAG_TLS_LDO_HI16 },
+ { BFD_RELOC_METAG_TLS_LDO_LO16, R_METAG_TLS_LDO_LO16 },
+ { BFD_RELOC_METAG_TLS_LDO, R_METAG_TLS_LDO },
+ { BFD_RELOC_METAG_TLS_IE, R_METAG_TLS_IE },
+ { BFD_RELOC_METAG_TLS_IENONPIC, R_METAG_TLS_IENONPIC },
+ { BFD_RELOC_METAG_TLS_IENONPIC_HI16, R_METAG_TLS_IENONPIC_HI16 },
+ { BFD_RELOC_METAG_TLS_IENONPIC_LO16, R_METAG_TLS_IENONPIC_LO16 },
+ { BFD_RELOC_METAG_TLS_TPOFF, R_METAG_TLS_TPOFF },
+ { BFD_RELOC_METAG_TLS_DTPMOD, R_METAG_TLS_DTPMOD },
+ { BFD_RELOC_METAG_TLS_DTPOFF, R_METAG_TLS_DTPOFF },
+ { BFD_RELOC_METAG_TLS_LE, R_METAG_TLS_LE },
+ { BFD_RELOC_METAG_TLS_LE_HI16, R_METAG_TLS_LE_HI16 },
+ { BFD_RELOC_METAG_TLS_LE_LO16, R_METAG_TLS_LE_LO16 },
+ };
+
+enum elf_metag_stub_type
+{
+ metag_stub_long_branch,
+ metag_stub_long_branch_shared,
+ metag_stub_none
+};
+
+struct elf_metag_stub_hash_entry
+{
+ /* Base hash table entry structure. */
+ struct bfd_hash_entry bh_root;
+
+ /* The stub section. */
+ asection *stub_sec;
+
+ /* Offset within stub_sec of the beginning of this stub. */
+ bfd_vma stub_offset;
+
+ /* Given the symbol's value and its section we can determine its final
+ value when building the stubs (so the stub knows where to jump. */
+ bfd_vma target_value;
+ asection *target_section;
+
+ enum elf_metag_stub_type stub_type;
+
+ /* The symbol table entry, if any, that this was derived from. */
+ struct elf_metag_link_hash_entry *hh;
+
+ /* And the reloc addend that this was derived from. */
+ bfd_vma addend;
+
+ /* Where this stub is being called from, or, in the case of combined
+ stub sections, the first input section in the group. */
+ asection *id_sec;
+};
+
+struct elf_metag_link_hash_entry
+{
+ struct elf_link_hash_entry eh;
+
+ /* A pointer to the most recently used stub hash entry against this
+ symbol. */
+ struct elf_metag_stub_hash_entry *hsh_cache;
+
+ /* Used to count relocations for delayed sizing of relocation
+ sections. */
+ struct elf_metag_dyn_reloc_entry {
+
+ /* Next relocation in the chain. */
+ struct elf_metag_dyn_reloc_entry *hdh_next;
+
+ /* The input section of the reloc. */
+ asection *sec;
+
+ /* Number of relocs copied in this section. */
+ bfd_size_type count;
+
+ /* Number of relative relocs copied for the input section. */
+ bfd_size_type relative_count;
+ } *dyn_relocs;
+
+ enum
+ {
+ GOT_UNKNOWN = 0, GOT_NORMAL = 1, GOT_TLS_IE = 2, GOT_TLS_LDM = 4, GOT_TLS_GD = 8
+ } tls_type;
+};
+
+struct elf_metag_link_hash_table
+{
+ /* The main hash table. */
+ struct elf_link_hash_table etab;
+
+ /* The stub hash table. */
+ struct bfd_hash_table bstab;
+
+ /* Linker stub bfd. */
+ bfd *stub_bfd;
+
+ /* Linker call-backs. */
+ asection * (*add_stub_section) (const char *, asection *);
+ void (*layout_sections_again) (void);
+
+ /* Array to keep track of which stub sections have been created, and
+ information on stub grouping. */
+ struct map_stub
+ {
+ /* This is the section to which stubs in the group will be
+ attached. */
+ asection *link_sec;
+ /* The stub section. */
+ asection *stub_sec;
+ } *stub_group;
+
+ /* Assorted information used by elf_metag_size_stubs. */
+ unsigned int bfd_count;
+ int top_index;
+ asection **input_list;
+ Elf_Internal_Sym **all_local_syms;
+
+ /* Short-cuts to get to dynamic linker sections. */
+ asection *sgot;
+ asection *sgotplt;
+ asection *srelgot;
+ asection *splt;
+ asection *srelplt;
+ asection *sdynbss;
+ asection *srelbss;
+
+ /* Small local sym cache. */
+ struct sym_cache sym_cache;
+
+ /* Data for LDM relocations. */
+ union
+ {
+ bfd_signed_vma refcount;
+ bfd_vma offset;
+ } tls_ldm_got;
+};
+
+/* Return the base vma address which should be subtracted from the
+ real address when resolving a dtpoff relocation. This is PT_TLS
+ segment p_vaddr. */
+static bfd_vma
+dtpoff_base (struct bfd_link_info *info)
+{
+ /* If tls_sec is NULL, we should have signalled an error already. */
+ if (elf_hash_table (info)->tls_sec == NULL)
+ return 0;
+ return elf_hash_table (info)->tls_sec->vma;
+}
+
+/* Return the relocation value for R_METAG_TLS_IE */
+static bfd_vma
+tpoff (struct bfd_link_info *info, bfd_vma address)
+{
+ /* If tls_sec is NULL, we should have signalled an error already. */
+ if (elf_hash_table (info)->tls_sec == NULL)
+ return 0;
+ /* METAG TLS ABI is variant I and static TLS blocks start just after
+ tcbhead structure which has 2 pointer fields. */
+ return (address - elf_hash_table (info)->tls_sec->vma
+ + align_power ((bfd_vma) 8,
+ elf_hash_table (info)->tls_sec->alignment_power));
+}
+
+static void
+metag_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ arelent *cache_ptr,
+ Elf_Internal_Rela *dst)
+{
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+ BFD_ASSERT (r_type < (unsigned int) R_METAG_MAX);
+ cache_ptr->howto = & elf_metag_howto_table [r_type];
+}
+
+static reloc_howto_type *
+metag_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
+{
+ unsigned int i;
+
+ for (i = 0; i < sizeof (metag_reloc_map) / sizeof (metag_reloc_map[0]); i++)
+ if (metag_reloc_map [i].bfd_reloc_val == code)
+ return & elf_metag_howto_table [metag_reloc_map[i].metag_reloc_val];
+
+ return NULL;
+}
+
+static reloc_howto_type *
+metag_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ const char *r_name)
+{
+ unsigned int i;
+
+ for (i = 0; i < sizeof (elf_metag_howto_table) / sizeof (elf_metag_howto_table[0]); i++)
+ if (elf_metag_howto_table[i].name != NULL
+ && strcasecmp (elf_metag_howto_table[i].name, r_name) == 0)
+ return &elf_metag_howto_table[i];
+
+ return NULL;
+}
+
+/* Various hash macros and functions. */
+#define metag_link_hash_table(p) \
+ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
+ == METAG_ELF_DATA ? ((struct elf_metag_link_hash_table *) ((p)->hash)) : NULL)
+
+#define metag_elf_hash_entry(ent) \
+ ((struct elf_metag_link_hash_entry *)(ent))
+
+#define metag_stub_hash_entry(ent) \
+ ((struct elf_metag_stub_hash_entry *)(ent))
+
+#define metag_stub_hash_lookup(table, string, create, copy) \
+ ((struct elf_metag_stub_hash_entry *) \
+ bfd_hash_lookup ((table), (string), (create), (copy)))
+
+#define metag_elf_local_got_tls_type(abfd) \
+ ((char *)(elf_local_got_offsets (abfd) + (elf_tdata (abfd)->symtab_hdr.sh_info)))
+
+/* Assorted hash table functions. */
+
+/* Initialize an entry in the stub hash table. */
+
+static struct bfd_hash_entry *
+stub_hash_newfunc (struct bfd_hash_entry *entry,
+ struct bfd_hash_table *table,
+ const char *string)
+{
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (entry == NULL)
+ {
+ entry = bfd_hash_allocate (table,
+ sizeof (struct elf_metag_stub_hash_entry));
+ if (entry == NULL)
+ return entry;
+ }
+
+ /* Call the allocation method of the superclass. */
+ entry = bfd_hash_newfunc (entry, table, string);
+ if (entry != NULL)
+ {
+ struct elf_metag_stub_hash_entry *hsh;
+
+ /* Initialize the local fields. */
+ hsh = (struct elf_metag_stub_hash_entry *) entry;
+ hsh->stub_sec = NULL;
+ hsh->stub_offset = 0;
+ hsh->target_value = 0;
+ hsh->target_section = NULL;
+ hsh->stub_type = metag_stub_long_branch;
+ hsh->hh = NULL;
+ hsh->id_sec = NULL;
+ }
+
+ return entry;
+}
+
+/* Initialize an entry in the link hash table. */
+
+static struct bfd_hash_entry *
+metag_link_hash_newfunc (struct bfd_hash_entry *entry,
+ struct bfd_hash_table *table,
+ const char *string)
+{
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (entry == NULL)
+ {
+ entry = bfd_hash_allocate (table,
+ sizeof (struct elf_metag_link_hash_entry));
+ if (entry == NULL)
+ return entry;
+ }
+
+ /* Call the allocation method of the superclass. */
+ entry = _bfd_elf_link_hash_newfunc (entry, table, string);
+ if (entry != NULL)
+ {
+ struct elf_metag_link_hash_entry *hh;
+
+ /* Initialize the local fields. */
+ hh = (struct elf_metag_link_hash_entry *) entry;
+ hh->hsh_cache = NULL;
+ hh->dyn_relocs = NULL;
+ hh->tls_type = GOT_UNKNOWN;
+ }
+
+ return entry;
+}
+
+/* Create the derived linker hash table. The Meta ELF port uses the derived
+ hash table to keep information specific to the Meta ELF linker (without
+ using static variables). */
+
+static struct bfd_link_hash_table *
+elf_metag_link_hash_table_create (bfd *abfd)
+{
+ struct elf_metag_link_hash_table *htab;
+ bfd_size_type amt = sizeof (*htab);
+
+ htab = bfd_malloc (amt);
+ if (htab == NULL)
+ return NULL;
+
+ if (!_bfd_elf_link_hash_table_init (&htab->etab, abfd,
+ metag_link_hash_newfunc,
+ sizeof (struct elf_metag_link_hash_entry),
+ METAG_ELF_DATA))
+ {
+ free (htab);
+ return NULL;
+ }
+
+ /* Init the stub hash table too. */
+ if (!bfd_hash_table_init (&htab->bstab, stub_hash_newfunc,
+ sizeof (struct elf_metag_stub_hash_entry)))
+ return NULL;
+
+ htab->stub_bfd = NULL;
+ htab->add_stub_section = NULL;
+ htab->layout_sections_again = NULL;
+ htab->stub_group = NULL;
+ htab->sgot = NULL;
+ htab->sgotplt = NULL;
+ htab->srelgot = NULL;
+ htab->splt = NULL;
+ htab->srelplt = NULL;
+ htab->sdynbss = NULL;
+ htab->srelbss = NULL;
+ htab->sym_cache.abfd = NULL;
+ htab->tls_ldm_got.refcount = 0;
+
+ return &htab->etab.root;
+}
+
+/* Free the derived linker hash table. */
+
+static void
+elf_metag_link_hash_table_free (struct bfd_link_hash_table *btab)
+{
+ struct elf_metag_link_hash_table *htab
+ = (struct elf_metag_link_hash_table *) btab;
+
+ bfd_hash_table_free (&htab->bstab);
+ _bfd_generic_link_hash_table_free (btab);
+}
+
+/* Section name for stubs is the associated section name plus this
+ string. */
+#define STUB_SUFFIX ".stub"
+
+/* Build a name for an entry in the stub hash table. */
+
+static char *
+metag_stub_name (const asection *input_section,
+ const asection *sym_sec,
+ const struct elf_metag_link_hash_entry *hh,
+ const Elf_Internal_Rela *rel)
+{
+ char *stub_name;
+ bfd_size_type len;
+
+ if (hh)
+ {
+ len = 8 + 1 + strlen (hh->eh.root.root.string) + 1 + 8 + 1;
+ stub_name = bfd_malloc (len);
+ if (stub_name != NULL)
+ {
+ sprintf (stub_name, "%08x_%s+%x",
+ input_section->id & 0xffffffff,
+ hh->eh.root.root.string,
+ (int) rel->r_addend & 0xffffffff);
+ }
+ }
+ else
+ {
+ len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1;
+ stub_name = bfd_malloc (len);
+ if (stub_name != NULL)
+ {
+ sprintf (stub_name, "%08x_%x:%x+%x",
+ input_section->id & 0xffffffff,
+ sym_sec->id & 0xffffffff,
+ (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
+ (int) rel->r_addend & 0xffffffff);
+ }
+ }
+ return stub_name;
+}
+
+/* Look up an entry in the stub hash. Stub entries are cached because
+ creating the stub name takes a bit of time. */
+
+static struct elf_metag_stub_hash_entry *
+metag_get_stub_entry (const asection *input_section,
+ const asection *sym_sec,
+ struct elf_metag_link_hash_entry *hh,
+ const Elf_Internal_Rela *rel,
+ struct elf_metag_link_hash_table *htab)
+{
+ struct elf_metag_stub_hash_entry *hsh;
+ const asection *id_sec;
+
+ /* If this input section is part of a group of sections sharing one
+ stub section, then use the id of the first section in the group.
+ Stub names need to include a section id, as there may well be
+ more than one stub used to reach say, printf, and we need to
+ distinguish between them. */
+ id_sec = htab->stub_group[input_section->id].link_sec;
+
+ if (hh != NULL && hh->hsh_cache != NULL
+ && hh->hsh_cache->hh == hh
+ && hh->hsh_cache->id_sec == id_sec)
+ {
+ hsh = hh->hsh_cache;
+ }
+ else
+ {
+ char *stub_name;
+
+ stub_name = metag_stub_name (id_sec, sym_sec, hh, rel);
+ if (stub_name == NULL)
+ return NULL;
+
+ hsh = metag_stub_hash_lookup (&htab->bstab,
+ stub_name, FALSE, FALSE);
+
+ if (hh != NULL)
+ hh->hsh_cache = hsh;
+
+ free (stub_name);
+ }
+
+ return hsh;
+}
+
+/* Add a new stub entry to the stub hash. Not all fields of the new
+ stub entry are initialised. */
+
+static struct elf_metag_stub_hash_entry *
+metag_add_stub (const char *stub_name,
+ asection *section,
+ struct elf_metag_link_hash_table *htab)
+{
+ asection *link_sec;
+ asection *stub_sec;
+ struct elf_metag_stub_hash_entry *hsh;
+
+ link_sec = htab->stub_group[section->id].link_sec;
+ stub_sec = htab->stub_group[section->id].stub_sec;
+ if (stub_sec == NULL)
+ {
+ stub_sec = htab->stub_group[link_sec->id].stub_sec;
+ if (stub_sec == NULL)
+ {
+ size_t namelen;
+ bfd_size_type len;
+ char *s_name;
+
+ namelen = strlen (link_sec->name);
+ len = namelen + sizeof (STUB_SUFFIX);
+ s_name = bfd_alloc (htab->stub_bfd, len);
+ if (s_name == NULL)
+ return NULL;
+
+ memcpy (s_name, link_sec->name, namelen);
+ memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
+
+ stub_sec = (*htab->add_stub_section) (s_name, link_sec);
+ if (stub_sec == NULL)
+ return NULL;
+ htab->stub_group[link_sec->id].stub_sec = stub_sec;
+ }
+ htab->stub_group[section->id].stub_sec = stub_sec;
+ }
+
+ /* Enter this entry into the linker stub hash table. */
+ hsh = metag_stub_hash_lookup (&htab->bstab, stub_name,
+ TRUE, FALSE);
+ if (hsh == NULL)
+ {
+ (*_bfd_error_handler) (_("%B: cannot create stub entry %s"),
+ section->owner,
+ stub_name);
+ return NULL;
+ }
+
+ hsh->stub_sec = stub_sec;
+ hsh->stub_offset = 0;
+ hsh->id_sec = link_sec;
+ return hsh;
+}
+
+/* Check a signed integer value can be represented in the given number
+ of bits. */
+
+static bfd_boolean
+within_signed_range (int value, unsigned int bits)
+{
+ int min_val = -(1 << (bits - 1));
+ int max_val = (1 << (bits - 1)) - 1;
+ return (value <= max_val) && (value >= min_val);
+}
+
+/* Perform a relocation as part of a final link. */
+
+static bfd_reloc_status_type
+metag_final_link_relocate (reloc_howto_type *howto,
+ bfd *input_bfd,
+ asection *input_section,
+ bfd_byte *contents,
+ Elf_Internal_Rela *rel,
+ bfd_vma relocation,
+ struct elf_metag_link_hash_entry *hh,
+ struct elf_metag_link_hash_table *htab,
+ asection *sym_sec)
+{
+ bfd_reloc_status_type r = bfd_reloc_ok;
+ bfd_byte *hit_data = contents + rel->r_offset;
+ int opcode, op_shift, op_extended, l1, l2;
+ bfd_signed_vma srel, addend = rel->r_addend;
+ struct elf_metag_stub_hash_entry *hsh = NULL;
+ bfd_vma location;
+
+ /* Find out where we are and where we're going. */
+ location = (rel->r_offset +
+ input_section->output_offset +
+ input_section->output_section->vma);
+
+ switch (howto->type)
+ {
+ case R_METAG_RELBRANCH:
+ case R_METAG_RELBRANCH_PLT:
+ /* Make it a pc relative offset. */
+ relocation -= location;
+ break;
+ case R_METAG_TLS_GD:
+ case R_METAG_TLS_IE:
+ relocation -= elf_gp (input_section->output_section->owner);
+ break;
+ default:
+ break;
+ }
+
+ switch (howto->type)
+ {
+ case R_METAG_RELBRANCH_PLT:
+ case R_METAG_RELBRANCH:
+ opcode = bfd_get_32 (input_bfd, hit_data);
+
+ srel = (bfd_signed_vma) relocation;
+ srel += addend;
+
+ /* If the branch is out of reach, then redirect the
+ call to the local stub for this function. */
+ if (srel > ((1 << (BRANCH_BITS + 1)) - 1) ||
+ (srel < - (1 << (BRANCH_BITS + 1))))
+ {
+ if (sym_sec == NULL)
+ break;
+
+ hsh = metag_get_stub_entry (input_section, sym_sec,
+ hh, rel, htab);
+ if (hsh == NULL)
+ return bfd_reloc_undefined;
+
+ /* Munge up the value and addend so that we call the stub
+ rather than the procedure directly. */
+ srel = (hsh->stub_offset
+ + hsh->stub_sec->output_offset
+ + hsh->stub_sec->output_section->vma);
+ srel -= location;
+ }
+
+ srel = srel >> 2;
+
+ if (!within_signed_range (srel, BRANCH_BITS))
+ {
+ if (hh && hh->eh.root.type == bfd_link_hash_undefweak)
+ srel = 0;
+ else
+ return bfd_reloc_overflow;
+ }
+
+ opcode &= ~(0x7ffff << 5);
+ opcode |= ((srel & 0x7ffff) << 5);
+
+ bfd_put_32 (input_bfd, opcode, hit_data);
+ break;
+ case R_METAG_GETSETOFF:
+ case R_METAG_GETSET_GOT:
+ case R_METAG_GETSET_GOTOFF:
+ opcode = bfd_get_32 (input_bfd, hit_data);
+
+ srel = (bfd_signed_vma) relocation;
+ srel += addend;
+
+ /* Is this a standard or extended GET/SET? */
+ if ((opcode & 0xf0000000) == 0xa0000000)
+ {
+ /* Extended GET/SET. */
+ l1 = opcode & 0x2;
+ l2 = opcode & 0x4;
+ op_extended = 1;
+ }
+ else
+ {
+ /* Standard GET/SET. */
+ l1 = opcode & 0x01000000;
+ l2 = opcode & 0x04000000;
+ op_extended = 0;
+ }
+
+ /* Calculate the width of the GET/SET and how much we need to
+ shift the result by. */
+ if (l2)
+ if (l1)
+ op_shift = 3;
+ else
+ op_shift = 2;
+ else
+ if (l1)
+ op_shift = 1;
+ else
+ op_shift = 0;
+
+ /* GET/SET offsets are scaled by the width of the transfer. */
+ srel = srel >> op_shift;
+
+ /* Extended GET/SET has signed 12 bits of offset, standard has
+ signed 6 bits. */
+ if (op_extended)
+ {
+ if (!within_signed_range (srel, 12))
+ {
+ if (hh && hh->eh.root.type == bfd_link_hash_undefweak)
+ srel = 0;
+ else
+ return bfd_reloc_overflow;
+ }
+ opcode &= ~(0xfff << 7);
+ opcode |= ((srel & 0xfff) << 7);
+ }
+ else
+ {
+ if (!within_signed_range (srel, 5))
+ {
+ if (hh && hh->eh.root.type == bfd_link_hash_undefweak)
+ srel = 0;
+ else
+ return bfd_reloc_overflow;
+ }
+ opcode &= ~(0x3f << 8);
+ opcode |= ((srel & 0x3f) << 8);
+ }
+
+ bfd_put_32 (input_bfd, opcode, hit_data);
+ break;
+ case R_METAG_TLS_GD:
+ case R_METAG_TLS_LDM:
+ opcode = bfd_get_32 (input_bfd, hit_data);
+
+ if ((bfd_signed_vma)relocation < 0)
+ {
+ /* sign extend immediate */
+ if ((opcode & 0xf2000001) == 0x02000000)
+ {
+ /* ADD De.e,Dx.r,#I16 */
+ /* set SE bit */
+ opcode |= (1 << 1);
+ } else
+ return bfd_reloc_overflow;
+ }
+
+ bfd_put_32 (input_bfd, opcode, hit_data);
+
+ r = _bfd_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel->r_offset,
+ relocation, rel->r_addend);
+ break;
+ default:
+ r = _bfd_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel->r_offset,
+ relocation, rel->r_addend);
+ }
+
+ return r;
+}
+
+/* This is defined because R_METAG_NONE != 0...
+ See RELOC_AGAINST_DISCARDED_SECTION for details. */
+#define METAG_RELOC_AGAINST_DISCARDED_SECTION(info, input_bfd, input_section, \
+ rel, relend, howto, contents) \
+ { \
+ _bfd_clear_contents (howto, input_bfd, input_section, \
+ contents + rel->r_offset); \
+ \
+ if (info->relocatable \
+ && (input_section->flags & SEC_DEBUGGING)) \
+ { \
+ /* Only remove relocations in debug sections since other \
+ sections may require relocations. */ \
+ Elf_Internal_Shdr *rel_hdr; \
+ \
+ rel_hdr = _bfd_elf_single_rel_hdr (input_section->output_section); \
+ \
+ /* Avoid empty output section. */ \
+ if (rel_hdr->sh_size > rel_hdr->sh_entsize) \
+ { \
+ rel_hdr->sh_size -= rel_hdr->sh_entsize; \
+ rel_hdr = _bfd_elf_single_rel_hdr (input_section); \
+ rel_hdr->sh_size -= rel_hdr->sh_entsize; \
+ \
+ memmove (rel, rel + 1, (relend - rel) * sizeof (*rel)); \
+ \
+ input_section->reloc_count--; \
+ relend--; \
+ rel--; \
+ continue; \
+ } \
+ } \
+ \
+ rel->r_info = R_METAG_NONE; \
+ rel->r_addend = 0; \
+ continue; \
+ }
+
+/* Relocate a META ELF section.
+
+The RELOCATE_SECTION function is called by the new ELF backend linker
+to handle the relocations for a section.
+
+The relocs are always passed as Rela structures; if the section
+actually uses Rel structures, the r_addend field will always be
+zero.
+
+This function is responsible for adjusting the section contents as
+necessary, and (if using Rela relocs and generating a relocatable
+output file) adjusting the reloc addend as necessary.
+
+This function does not have to worry about setting the reloc
+address or the reloc symbol index.
+
+LOCAL_SYMS is a pointer to the swapped in local symbols.
+
+LOCAL_SECTIONS is an array giving the section in the input file
+corresponding to the st_shndx field of each local symbol.
+
+The global hash table entry for the global symbols can be found
+via elf_sym_hashes (input_bfd).
+
+When generating relocatable output, this function must handle
+STB_LOCAL/STT_SECTION symbols specially. The output symbol is
+going to be the section symbol corresponding to the output
+section, which means that the addend must be adjusted
+accordingly. */
+
+static bfd_boolean
+elf_metag_relocate_section (bfd *output_bfd,
+ struct bfd_link_info *info,
+ bfd *input_bfd,
+ asection *input_section,
+ bfd_byte *contents,
+ Elf_Internal_Rela *relocs,
+ Elf_Internal_Sym *local_syms,
+ asection **local_sections)
+{
+ bfd_vma *local_got_offsets;
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **eh_syms;
+ struct elf_metag_link_hash_table *htab;
+ Elf_Internal_Rela *rel;
+ Elf_Internal_Rela *relend;
+ asection *sreloc;
+
+ symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
+ eh_syms = elf_sym_hashes (input_bfd);
+ relend = relocs + input_section->reloc_count;
+
+ htab = metag_link_hash_table (info);
+ local_got_offsets = elf_local_got_offsets (input_bfd);
+
+ sreloc = NULL;
+
+ for (rel = relocs; rel < relend; rel ++)
+ {
+ reloc_howto_type *howto;
+ unsigned long r_symndx;
+ Elf_Internal_Sym *sym;
+ asection *sec;
+ struct elf_metag_link_hash_entry *hh;
+ bfd_vma relocation;
+ bfd_reloc_status_type r;
+ const char *name;
+ int r_type;
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+
+ if (r_type == R_METAG_GNU_VTINHERIT
+ || r_type == R_METAG_GNU_VTENTRY
+ || r_type == R_METAG_NONE)
+ continue;
+
+ r_symndx = ELF32_R_SYM (rel->r_info);
+
+ howto = elf_metag_howto_table + ELF32_R_TYPE (rel->r_info);
+ hh = NULL;
+ sym = NULL;
+ sec = NULL;
+
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ sec = local_sections [r_symndx];
+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+
+ name = bfd_elf_string_from_elf_section
+ (input_bfd, symtab_hdr->sh_link, sym->st_name);
+ name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name;
+ }
+ else
+ {
+ struct elf_link_hash_entry *eh;
+ bfd_boolean unresolved_reloc, warned;
+
+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ r_symndx, symtab_hdr, eh_syms,
+ eh, sec, relocation,
+ unresolved_reloc, warned);
+
+ name = eh->root.root.string;
+ hh = (struct elf_metag_link_hash_entry *) eh;
+ }
+
+ if (sec != NULL && discarded_section (sec))
+ METAG_RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
+ rel, relend, howto, contents);
+
+ if (info->relocatable)
+ continue;
+
+ switch (r_type)
+ {
+ case R_METAG_ADDR32:
+ case R_METAG_RELBRANCH:
+ if ((input_section->flags & SEC_ALLOC) == 0)
+ break;
+
+ if ((info->shared
+ && r_symndx != STN_UNDEF
+ && (input_section->flags & SEC_ALLOC) != 0
+ && (r_type != R_METAG_RELBRANCH
+ || !SYMBOL_CALLS_LOCAL (info, &hh->eh)))
+ || (!info->shared
+ && hh != NULL
+ && hh->eh.dynindx != -1
+ && !hh->eh.non_got_ref
+ && ((hh->eh.def_dynamic
+ && !hh->eh.def_regular)
+ || hh->eh.root.type == bfd_link_hash_undefweak
+ || hh->eh.root.type == bfd_link_hash_undefined)))
+ {
+ Elf_Internal_Rela outrel;
+ bfd_boolean skip, relocate;
+ bfd_byte *loc;
+
+ /* When generating a shared object, these relocations
+ are copied into the output file to be resolved at run
+ time. */
+
+ sreloc = elf_section_data (input_section)->sreloc;
+ BFD_ASSERT (sreloc != NULL);
+
+ skip = FALSE;
+ relocate = FALSE;
+
+ outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+ info,
+ input_section,
+ rel->r_offset);
+ if (outrel.r_offset == (bfd_vma) -1)
+ skip = TRUE;
+ else if (outrel.r_offset == (bfd_vma) -2)
+ skip = TRUE, relocate = TRUE;
+ outrel.r_offset += (input_section->output_section->vma
+ + input_section->output_offset);
+
+ if (skip)
+ {
+ memset (&outrel, 0, sizeof outrel);
+ outrel.r_info = ELF32_R_INFO (0, R_METAG_NONE);
+ }
+ else if (r_type == R_METAG_RELBRANCH)
+ {
+ BFD_ASSERT (hh != NULL && hh->eh.dynindx != -1);
+ outrel.r_info = ELF32_R_INFO (hh->eh.dynindx, r_type);
+ outrel.r_addend = rel->r_addend;
+ }
+ else
+ {
+ /* h->dynindx may be -1 if this symbol was marked to
+ become local. */
+ if (hh == NULL
+ || ((info->symbolic || hh->eh.dynindx == -1)
+ && hh->eh.def_regular))
+ {
+ relocate = TRUE;
+ outrel.r_info = ELF32_R_INFO (0, R_METAG_RELATIVE);
+ outrel.r_addend = relocation + rel->r_addend;
+ }
+ else
+ {
+ BFD_ASSERT (hh->eh.dynindx != -1);
+ outrel.r_info = ELF32_R_INFO (hh->eh.dynindx, r_type);
+ outrel.r_addend = rel->r_addend;
+ }
+ }
+
+ loc = sreloc->contents;
+ loc += sreloc->reloc_count * sizeof(Elf32_External_Rela);
+ bfd_elf32_swap_reloca_out (output_bfd, &outrel,loc);
+ ++sreloc->reloc_count;
+
+ /* If this reloc is against an external symbol, we do
+ not want to fiddle with the addend. Otherwise, we
+ need to include the symbol value so that it becomes
+ an addend for the dynamic reloc. */
+ if (! relocate)
+ continue;
+ }
+ break;
+
+ case R_METAG_RELBRANCH_PLT:
+ /* Relocation is to the entry for this symbol in the
+ procedure linkage table. */
+
+ if (hh == NULL)
+ break;
+
+ if (hh->eh.forced_local)
+ break;
+
+ if (hh->eh.plt.offset == (bfd_vma) -1 ||
+ htab->splt == NULL)
+ {
+ /* We didn't make a PLT entry for this symbol. This
+ happens when statically linking PIC code, or when
+ using -Bsymbolic. */
+ break;
+ }
+
+ relocation = (htab->splt->output_section->vma
+ + htab->splt->output_offset
+ + hh->eh.plt.offset);
+ break;
+ case R_METAG_HI16_GOTPC:
+ case R_METAG_LO16_GOTPC:
+ BFD_ASSERT (htab->sgot != NULL);
+
+ relocation = (htab->sgot->output_section->vma +
+ htab->sgot->output_offset);
+ relocation += GOT_REG_OFFSET;
+ relocation -= (input_section->output_section->vma
+ + input_section->output_offset
+ + rel->r_offset);
+ break;
+ case R_METAG_HI16_GOTOFF:
+ case R_METAG_LO16_GOTOFF:
+ case R_METAG_GETSET_GOTOFF:
+ BFD_ASSERT (htab->sgot != NULL);
+
+ relocation -= (htab->sgot->output_section->vma +
+ htab->sgot->output_offset);
+ relocation -= GOT_REG_OFFSET;
+ break;
+ case R_METAG_GETSET_GOT:
+ {
+ bfd_vma off;
+ bfd_boolean do_got = 0;
+
+ /* Relocation is to the entry for this symbol in the
+ global offset table. */
+ if (hh != NULL)
+ {
+ bfd_boolean dyn;
+
+ off = hh->eh.got.offset;
+ dyn = htab->etab.dynamic_sections_created;
+ if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared,
+ &hh->eh))
+ {
+ /* If we aren't going to call finish_dynamic_symbol,
+ then we need to handle initialisation of the .got
+ entry and create needed relocs here. Since the
+ offset must always be a multiple of 4, we use the
+ least significant bit to record whether we have
+ initialised it already. */
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ hh->eh.got.offset |= 1;
+ do_got = 1;
+ }
+ }
+ }
+ else
+ {
+ /* Local symbol case. */
+ if (local_got_offsets == NULL)
+ abort ();
+
+ off = local_got_offsets[r_symndx];
+
+ /* The offset must always be a multiple of 4. We use
+ the least significant bit to record whether we have
+ already generated the necessary reloc. */
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ local_got_offsets[r_symndx] |= 1;
+ do_got = 1;
+ }
+ }
+
+ if (do_got)
+ {
+ if (info->shared)
+ {
+ /* Output a dynamic relocation for this GOT entry.
+ In this case it is relative to the base of the
+ object because the symbol index is zero. */
+ Elf_Internal_Rela outrel;
+ bfd_byte *loc;
+ asection *s = htab->srelgot;
+
+ outrel.r_offset = (off
+ + htab->sgot->output_offset
+ + htab->sgot->output_section->vma);
+ outrel.r_info = ELF32_R_INFO (0, R_METAG_RELATIVE);
+ outrel.r_addend = relocation;
+ loc = s->contents;
+ loc += s->reloc_count++ * sizeof (Elf32_External_Rela);
+ bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+ }
+ else
+ bfd_put_32 (output_bfd, relocation,
+ htab->sgot->contents + off);
+ }
+
+ if (off >= (bfd_vma) -2)
+ abort ();
+
+ relocation = off - GOT_REG_OFFSET;
+ }
+ break;
+ case R_METAG_TLS_GD:
+ case R_METAG_TLS_IE:
+ {
+ /* XXXMJF There is room here for optimisations. For example
+ converting from GD->IE, etc. */
+ bfd_vma off;
+ int indx;
+ char tls_type;
+
+ if (htab->sgot == NULL)
+ abort();
+
+ indx = 0;
+ if (hh != NULL)
+ {
+ bfd_boolean dyn;
+ dyn = htab->etab.dynamic_sections_created;
+
+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, &hh->eh)
+ && (!info->shared
+ || !SYMBOL_REFERENCES_LOCAL (info, &hh->eh)))
+ {
+ indx = hh->eh.dynindx;
+ }
+ off = hh->eh.got.offset;
+ tls_type = hh->tls_type;
+ }
+ else
+ {
+ /* Local symbol case. */
+ if (local_got_offsets == NULL)
+ abort ();
+
+ off = local_got_offsets[r_symndx];
+ tls_type = metag_elf_local_got_tls_type (input_bfd) [r_symndx];
+ }
+
+ if (tls_type == GOT_UNKNOWN)
+ abort();
+
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ bfd_boolean need_relocs = FALSE;
+ Elf_Internal_Rela outrel;
+ bfd_byte *loc = NULL;
+ int cur_off = off;
+
+ /* The GOT entries have not been initialized yet. Do it
+ now, and emit any relocations. If both an IE GOT and a
+ GD GOT are necessary, we emit the GD first. */
+
+ if ((info->shared || indx != 0)
+ && (hh == NULL
+ || ELF_ST_VISIBILITY (hh->eh.other) == STV_DEFAULT
+ || hh->eh.root.type != bfd_link_hash_undefweak))
+ {
+ need_relocs = TRUE;
+ loc = htab->srelgot->contents;
+ /* FIXME (CAO): Should this be reloc_count++ ? */
+ loc += htab->srelgot->reloc_count * sizeof (Elf32_External_Rela);
+ }
+
+ if (tls_type & GOT_TLS_GD)
+ {
+ if (need_relocs)
+ {
+ outrel.r_offset = (cur_off
+ + htab->sgot->output_section->vma
+ + htab->sgot->output_offset);
+ outrel.r_info = ELF32_R_INFO (indx, R_METAG_TLS_DTPMOD);
+ outrel.r_addend = 0;
+ bfd_put_32 (output_bfd, 0, htab->sgot->contents + cur_off);
+
+ bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+ htab->srelgot->reloc_count++;
+ loc += sizeof (Elf32_External_Rela);
+
+ if (indx == 0)
+ bfd_put_32 (output_bfd, 0,
+ htab->sgot->contents + cur_off + 4);
+ else
+ {
+ bfd_put_32 (output_bfd, 0,
+ htab->sgot->contents + cur_off + 4);
+ outrel.r_info = ELF32_R_INFO (indx,
+ R_METAG_TLS_DTPOFF);
+ outrel.r_offset += 4;
+ bfd_elf32_swap_reloca_out (output_bfd,
+ &outrel, loc);
+ htab->srelgot->reloc_count++;
+ loc += sizeof (Elf32_External_Rela);
+ }
+ }
+ else
+ {
+ /* We don't support changing the TLS model. */
+ abort ();
+ }
+
+ cur_off += 8;
+ }
+
+ if (tls_type & GOT_TLS_IE)
+ {
+ if (need_relocs)
+ {
+ outrel.r_offset = (cur_off
+ + htab->sgot->output_section->vma
+ + htab->sgot->output_offset);
+ outrel.r_info = ELF32_R_INFO (indx, R_METAG_TLS_TPOFF);
+
+ if (indx == 0)
+ outrel.r_addend = relocation - dtpoff_base (info);
+ else
+ outrel.r_addend = 0;
+
+ bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+ htab->srelgot->reloc_count++;
+ loc += sizeof (Elf32_External_Rela);
+ }
+ else
+ bfd_put_32 (output_bfd, tpoff (info, relocation),
+ htab->sgot->contents + cur_off);
+
+ cur_off += 4;
+ }
+
+ if (hh != NULL)
+ hh->eh.got.offset |= 1;
+ else
+ local_got_offsets[r_symndx] |= 1;
+ }
+
+ /* Add the base of the GOT to the relocation value. */
+ relocation = off - GOT_REG_OFFSET;
+
+ break;
+ }
+
+ case R_METAG_TLS_IENONPIC_HI16:
+ case R_METAG_TLS_IENONPIC_LO16:
+ case R_METAG_TLS_LE_HI16:
+ case R_METAG_TLS_LE_LO16:
+ if (info->shared)
+ {
+ (*_bfd_error_handler)
+ (_("%B(%A+0x%lx): R_METAG_TLS_LE/IENONPIC relocation not permitted in shared object"),
+ input_bfd, input_section,
+ (long) rel->r_offset, howto->name);
+ return FALSE;
+ }
+ else
+ relocation = tpoff (info, relocation);
+ break;
+ case R_METAG_TLS_LDO_HI16:
+ case R_METAG_TLS_LDO_LO16:
+ if (! info->shared)
+ relocation = tpoff (info, relocation);
+ else
+ relocation -= dtpoff_base (info);
+ break;
+ case R_METAG_TLS_LDM:
+ {
+ bfd_vma off;
+
+ if (htab->sgot == NULL)
+ abort();
+ off = htab->tls_ldm_got.offset;
+ if (off & 1)
+ off &= ~1;
+ else
+ {
+ Elf_Internal_Rela outrel;
+ bfd_byte *loc;
+
+ outrel.r_offset = (off
+ + htab->sgot->output_section->vma
+ + htab->sgot->output_offset);
+
+ outrel.r_addend = 0;
+ outrel.r_info = ELF32_R_INFO (0, R_METAG_TLS_DTPMOD);
+ loc = htab->srelgot->contents;
+ loc += htab->srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
+ bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+ htab->tls_ldm_got.offset |= 1;
+ }
+
+ relocation = off - GOT_REG_OFFSET;
+ break;
+ }
+ default:
+ break;
+ }
+
+ r = metag_final_link_relocate (howto, input_bfd, input_section,
+ contents, rel, relocation, hh, htab,
+ sec);
+
+ if (r != bfd_reloc_ok)
+ {
+ const char * msg = (const char *) NULL;
+
+ switch (r)
+ {
+ case bfd_reloc_overflow:
+ r = info->callbacks->reloc_overflow
+ (info, (hh ? &hh->eh.root : NULL), name, howto->name,
+ (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
+ break;
+
+ case bfd_reloc_undefined:
+ r = info->callbacks->undefined_symbol
+ (info, name, input_bfd, input_section, rel->r_offset,
+ TRUE);
+ break;
+
+ case bfd_reloc_outofrange:
+ msg = _("internal error: out of range error");
+ break;
+
+ case bfd_reloc_notsupported:
+ msg = _("internal error: unsupported relocation error");
+ break;
+
+ case bfd_reloc_dangerous:
+ msg = _("internal error: dangerous relocation");
+ break;
+
+ default:
+ msg = _("internal error: unknown error");
+ break;
+ }
+
+ if (msg)
+ r = info->callbacks->warning
+ (info, msg, name, input_bfd, input_section, rel->r_offset);
+
+ if (! r)
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+/* Create the .plt and .got sections, and set up our hash table
+ short-cuts to various dynamic sections. */
+
+static bfd_boolean
+elf_metag_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
+{
+ struct elf_metag_link_hash_table *htab;
+ struct elf_link_hash_entry *eh;
+ struct bfd_link_hash_entry *bh;
+ const struct elf_backend_data *bed = get_elf_backend_data (abfd);
+
+ /* Don't try to create the .plt and .got twice. */
+ htab = metag_link_hash_table (info);
+ if (htab->splt != NULL)
+ return TRUE;
+
+ /* Call the generic code to do most of the work. */
+ if (! _bfd_elf_create_dynamic_sections (abfd, info))
+ return FALSE;
+
+ htab->sgot = bfd_get_section_by_name (abfd, ".got");
+ if (! htab->sgot)
+ return FALSE;
+
+ htab->sgotplt = bfd_make_section_with_flags (abfd, ".got.plt",
+ (SEC_ALLOC | SEC_LOAD |
+ SEC_HAS_CONTENTS |
+ SEC_IN_MEMORY |
+ SEC_LINKER_CREATED));
+ if (htab->sgotplt == NULL
+ || !bfd_set_section_alignment (abfd, htab->sgotplt, 2))
+ return FALSE;
+
+ /* Define the symbol __GLOBAL_OFFSET_TABLE__ at the start of the .got
+ section. We don't do this in the linker script because we don't want
+ to define the symbol if we are not creating a global offset table. */
+ bh = NULL;
+ if (!(_bfd_generic_link_add_one_symbol
+ (info, abfd, "__GLOBAL_OFFSET_TABLE__", BSF_GLOBAL, htab->sgot,
+ (bfd_vma) 0, NULL, FALSE, bed->collect, &bh)))
+ return FALSE;
+ eh = (struct elf_link_hash_entry *) bh;
+ eh->def_regular = 1;
+ eh->type = STT_OBJECT;
+ eh->other = STV_HIDDEN;
+
+ if (! info->executable
+ && ! bfd_elf_link_record_dynamic_symbol (info, eh))
+ return FALSE;
+
+ elf_hash_table (info)->hgot = eh;
+
+ htab->splt = bfd_get_section_by_name (abfd, ".plt");
+ htab->srelplt = bfd_get_section_by_name (abfd, ".rela.plt");
+
+ htab->srelgot = bfd_get_section_by_name (abfd, ".rela.got");
+
+ htab->sdynbss = bfd_get_section_by_name (abfd, ".dynbss");
+ htab->srelbss = bfd_get_section_by_name (abfd, ".rela.bss");
+
+ return TRUE;
+}
+
+/* Look through the relocs for a section during the first phase, and
+ calculate needed space in the global offset table, procedure linkage
+ table, and dynamic reloc sections. At this point we haven't
+ necessarily read all the input files. */
+
+static bfd_boolean
+elf_metag_check_relocs (bfd *abfd,
+ struct bfd_link_info *info,
+ asection *sec,
+ const Elf_Internal_Rela *relocs)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **eh_syms;
+ const Elf_Internal_Rela *rel;
+ const Elf_Internal_Rela *rel_end;
+ struct elf_metag_link_hash_table *htab;
+ asection *sreloc;
+ bfd *dynobj;
+ int tls_type = GOT_UNKNOWN, old_tls_type = GOT_UNKNOWN;
+
+ if (info->relocatable)
+ return TRUE;
+
+ htab = metag_link_hash_table (info);
+ dynobj = htab->etab.dynobj;
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ eh_syms = elf_sym_hashes (abfd);
+ sreloc = NULL;
+
+ if (htab == NULL)
+ return FALSE;
+
+ rel_end = relocs + sec->reloc_count;
+ for (rel = relocs; rel < rel_end; rel++)
+ {
+ int r_type;
+ struct elf_metag_link_hash_entry *hh;
+ unsigned long r_symndx;
+
+ r_symndx = ELF32_R_SYM (rel->r_info);
+ r_type = ELF32_R_TYPE (rel->r_info);
+ if (r_symndx < symtab_hdr->sh_info)
+ hh = NULL;
+ else
+ {
+ hh = (struct elf_metag_link_hash_entry *)
+ eh_syms[r_symndx - symtab_hdr->sh_info];
+ while (hh->eh.root.type == bfd_link_hash_indirect
+ || hh->eh.root.type == bfd_link_hash_warning)
+ hh = (struct elf_metag_link_hash_entry *) hh->eh.root.u.i.link;
+ }
+
+ /* Some relocs require a global offset table. */
+ if (htab->sgot == NULL)
+ {
+ switch (r_type)
+ {
+ case R_METAG_TLS_GD:
+ case R_METAG_TLS_LDM:
+ case R_METAG_TLS_IE:
+ if (info->shared)
+ info->flags |= DF_STATIC_TLS;
+ /* Fall through. */
+
+ case R_METAG_HI16_GOTOFF:
+ case R_METAG_LO16_GOTOFF:
+ case R_METAG_GETSET_GOTOFF:
+ case R_METAG_GETSET_GOT:
+ case R_METAG_HI16_GOTPC:
+ case R_METAG_LO16_GOTPC:
+ if (dynobj == NULL)
+ htab->etab.dynobj = dynobj = abfd;
+ if (!elf_metag_create_dynamic_sections (dynobj, info))
+ return FALSE;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ switch (r_type)
+ {
+ case R_METAG_TLS_IE:
+ case R_METAG_TLS_GD:
+ case R_METAG_GETSET_GOT:
+ switch (r_type)
+ {
+ default:
+ tls_type = GOT_NORMAL;
+ break;
+ case R_METAG_TLS_IE:
+ tls_type = GOT_TLS_IE;
+ break;
+ case R_METAG_TLS_GD:
+ tls_type = GOT_TLS_GD;
+ break;
+ }
+
+ if (hh != NULL)
+ {
+ hh->eh.got.refcount += 1;
+ old_tls_type = hh->tls_type;
+ }
+ else
+ {
+ bfd_signed_vma *local_got_refcounts;
+
+ /* This is a global offset table entry for a local
+ symbol. */
+ local_got_refcounts = elf_local_got_refcounts (abfd);
+ if (local_got_refcounts == NULL)
+ {
+ bfd_size_type size;
+
+ size = symtab_hdr->sh_info;
+ size *= sizeof (bfd_signed_vma);
+ /* Add in space to store the local GOT TLS types. */
+ size += symtab_hdr->sh_info;
+ local_got_refcounts = ((bfd_signed_vma *)
+ bfd_zalloc (abfd, size));
+ if (local_got_refcounts == NULL)
+ return FALSE;
+ elf_local_got_refcounts (abfd) = local_got_refcounts;
+ memset (metag_elf_local_got_tls_type (abfd),
+ GOT_UNKNOWN, symtab_hdr->sh_info);
+ }
+ local_got_refcounts[r_symndx] += 1;
+ old_tls_type = metag_elf_local_got_tls_type (abfd) [r_symndx];
+ }
+
+ if (old_tls_type != tls_type)
+ {
+ if (hh != NULL)
+ {
+ hh->tls_type = tls_type;
+ }
+ else
+ {
+ metag_elf_local_got_tls_type (abfd) [r_symndx] = tls_type;
+ }
+ }
+
+ break;
+
+ case R_METAG_TLS_LDM:
+ metag_link_hash_table (info)->tls_ldm_got.refcount += 1;
+ break;
+
+ case R_METAG_RELBRANCH_PLT:
+ /* This symbol requires a procedure linkage table entry. We
+ actually build the entry in adjust_dynamic_symbol,
+ because this might be a case of linking PIC code without
+ linking in any dynamic objects, in which case we don't
+ need to generate a procedure linkage table after all. */
+
+ /* If this is a local symbol, we resolve it directly without
+ creating a procedure linkage table entry. */
+ if (hh == NULL)
+ continue;
+
+ if (hh->eh.forced_local)
+ break;
+
+ hh->eh.needs_plt = 1;
+ hh->eh.plt.refcount += 1;
+ break;
+
+ case R_METAG_ADDR32:
+ case R_METAG_HIADDR16:
+ case R_METAG_LOADDR16:
+ case R_METAG_RELBRANCH:
+ case R_METAG_GETSETOFF:
+ if (hh != NULL && !info->shared)
+ {
+ hh->eh.non_got_ref = 1;
+ hh->eh.plt.refcount += 1;
+ }
+
+ /* If we are creating a shared library, and this is a reloc
+ against a global symbol, or a non PC relative reloc
+ against a local symbol, then we need to copy the reloc
+ into the shared library. However, if we are linking with
+ -Bsymbolic, we do not need to copy a reloc against a
+ global symbol which is defined in an object we are
+ including in the link (i.e., DEF_REGULAR is set). At
+ this point we have not seen all the input files, so it is
+ possible that DEF_REGULAR is not set now but will be set
+ later (it is never cleared). We account for that
+ possibility below by storing information in the
+ dyn_relocs field of the hash table entry. A similar
+ situation occurs when creating shared libraries and symbol
+ visibility changes render the symbol local.
+
+ If on the other hand, we are creating an executable, we
+ may need to keep relocations for symbols satisfied by a
+ dynamic library if we manage to avoid copy relocs for the
+ symbol. */
+ if ((info->shared
+ && (sec->flags & SEC_ALLOC) != 0
+ && (r_type != R_METAG_RELBRANCH
+ || (hh != NULL
+ && (! info->symbolic
+ || hh->eh.root.type == bfd_link_hash_defweak
+ || !hh->eh.def_regular))))
+ || (!info->shared
+ && (sec->flags & SEC_ALLOC) != 0
+ && hh != NULL
+ && (hh->eh.root.type == bfd_link_hash_defweak
+ || !hh->eh.def_regular)))
+ {
+ struct elf_metag_dyn_reloc_entry *hdh_p;
+ struct elf_metag_dyn_reloc_entry **hdh_head;
+
+ if (dynobj == NULL)
+ htab->etab.dynobj = dynobj = abfd;
+
+ /* When creating a shared object, we must copy these
+ relocs into the output file. We create a reloc
+ section in dynobj and make room for the reloc. */
+ if (sreloc == NULL)
+ {
+ sreloc = _bfd_elf_make_dynamic_reloc_section
+ (sec, htab->etab.dynobj, 2, abfd, /*rela?*/ TRUE);
+
+ if (sreloc == NULL)
+ {
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ elf_section_data (sec)->sreloc = sreloc;
+ }
+
+ /* If this is a global symbol, we count the number of
+ relocations we need for this symbol. */
+ if (hh != NULL)
+ hdh_head = &((struct elf_metag_link_hash_entry *) hh)->dyn_relocs;
+ else
+ {
+ /* Track dynamic relocs needed for local syms too. */
+ asection *sr;
+ void *vpp;
+ Elf_Internal_Sym *isym;
+
+ isym = bfd_sym_from_r_symndx (&htab->sym_cache,
+ abfd, r_symndx);
+ if (isym == NULL)
+ return FALSE;
+
+ sr = bfd_section_from_elf_index (abfd, isym->st_shndx);
+ if (sr == NULL)
+ sr = sec;
+
+ vpp = &elf_section_data (sr)->local_dynrel;
+ hdh_head = (struct elf_metag_dyn_reloc_entry **) vpp;
+ }
+
+ hdh_p = *hdh_head;
+ if (hdh_p == NULL || hdh_p->sec != sec)
+ {
+ hdh_p = ((struct elf_metag_dyn_reloc_entry *)
+ bfd_alloc (dynobj, sizeof *hdh_p));
+ if (hdh_p == NULL)
+ return FALSE;
+ hdh_p->hdh_next = *hdh_head;
+ *hdh_head = hdh_p;
+ hdh_p->sec = sec;
+ hdh_p->count = 0;
+ hdh_p->relative_count = 0;
+ }
+
+ hdh_p->count += 1;
+ if (ELF32_R_TYPE (rel->r_info) == R_METAG_RELBRANCH)
+ hdh_p->relative_count += 1;
+ }
+ break;
+
+ /* This relocation describes the C++ object vtable hierarchy.
+ Reconstruct it for later use during GC. */
+ case R_METAG_GNU_VTINHERIT:
+ if (!bfd_elf_gc_record_vtinherit (abfd, sec, &hh->eh,
+ rel->r_offset))
+ return FALSE;
+ break;
+
+ /* This relocation describes which C++ vtable entries are actually
+ used. Record for later use during GC. */
+ case R_METAG_GNU_VTENTRY:
+ BFD_ASSERT (hh != NULL);
+ if (hh != NULL
+ && !bfd_elf_gc_record_vtentry (abfd, sec, &hh->eh, rel->r_addend))
+ return FALSE;
+ break;
+ }
+ }
+
+ return TRUE;
+}
+
+/* Copy the extra info we tack onto an elf_link_hash_entry. */
+
+static void
+elf_metag_copy_indirect_symbol (struct bfd_link_info *info,
+ struct elf_link_hash_entry *eh_dir,
+ struct elf_link_hash_entry *eh_ind)
+{
+ struct elf_metag_link_hash_entry *hh_dir, *hh_ind;
+
+ hh_dir = metag_elf_hash_entry (eh_dir);
+ hh_ind = metag_elf_hash_entry (eh_ind);
+
+ if (hh_ind->dyn_relocs != NULL)
+ {
+ if (hh_dir->dyn_relocs != NULL)
+ {
+ struct elf_metag_dyn_reloc_entry **hdh_pp;
+ struct elf_metag_dyn_reloc_entry *hdh_p;
+
+ if (eh_ind->root.type == bfd_link_hash_indirect)
+ abort ();
+
+ /* Add reloc counts against the weak sym to the strong sym
+ list. Merge any entries against the same section. */
+ for (hdh_pp = &hh_ind->dyn_relocs; (hdh_p = *hdh_pp) != NULL; )
+ {
+ struct elf_metag_dyn_reloc_entry *hdh_q;
+
+ for (hdh_q = hh_dir->dyn_relocs; hdh_q != NULL;
+ hdh_q = hdh_q->hdh_next)
+ if (hdh_q->sec == hdh_p->sec)
+ {
+ hdh_q->relative_count += hdh_p->relative_count;
+ hdh_q->count += hdh_p->count;
+ *hdh_pp = hdh_p->hdh_next;
+ break;
+ }
+ if (hdh_q == NULL)
+ hdh_pp = &hdh_p->hdh_next;
+ }
+ *hdh_pp = hh_dir->dyn_relocs;
+ }
+
+ hh_dir->dyn_relocs = hh_ind->dyn_relocs;
+ hh_ind->dyn_relocs = NULL;
+ }
+
+ if (eh_ind->root.type == bfd_link_hash_indirect
+ && eh_dir->got.refcount <= 0)
+ {
+ hh_dir->tls_type = hh_ind->tls_type;
+ hh_ind->tls_type = GOT_UNKNOWN;
+ }
+
+ _bfd_elf_link_hash_copy_indirect (info, eh_dir, eh_ind);
+}
+
+/* Adjust a symbol defined by a dynamic object and referenced by a
+ regular object. The current definition is in some section of the
+ dynamic object, but we're not including those sections. We have to
+ change the definition to something the rest of the link can
+ understand. */
+
+static bfd_boolean
+elf_metag_adjust_dynamic_symbol (struct bfd_link_info *info,
+ struct elf_link_hash_entry *eh)
+{
+ struct elf_metag_link_hash_table *htab;
+ struct elf_metag_link_hash_entry *hh;
+ struct elf_metag_dyn_reloc_entry *hdh_p;
+ asection *s;
+
+ /* If this is a function, put it in the procedure linkage table. We
+ will fill in the contents of the procedure linkage table later,
+ when we know the address of the .got section. */
+ if (eh->type == STT_FUNC
+ || eh->needs_plt)
+ {
+ if (eh->plt.refcount <= 0
+ || SYMBOL_CALLS_LOCAL (info, eh)
+ || (ELF_ST_VISIBILITY (eh->other) != STV_DEFAULT
+ && eh->root.type == bfd_link_hash_undefweak))
+ {
+ /* This case can occur if we saw a PLT reloc in an input
+ file, but the symbol was never referred to by a dynamic
+ object. In such a case, we don't actually need to build
+ a procedure linkage table, and we can just do a PCREL
+ reloc instead. */
+ eh->plt.offset = (bfd_vma) -1;
+ eh->needs_plt = 0;
+ }
+
+ return TRUE;
+ }
+ else
+ eh->plt.offset = (bfd_vma) -1;
+
+ /* If this is a weak symbol, and there is a real definition, the
+ processor independent code will have arranged for us to see the
+ real definition first, and we can just use the same value. */
+ if (eh->u.weakdef != NULL)
+ {
+ if (eh->u.weakdef->root.type != bfd_link_hash_defined
+ && eh->u.weakdef->root.type != bfd_link_hash_defweak)
+ abort ();
+ eh->root.u.def.section = eh->u.weakdef->root.u.def.section;
+ eh->root.u.def.value = eh->u.weakdef->root.u.def.value;
+ eh->non_got_ref = eh->u.weakdef->non_got_ref;
+ return TRUE;
+ }
+
+ /* This is a reference to a symbol defined by a dynamic object which
+ is not a function. */
+
+ /* If we are creating a shared library, we must presume that the
+ only references to the symbol are via the global offset table.
+ For such cases we need not do anything here; the relocations will
+ be handled correctly by relocate_section. */
+ if (info->shared)
+ return TRUE;
+
+ /* If there are no references to this symbol that do not use the
+ GOT, we don't need to generate a copy reloc. */
+ if (!eh->non_got_ref)
+ return TRUE;
+
+ /* If -z nocopyreloc was given, we won't generate them either. */
+ if (info->nocopyreloc)
+ {
+ eh->non_got_ref = 0;
+ return TRUE;
+ }
+
+ hh = (struct elf_metag_link_hash_entry *) eh;
+ for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->hdh_next)
+ {
+ s = hdh_p->sec->output_section;
+ if (s != NULL && (s->flags & SEC_READONLY) != 0)
+ break;
+ }
+
+ /* If we didn't find any dynamic relocs in read-only sections, then
+ we'll be keeping the dynamic relocs and avoiding the copy reloc. */
+ if (hdh_p == NULL)
+ {
+ eh->non_got_ref = 0;
+ return TRUE;
+ }
+
+ if (eh->size == 0)
+ {
+ (*_bfd_error_handler) (_("dynamic variable `%s' is zero size"),
+ hh->eh.root.root.string);
+ return TRUE;
+ }
+
+ /* We must allocate the symbol in our .dynbss section, which will
+ become part of the .bss section of the executable. There will be
+ an entry for this symbol in the .dynsym section. The dynamic
+ object will contain position independent code, so all references
+ from the dynamic object to this symbol will go through the global
+ offset table. The dynamic linker will use the .dynsym entry to
+ determine the address it must put in the global offset table, so
+ both the dynamic object and the regular object will refer to the
+ same memory location for the variable. */
+
+ htab = metag_link_hash_table (info);
+
+ /* We must generate a COPY reloc to tell the dynamic linker to
+ copy the initial value out of the dynamic object and into the
+ runtime process image. */
+ if ((eh->root.u.def.section->flags & SEC_ALLOC) != 0)
+ {
+ htab->srelbss->size += sizeof (Elf32_External_Rela);
+ eh->needs_copy = 1;
+ }
+
+ s = htab->sdynbss;
+
+ return _bfd_elf_adjust_dynamic_copy (eh, s);
+}
+
+/* Allocate space in .plt, .got and associated reloc sections for
+ global syms. */
+
+static bfd_boolean
+allocate_dynrelocs (struct elf_link_hash_entry *eh, void *inf)
+{
+ struct bfd_link_info *info;
+ struct elf_metag_link_hash_table *htab;
+ struct elf_metag_link_hash_entry *hh;
+ struct elf_metag_dyn_reloc_entry *hdh_p;
+
+ if (eh->root.type == bfd_link_hash_indirect)
+ return TRUE;
+
+ if (eh->root.type == bfd_link_hash_warning)
+ eh = (struct elf_link_hash_entry *) eh->root.u.i.link;
+
+ info = inf;
+ htab = metag_link_hash_table (info);
+
+ if (htab->etab.dynamic_sections_created
+ && eh->plt.refcount > 0)
+ {
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (eh->dynindx == -1
+ && !eh->forced_local)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, eh))
+ return FALSE;
+ }
+
+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, info->shared, eh))
+ {
+ asection *s = htab->splt;
+
+ /* If this is the first .plt entry, make room for the special
+ first entry. */
+ if (s->size == 0)
+ s->size += PLT_ENTRY_SIZE;
+
+ eh->plt.offset = s->size;
+
+ /* If this symbol is not defined in a regular file, and we are
+ not generating a shared library, then set the symbol to this
+ location in the .plt. This is required to make function
+ pointers compare as equal between the normal executable and
+ the shared library. */
+ if (! info->shared
+ && !eh->def_regular)
+ {
+ eh->root.u.def.section = s;
+ eh->root.u.def.value = eh->plt.offset;
+ }
+
+ /* Make room for this entry. */
+ s->size += PLT_ENTRY_SIZE;
+
+ /* We also need to make an entry in the .got.plt section, which
+ will be placed in the .got section by the linker script. */
+ htab->sgotplt->size += 4;
+
+ /* We also need to make an entry in the .rel.plt section. */
+ htab->srelplt->size += sizeof (Elf32_External_Rela);
+ }
+ else
+ {
+ eh->plt.offset = (bfd_vma) -1;
+ eh->needs_plt = 0;
+ }
+ }
+ else
+ {
+ eh->plt.offset = (bfd_vma) -1;
+ eh->needs_plt = 0;
+ }
+
+ if (eh->got.refcount > 0)
+ {
+ asection *s;
+ bfd_boolean dyn;
+ int tls_type = metag_elf_hash_entry (eh)->tls_type;
+
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (eh->dynindx == -1
+ && !eh->forced_local)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, eh))
+ return FALSE;
+ }
+
+ s = htab->sgot;
+
+ eh->got.offset = s->size;
+ s->size += 4;
+ /* R_METAG_TLS_GD needs 2 consecutive GOT slots. */
+ if (tls_type == GOT_TLS_GD)
+ s->size += 4;
+ dyn = htab->etab.dynamic_sections_created;
+ /* R_METAG_TLS_IE needs one dynamic relocation if dynamic,
+ R_METAG_TLS_GD needs one if local symbol and two if global. */
+ if ((tls_type == GOT_TLS_GD && eh->dynindx == -1)
+ || (tls_type == GOT_TLS_IE && dyn))
+ htab->srelgot->size += sizeof (Elf32_External_Rela);
+ else if (tls_type == GOT_TLS_GD)
+ htab->srelgot->size += 2 * sizeof (Elf32_External_Rela);
+ else if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, eh))
+ htab->srelgot->size += sizeof (Elf32_External_Rela);
+ }
+ else
+ eh->got.offset = (bfd_vma) -1;
+
+ hh = (struct elf_metag_link_hash_entry *) eh;
+ if (hh->dyn_relocs == NULL)
+ return TRUE;
+
+ /* If this is a -Bsymbolic shared link, then we need to discard all
+ space allocated for dynamic pc-relative relocs against symbols
+ defined in a regular object. For the normal shared case, discard
+ space for relocs that have become local due to symbol visibility
+ changes. */
+ if (info->shared)
+ {
+ if (SYMBOL_CALLS_LOCAL (info, eh))
+ {
+ struct elf_metag_dyn_reloc_entry **hdh_pp;
+
+ for (hdh_pp = &hh->dyn_relocs; (hdh_p = *hdh_pp) != NULL; )
+ {
+ hdh_p->count -= hdh_p->relative_count;
+ hdh_p->relative_count = 0;
+ if (hdh_p->count == 0)
+ *hdh_pp = hdh_p->hdh_next;
+ else
+ hdh_pp = &hdh_p->hdh_next;
+ }
+ }
+
+ /* Also discard relocs on undefined weak syms with non-default
+ visibility. */
+ if (hh->dyn_relocs != NULL
+ && eh->root.type == bfd_link_hash_undefweak)
+ {
+ if (ELF_ST_VISIBILITY (eh->other) != STV_DEFAULT)
+ hh->dyn_relocs = NULL;
+
+ /* Make sure undefined weak symbols are output as a dynamic
+ symbol in PIEs. */
+ else if (eh->dynindx == -1
+ && !eh->forced_local)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, eh))
+ return FALSE;
+ }
+ }
+ }
+ else
+ {
+ /* For the non-shared case, discard space for relocs against
+ symbols which turn out to need copy relocs or are not
+ dynamic. */
+ if (!eh->non_got_ref
+ && ((eh->def_dynamic
+ && !eh->def_regular)
+ || (htab->etab.dynamic_sections_created
+ && (eh->root.type == bfd_link_hash_undefweak
+ || eh->root.type == bfd_link_hash_undefined))))
+ {
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (eh->dynindx == -1
+ && !eh->forced_local)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, eh))
+ return FALSE;
+ }
+
+ /* If that succeeded, we know we'll be keeping all the
+ relocs. */
+ if (eh->dynindx != -1)
+ goto keep;
+ }
+
+ hh->dyn_relocs = NULL;
+ return TRUE;
+
+ keep: ;
+ }
+
+ /* Finally, allocate space. */
+ for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->hdh_next)
+ {
+ asection *sreloc = elf_section_data (hdh_p->sec)->sreloc;
+ sreloc->size += hdh_p->count * sizeof (Elf32_External_Rela);
+ }
+
+ return TRUE;
+}
+
+/* Find any dynamic relocs that apply to read-only sections. */
+
+static bfd_boolean
+readonly_dynrelocs (struct elf_link_hash_entry *eh, void *inf)
+{
+ struct elf_metag_link_hash_entry *hh;
+ struct elf_metag_dyn_reloc_entry *hdh_p;
+
+ if (eh->root.type == bfd_link_hash_warning)
+ eh = (struct elf_link_hash_entry *) eh->root.u.i.link;
+
+ hh = (struct elf_metag_link_hash_entry *) eh;
+ for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->hdh_next)
+ {
+ asection *s = hdh_p->sec->output_section;
+
+ if (s != NULL && (s->flags & SEC_READONLY) != 0)
+ {
+ struct bfd_link_info *info = inf;
+
+ info->flags |= DF_TEXTREL;
+
+ /* Not an error, just cut short the traversal. */
+ return FALSE;
+ }
+ }
+ return TRUE;
+}
+
+/* Set the sizes of the dynamic sections. */
+
+static bfd_boolean
+elf_metag_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ struct bfd_link_info *info)
+{
+ struct elf_metag_link_hash_table *htab;
+ bfd *dynobj;
+ bfd *ibfd;
+ asection *s;
+ bfd_boolean relocs;
+
+ htab = metag_link_hash_table (info);
+ dynobj = htab->etab.dynobj;
+ if (dynobj == NULL)
+ abort ();
+
+ if (htab->etab.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+ if (info->executable)
+ {
+ s = bfd_get_section_by_name (dynobj, ".interp");
+ if (s == NULL)
+ abort ();
+ s->size = sizeof ELF_DYNAMIC_INTERPRETER;
+ s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
+ }
+ }
+
+ /* Set up .got offsets for local syms, and space for local dynamic
+ relocs. */
+ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
+ {
+ bfd_signed_vma *local_got;
+ bfd_signed_vma *end_local_got;
+ bfd_size_type locsymcount;
+ Elf_Internal_Shdr *symtab_hdr;
+ asection *srel;
+ char *local_tls_type;
+
+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour)
+ continue;
+
+ for (s = ibfd->sections; s != NULL; s = s->next)
+ {
+ struct elf_metag_dyn_reloc_entry *hdh_p;
+
+ for (hdh_p = ((struct elf_metag_dyn_reloc_entry *)
+ elf_section_data (s)->local_dynrel);
+ hdh_p != NULL;
+ hdh_p = hdh_p->hdh_next)
+ {
+ if (!bfd_is_abs_section (hdh_p->sec)
+ && bfd_is_abs_section (hdh_p->sec->output_section))
+ {
+ /* Input section has been discarded, either because
+ it is a copy of a linkonce section or due to
+ linker script /DISCARD/, so we'll be discarding
+ the relocs too. */
+ }
+ else if (hdh_p->count != 0)
+ {
+ srel = elf_section_data (hdh_p->sec)->sreloc;
+ srel->size += hdh_p->count * sizeof (Elf32_External_Rela);
+ if ((hdh_p->sec->output_section->flags & SEC_READONLY) != 0)
+ info->flags |= DF_TEXTREL;
+ }
+ }
+ }
+
+ local_got = elf_local_got_refcounts (ibfd);
+ if (!local_got)
+ continue;
+
+ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
+ locsymcount = symtab_hdr->sh_info;
+ end_local_got = local_got + locsymcount;
+ local_tls_type = metag_elf_local_got_tls_type (ibfd);
+ s = htab->sgot;
+ srel = htab->srelgot;
+ for (; local_got < end_local_got; ++local_got)
+ {
+ if (*local_got > 0)
+ {
+ *local_got = s->size;
+ s->size += GOT_ENTRY_SIZE;
+ /* R_METAG_TLS_GD relocs need 2 consecutive GOT entries. */
+ if (*local_tls_type == GOT_TLS_GD)
+ s->size += 4;
+ if (info->shared)
+ srel->size += sizeof (Elf32_External_Rela);
+ }
+ else
+ *local_got = (bfd_vma) -1;
+ ++local_tls_type;
+ }
+ }
+
+ if (htab->tls_ldm_got.refcount > 0)
+ {
+ /* Allocate 2 got entries and 1 dynamic reloc for R_METAG_TLS_LDM
+ reloc. */
+ htab->tls_ldm_got.offset = htab->sgot->size;
+ htab->sgot->size += 8;
+ htab->srelgot->size += sizeof (Elf32_External_Rela);
+ }
+ else
+ htab->tls_ldm_got.offset = -1;
+
+ /* Allocate global sym .plt and .got entries, and space for global
+ sym dynamic relocs. */
+ elf_link_hash_traverse (&htab->etab, allocate_dynrelocs, info);
+
+ /* We now have determined the sizes of the various dynamic sections.
+ Allocate memory for them. */
+ relocs = FALSE;
+ for (s = dynobj->sections; s != NULL; s = s->next)
+ {
+ bfd_boolean reloc_section = FALSE;
+
+ if ((s->flags & SEC_LINKER_CREATED) == 0)
+ continue;
+
+ if (s == htab->splt
+ || s == htab->sgot
+ || s == htab->sgotplt
+ || s == htab->sdynbss)
+ {
+ /* Strip this section if we don't need it; see the
+ comment below. */
+ }
+ else if (CONST_STRNEQ (bfd_get_section_name (dynobj, s), ".rela"))
+ {
+ if (s->size != 0 && s != htab->srelplt)
+ relocs = TRUE;
+
+ /* We use the reloc_count field as a counter if we need
+ to copy relocs into the output file. */
+ s->reloc_count = 0;
+ reloc_section = TRUE;
+ }
+ else
+ {
+ /* It's not one of our sections, so don't allocate space. */
+ continue;
+ }
+
+ if (s->size == 0)
+ {
+ /* If we don't need this section, strip it from the
+ output file. This is mostly to handle .rela.bss and
+ .rela.plt. We must create both sections in
+ create_dynamic_sections, because they must be created
+ before the linker maps input sections to output
+ sections. The linker does that before
+ adjust_dynamic_symbol is called, and it is that
+ function which decides whether anything needs to go
+ into these sections. */
+ s->flags |= SEC_EXCLUDE;
+ continue;
+ }
+
+ if ((s->flags & SEC_HAS_CONTENTS) == 0)
+ continue;
+
+ /* Allocate memory for the section contents. */
+ s->contents = bfd_zalloc (dynobj, s->size);
+ if (s->contents == NULL)
+ return FALSE;
+ else if (reloc_section)
+ {
+ unsigned char *contents = s->contents;
+ Elf32_External_Rela reloc;
+
+ /* Fill the reloc section with a R_METAG_NONE type reloc. */
+ memset(&reloc, 0, sizeof(Elf32_External_Rela));
+ reloc.r_info[0] = R_METAG_NONE;
+ for (; contents < (s->contents + s->size);
+ contents += sizeof(Elf32_External_Rela))
+ {
+ memcpy(contents, &reloc, sizeof(Elf32_External_Rela));
+ }
+ }
+ }
+
+ if (htab->etab.dynamic_sections_created)
+ {
+ /* Add some entries to the .dynamic section. We fill in the
+ values later, in elf_metag_finish_dynamic_sections, but we
+ must add the entries now so that we get the correct size for
+ the .dynamic section. The DT_DEBUG entry is filled in by the
+ dynamic linker and used by the debugger. */
+#define add_dynamic_entry(TAG, VAL) \
+ _bfd_elf_add_dynamic_entry (info, TAG, VAL)
+
+ if (!add_dynamic_entry (DT_PLTGOT, 0))
+ return FALSE;
+
+ if (info->executable)
+ {
+ if (!add_dynamic_entry (DT_DEBUG, 0))
+ return FALSE;
+ }
+
+ if (htab->srelplt->size != 0)
+ {
+ if (!add_dynamic_entry (DT_PLTRELSZ, 0)
+ || !add_dynamic_entry (DT_PLTREL, DT_RELA)
+ || !add_dynamic_entry (DT_JMPREL, 0))
+ return FALSE;
+ }
+
+ if (relocs)
+ {
+ if (!add_dynamic_entry (DT_RELA, 0)
+ || !add_dynamic_entry (DT_RELASZ, 0)
+ || !add_dynamic_entry (DT_RELAENT, sizeof (Elf32_External_Rela)))
+ return FALSE;
+
+ /* If any dynamic relocs apply to a read-only section,
+ then we need a DT_TEXTREL entry. */
+ if ((info->flags & DF_TEXTREL) == 0)
+ elf_link_hash_traverse (&htab->etab, readonly_dynrelocs, info);
+
+ if ((info->flags & DF_TEXTREL) != 0)
+ {
+ if (!add_dynamic_entry (DT_TEXTREL, 0))
+ return FALSE;
+ }
+ }
+ }
+#undef add_dynamic_entry
+
+ return TRUE;
+}
+
+/* Finish up dynamic symbol handling. We set the contents of various
+ dynamic sections here. */
+
+static bfd_boolean
+elf_metag_finish_dynamic_symbol (bfd *output_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *eh,
+ Elf_Internal_Sym *sym)
+{
+ struct elf_metag_link_hash_table *htab;
+ Elf_Internal_Rela rel;
+ bfd_byte *loc;
+
+ htab = metag_link_hash_table (info);
+
+ if (eh->plt.offset != (bfd_vma) -1)
+ {
+ asection *splt;
+ asection *sgot;
+ asection *srela;
+
+ bfd_vma plt_index;
+ bfd_vma got_offset;
+ bfd_vma got_entry;
+
+ if (eh->plt.offset & 1)
+ abort ();
+
+ BFD_ASSERT (eh->dynindx != -1);
+
+ splt = htab->splt;
+ sgot = htab->sgotplt;
+ srela = htab->srelplt;
+ BFD_ASSERT (splt != NULL && sgot != NULL && srela != NULL);
+
+ /* Get the index in the procedure linkage table which
+ corresponds to this symbol. This is the index of this symbol
+ in all the symbols for which we are making plt entries. The
+ first entry in the procedure linkage table is reserved. */
+ plt_index = eh->plt.offset / PLT_ENTRY_SIZE - 1;
+
+ /* Get the offset into the .got.plt table of the entry that
+ corresponds to this function. */
+ got_offset = plt_index * GOT_ENTRY_SIZE;
+
+ BFD_ASSERT (got_offset < (1 << 16));
+
+ got_entry = sgot->output_section->vma
+ + sgot->output_offset
+ + got_offset;
+
+ BFD_ASSERT (plt_index < (1 << 16));
+
+ /* Fill in the entry in the procedure linkage table. */
+ if (! info->shared)
+ {
+ bfd_put_32 (output_bfd,
+ (plt_entry[0]
+ | (((got_entry >> 16) & 0xffff) << 3)),
+ splt->contents + eh->plt.offset);
+ bfd_put_32 (output_bfd,
+ (plt_entry[1]
+ | ((got_entry & 0xffff) << 3)),
+ splt->contents + eh->plt.offset + 4);
+ bfd_put_32 (output_bfd, plt_entry[2],
+ splt->contents + eh->plt.offset + 8);
+ bfd_put_32 (output_bfd,
+ (plt_entry[3] | (plt_index << 3)),
+ splt->contents + eh->plt.offset + 12);
+ bfd_put_32 (output_bfd,
+ (plt_entry[4]
+ | ((((unsigned int) ((- (eh->plt.offset + 16)) >> 2)) & 0x7ffff) << 5)),
+ splt->contents + eh->plt.offset + 16);
+ }
+ else
+ {
+ bfd_vma addr = got_entry - (splt->output_section->vma +
+ splt->output_offset + eh->plt.offset);
+
+ bfd_put_32 (output_bfd,
+ plt_pic_entry[0] | (((addr >> 16) & 0xffff) << 3),
+ splt->contents + eh->plt.offset);
+ bfd_put_32 (output_bfd,
+ plt_pic_entry[1] | ((addr & 0xffff) << 3),
+ splt->contents + eh->plt.offset + 4);
+ bfd_put_32 (output_bfd, plt_pic_entry[2],
+ splt->contents + eh->plt.offset + 8);
+ bfd_put_32 (output_bfd,
+ (plt_pic_entry[3] | (plt_index << 3)),
+ splt->contents + eh->plt.offset + 12);
+ bfd_put_32 (output_bfd,
+ (plt_pic_entry[4]
+ + ((((unsigned int) ((- (eh->plt.offset + 16)) >> 2)) & 0x7ffff) << 5)),
+ splt->contents + eh->plt.offset + 16);
+ }
+
+ /* Fill in the entry in the global offset table. */
+ bfd_put_32 (output_bfd,
+ (splt->output_section->vma
+ + splt->output_offset
+ + eh->plt.offset
+ + 12), /* offset within PLT entry */
+ sgot->contents + got_offset);
+
+ /* Fill in the entry in the .rela.plt section. */
+ rel.r_offset = (sgot->output_section->vma
+ + sgot->output_offset
+ + got_offset);
+ rel.r_info = ELF32_R_INFO (eh->dynindx, R_METAG_JMP_SLOT);
+ rel.r_addend = 0;
+ loc = htab->srelplt->contents;
+ loc += plt_index * sizeof(Elf32_External_Rela);
+ bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+
+ if (!eh->def_regular)
+ {
+ /* Mark the symbol as undefined, rather than as defined in
+ the .plt section. Leave the value alone. */
+ sym->st_shndx = SHN_UNDEF;
+ }
+ }
+
+ if (eh->got.offset != (bfd_vma) -1
+ && (metag_elf_hash_entry (eh)->tls_type & GOT_TLS_GD) == 0
+ && (metag_elf_hash_entry (eh)->tls_type & GOT_TLS_IE) == 0)
+ {
+ /* This symbol has an entry in the global offset table. Set it
+ up. */
+
+ rel.r_offset = ((eh->got.offset &~ (bfd_vma) 1)
+ + htab->sgot->output_offset
+ + htab->sgot->output_section->vma);
+
+ /* If this is a -Bsymbolic link and the symbol is defined
+ locally or was forced to be local because of a version file,
+ we just want to emit a RELATIVE reloc. The entry in the
+ global offset table will already have been initialized in the
+ relocate_section function. */
+ if (info->shared
+ && (info->symbolic || eh->dynindx == -1)
+ && eh->def_regular)
+ {
+ rel.r_info = ELF32_R_INFO (0, R_METAG_RELATIVE);
+ rel.r_addend = (eh->root.u.def.value
+ + eh->root.u.def.section->output_offset
+ + eh->root.u.def.section->output_section->vma);
+ }
+ else
+ {
+ if ((eh->got.offset & 1) != 0)
+ abort ();
+ bfd_put_32 (output_bfd, 0, htab->sgot->contents + eh->got.offset);
+ rel.r_info = ELF32_R_INFO (eh->dynindx, R_METAG_GLOB_DAT);
+ rel.r_addend = 0;
+ }
+
+ loc = htab->srelgot->contents;
+ loc += htab->srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
+ bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+ }
+
+ if (eh->needs_copy)
+ {
+ asection *s;
+
+ /* This symbol needs a copy reloc. Set it up. */
+
+ if (! (eh->dynindx != -1
+ && (eh->root.type == bfd_link_hash_defined
+ || eh->root.type == bfd_link_hash_defweak)))
+ abort ();
+
+ s = htab->srelbss;
+
+ rel.r_offset = (eh->root.u.def.value
+ + eh->root.u.def.section->output_offset
+ + eh->root.u.def.section->output_section->vma);
+ rel.r_addend = 0;
+ rel.r_info = ELF32_R_INFO (eh->dynindx, R_METAG_COPY);
+ loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
+ bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+ }
+
+ /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */
+ if (eh->root.root.string[0] == '_'
+ && (strcmp (eh->root.root.string, "_DYNAMIC") == 0
+ || eh == htab->etab.hgot))
+ {
+ sym->st_shndx = SHN_ABS;
+ }
+
+ return TRUE;
+}
+
+/* Set the Meta ELF ABI version. */
+
+static void
+elf_metag_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
+{
+ Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
+
+ i_ehdrp = elf_elfheader (abfd);
+ i_ehdrp->e_ident[EI_ABIVERSION] = METAG_ELF_ABI_VERSION;
+}
+
+/* Used to decide how to sort relocs in an optimal manner for the
+ dynamic linker, before writing them out. */
+
+static enum elf_reloc_type_class
+elf_metag_reloc_type_class (const Elf_Internal_Rela *rela)
+{
+ switch ((int) ELF32_R_TYPE (rela->r_info))
+ {
+ case R_METAG_RELATIVE:
+ return reloc_class_relative;
+ case R_METAG_JMP_SLOT:
+ return reloc_class_plt;
+ case R_METAG_COPY:
+ return reloc_class_copy;
+ default:
+ return reloc_class_normal;
+ }
+}
+
+/* Finish up the dynamic sections. */
+
+static bfd_boolean
+elf_metag_finish_dynamic_sections (bfd *output_bfd,
+ struct bfd_link_info *info)
+{
+ bfd *dynobj;
+ struct elf_metag_link_hash_table *htab;
+ asection *sdyn;
+
+ htab = metag_link_hash_table (info);
+ dynobj = htab->etab.dynobj;
+
+ sdyn = bfd_get_section_by_name (dynobj, ".dynamic");
+
+ if (htab->etab.dynamic_sections_created)
+ {
+ asection *splt;
+ Elf32_External_Dyn *dyncon, *dynconend;
+
+ if (sdyn == NULL)
+ abort ();
+
+ dyncon = (Elf32_External_Dyn *) sdyn->contents;
+ dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
+ for (; dyncon < dynconend; dyncon++)
+ {
+ Elf_Internal_Dyn dyn;
+ asection *s;
+
+ bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
+
+ switch (dyn.d_tag)
+ {
+ default:
+ continue;
+
+ case DT_PLTGOT:
+ s = htab->sgot->output_section;
+ BFD_ASSERT (s != NULL);
+ dyn.d_un.d_ptr = s->vma + htab->sgot->output_offset;
+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+ break;
+
+ case DT_JMPREL:
+ s = htab->srelplt->output_section;
+ BFD_ASSERT (s != NULL);
+ dyn.d_un.d_ptr = s->vma;
+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+ break;
+
+ case DT_PLTRELSZ:
+ s = htab->srelplt;
+ dyn.d_un.d_val = s->size;
+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+ break;
+
+ case DT_RELASZ:
+ /* Don't count procedure linkage table relocs in the
+ overall reloc count. */
+ if (htab->srelplt) {
+ s = htab->srelplt;
+ dyn.d_un.d_val -= s->size;
+ }
+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+ break;
+
+ case DT_RELA:
+ /* We may not be using the standard ELF linker script.
+ If .rela.plt is the first .rela section, we adjust
+ DT_RELA to not include it. */
+ if (htab->srelplt) {
+ s = htab->srelplt;
+ if (dyn.d_un.d_ptr == s->output_section->vma + s->output_offset)
+ dyn.d_un.d_ptr += s->size;
+ }
+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+ break;
+ }
+
+ }
+
+ /* Fill in the first entry in the procedure linkage table. */
+ splt = htab->splt;
+ if (splt && splt->size > 0)
+ {
+ unsigned long addr;
+ /* addr = .got + 4 */
+ addr = htab->sgot->output_section->vma +
+ htab->sgot->output_offset + 4;
+ if (info->shared)
+ {
+ addr -= splt->output_section->vma + splt->output_offset;
+ bfd_put_32 (output_bfd,
+ plt0_pic_entry[0] | (((addr >> 16) & 0xffff) << 3),
+ splt->contents);
+ bfd_put_32 (output_bfd,
+ plt0_pic_entry[1] | ((addr & 0xffff) << 3),
+ splt->contents + 4);
+ bfd_put_32 (output_bfd, plt0_pic_entry[2], splt->contents + 8);
+ bfd_put_32 (output_bfd, plt0_pic_entry[3], splt->contents + 12);
+ bfd_put_32 (output_bfd, plt0_pic_entry[4], splt->contents + 16);
+ }
+ else
+ {
+ bfd_put_32 (output_bfd,
+ plt0_entry[0] | (((addr >> 16) & 0xffff) << 3),
+ splt->contents);
+ bfd_put_32 (output_bfd,
+ plt0_entry[1] | ((addr & 0xffff) << 3),
+ splt->contents + 4);
+ bfd_put_32 (output_bfd, plt0_entry[2], splt->contents + 8);
+ bfd_put_32 (output_bfd, plt0_entry[3], splt->contents + 12);
+ bfd_put_32 (output_bfd, plt0_entry[4], splt->contents + 16);
+ }
+
+ elf_section_data (splt->output_section)->this_hdr.sh_entsize =
+ PLT_ENTRY_SIZE;
+ }
+ }
+
+ if (htab->sgot != NULL && htab->sgot->size != 0)
+ {
+ /* Fill in the first entry in the global offset table.
+ We use it to point to our dynamic section, if we have one. */
+ bfd_put_32 (output_bfd,
+ sdyn ? sdyn->output_section->vma + sdyn->output_offset : 0,
+ htab->sgot->contents);
+
+ /* The second entry is reserved for use by the dynamic linker. */
+ memset (htab->sgot->contents + GOT_ENTRY_SIZE, 0, GOT_ENTRY_SIZE);
+
+ /* Set .got entry size. */
+ elf_section_data (htab->sgot->output_section)
+ ->this_hdr.sh_entsize = GOT_ENTRY_SIZE;
+ }
+
+ return TRUE;
+}
+
+/* Return the section that should be marked against GC for a given
+ relocation. */
+
+static asection *
+elf_metag_gc_mark_hook (asection *sec,
+ struct bfd_link_info *info,
+ Elf_Internal_Rela *rela,
+ struct elf_link_hash_entry *hh,
+ Elf_Internal_Sym *sym)
+{
+ if (hh != NULL)
+ switch ((unsigned int) ELF32_R_TYPE (rela->r_info))
+ {
+ case R_METAG_GNU_VTINHERIT:
+ case R_METAG_GNU_VTENTRY:
+ return NULL;
+ }
+
+ return _bfd_elf_gc_mark_hook (sec, info, rela, hh, sym);
+}
+
+/* Update the got and plt entry reference counts for the section being
+ removed. */
+
+static bfd_boolean
+elf_metag_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED,
+ struct bfd_link_info *info ATTRIBUTE_UNUSED,
+ asection *sec ATTRIBUTE_UNUSED,
+ const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **eh_syms;
+ bfd_signed_vma *local_got_refcounts;
+ bfd_signed_vma *local_plt_refcounts;
+ const Elf_Internal_Rela *rel, *relend;
+
+ if (info->relocatable)
+ return TRUE;
+
+ elf_section_data (sec)->local_dynrel = NULL;
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ eh_syms = elf_sym_hashes (abfd);
+ local_got_refcounts = elf_local_got_refcounts (abfd);
+ local_plt_refcounts = local_got_refcounts;
+ if (local_plt_refcounts != NULL)
+ local_plt_refcounts += symtab_hdr->sh_info;
+
+ relend = relocs + sec->reloc_count;
+ for (rel = relocs; rel < relend; rel++)
+ {
+ unsigned long r_symndx;
+ unsigned int r_type;
+ struct elf_link_hash_entry *eh = NULL;
+
+ r_symndx = ELF32_R_SYM (rel->r_info);
+ if (r_symndx >= symtab_hdr->sh_info)
+ {
+ struct elf_metag_link_hash_entry *hh;
+ struct elf_metag_dyn_reloc_entry **hdh_pp;
+ struct elf_metag_dyn_reloc_entry *hdh_p;
+
+ eh = eh_syms[r_symndx - symtab_hdr->sh_info];
+ while (eh->root.type == bfd_link_hash_indirect
+ || eh->root.type == bfd_link_hash_warning)
+ eh = (struct elf_link_hash_entry *) eh->root.u.i.link;
+ hh = (struct elf_metag_link_hash_entry *) eh;
+
+ for (hdh_pp = &hh->dyn_relocs; (hdh_p = *hdh_pp) != NULL;
+ hdh_pp = &hdh_p->hdh_next)
+ if (hdh_p->sec == sec)
+ {
+ /* Everything must go for SEC. */
+ *hdh_pp = hdh_p->hdh_next;
+ break;
+ }
+ }
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+ switch (r_type)
+ {
+ case R_METAG_TLS_LDM:
+ if (metag_link_hash_table (info)->tls_ldm_got.refcount > 0)
+ metag_link_hash_table (info)->tls_ldm_got.refcount -= 1;
+ break;
+ case R_METAG_TLS_IE:
+ case R_METAG_TLS_GD:
+ case R_METAG_GETSET_GOT:
+ if (eh != NULL)
+ {
+ if (eh->got.refcount > 0)
+ eh->got.refcount -= 1;
+ }
+ else if (local_got_refcounts != NULL)
+ {
+ if (local_got_refcounts[r_symndx] > 0)
+ local_got_refcounts[r_symndx] -= 1;
+ }
+ break;
+
+ case R_METAG_RELBRANCH_PLT:
+ if (eh != NULL)
+ {
+ if (eh->plt.refcount > 0)
+ eh->plt.refcount -= 1;
+ }
+ break;
+
+ case R_METAG_ADDR32:
+ case R_METAG_HIADDR16:
+ case R_METAG_LOADDR16:
+ case R_METAG_GETSETOFF:
+ case R_METAG_RELBRANCH:
+ if (eh != NULL)
+ {
+ struct elf_metag_link_hash_entry *hh;
+ struct elf_metag_dyn_reloc_entry **hdh_pp;
+ struct elf_metag_dyn_reloc_entry *hdh_p;
+
+ if (!info->shared && eh->plt.refcount > 0)
+ eh->plt.refcount -= 1;
+
+ hh = (struct elf_metag_link_hash_entry *) eh;
+
+ for (hdh_pp = &hh->dyn_relocs; (hdh_p = *hdh_pp) != NULL;
+ hdh_pp = &hdh_p->hdh_next)
+ if (hdh_p->sec == sec)
+ {
+ if (ELF32_R_TYPE (rel->r_info) == R_METAG_RELBRANCH)
+ hdh_p->relative_count -= 1;
+ hdh_p->count -= 1;
+ if (hdh_p->count == 0)
+ *hdh_pp = hdh_p->hdh_next;
+ break;
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ return TRUE;
+}
+
+/* Determine the type of stub needed, if any, for a call. */
+
+static enum elf_metag_stub_type
+metag_type_of_stub (asection *input_sec,
+ const Elf_Internal_Rela *rel,
+ struct elf_metag_link_hash_entry *hh,
+ bfd_vma destination,
+ struct bfd_link_info *info ATTRIBUTE_UNUSED)
+{
+ bfd_vma location;
+ bfd_vma branch_offset;
+ bfd_vma max_branch_offset;
+
+ if (hh != NULL &&
+ !(hh->eh.root.type == bfd_link_hash_defined
+ || hh->eh.root.type == bfd_link_hash_defweak))
+ return metag_stub_none;
+
+ /* Determine where the call point is. */
+ location = (input_sec->output_offset
+ + input_sec->output_section->vma
+ + rel->r_offset);
+
+ branch_offset = destination - location;
+
+ /* Determine if a long branch stub is needed. Meta branch offsets
+ are signed 19 bits 4 byte aligned. */
+ max_branch_offset = (1 << (BRANCH_BITS-1)) << 2;
+
+ if (branch_offset + max_branch_offset >= 2*max_branch_offset)
+ {
+ if (info->shared)
+ return metag_stub_long_branch_shared;
+ else
+ return metag_stub_long_branch;
+ }
+
+ return metag_stub_none;
+}
+
+#define MOVT_A0_3 0x82180005
+#define JUMP_A0_3 0xac180003
+
+#define MOVT_A1LBP 0x83080005
+#define ADD_A1LBP 0x83080000
+
+#define ADDT_A0_3_CPC 0x82980001
+#define ADD_A0_3_A0_3 0x82180000
+#define MOV_PC_A0_3 0xa3180ca0
+
+static bfd_boolean
+metag_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg ATTRIBUTE_UNUSED)
+{
+ struct elf_metag_stub_hash_entry *hsh;
+ asection *stub_sec;
+ bfd *stub_bfd;
+ bfd_byte *loc;
+ bfd_vma sym_value;
+ int size;
+
+ /* Massage our args to the form they really have. */
+ hsh = (struct elf_metag_stub_hash_entry *) gen_entry;
+
+ stub_sec = hsh->stub_sec;
+
+ /* Make a note of the offset within the stubs for this entry. */
+ hsh->stub_offset = stub_sec->size;
+ loc = stub_sec->contents + hsh->stub_offset;
+
+ stub_bfd = stub_sec->owner;
+
+ switch (hsh->stub_type)
+ {
+ case metag_stub_long_branch_shared:
+ /* A PIC long branch stub is an ADDT and an ADD instruction used to
+ calculate the jump target using A0.3 as a temporary. Then a MOV
+ to PC carries out the jump. */
+ sym_value = (hsh->target_value
+ + hsh->target_section->output_offset
+ + hsh->target_section->output_section->vma
+ + hsh->addend);
+
+ sym_value -= (hsh->stub_offset
+ + stub_sec->output_offset
+ + stub_sec->output_section->vma);
+
+ bfd_put_32 (stub_bfd, ADDT_A0_3_CPC | (((sym_value >> 16) & 0xffff) << 3),
+ loc);
+
+ bfd_put_32 (stub_bfd, ADD_A0_3_A0_3 | ((sym_value & 0xffff) << 3),
+ loc + 4);
+
+ bfd_put_32 (stub_bfd, MOV_PC_A0_3, loc + 8);
+
+ size = 12;
+ break;
+ case metag_stub_long_branch:
+ /* A standard long branch stub is a MOVT instruction followed by a
+ JUMP instruction using the A0.3 register as a temporary. This is
+ the same method used by the LDLK linker (patch.c). */
+ sym_value = (hsh->target_value
+ + hsh->target_section->output_offset
+ + hsh->target_section->output_section->vma
+ + hsh->addend);
+
+ bfd_put_32 (stub_bfd, MOVT_A0_3 | (((sym_value >> 16) & 0xffff) << 3),
+ loc);
+
+ bfd_put_32 (stub_bfd, JUMP_A0_3 | ((sym_value & 0xffff) << 3), loc + 4);
+
+ size = 8;
+ break;
+ default:
+ BFD_FAIL ();
+ return FALSE;
+ }
+
+ stub_sec->size += size;
+ return TRUE;
+}
+
+/* As above, but don't actually build the stub. Just bump offset so
+ we know stub section sizes. */
+
+static bfd_boolean
+metag_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg ATTRIBUTE_UNUSED)
+{
+ struct elf_metag_stub_hash_entry *hsh;
+ int size = 0;
+
+ /* Massage our args to the form they really have. */
+ hsh = (struct elf_metag_stub_hash_entry *) gen_entry;
+
+ if (hsh->stub_type == metag_stub_long_branch)
+ size = 8;
+ else if (hsh->stub_type == metag_stub_long_branch_shared)
+ size = 12;
+
+ hsh->stub_sec->size += size;
+ return TRUE;
+}
+
+/* Set up various things so that we can make a list of input sections
+ for each output section included in the link. Returns -1 on error,
+ 0 when no stubs will be needed, and 1 on success. */
+
+int
+elf_metag_setup_section_lists (bfd *output_bfd, struct bfd_link_info *info)
+{
+ bfd *input_bfd;
+ unsigned int bfd_count;
+ int top_id, top_index;
+ asection *section;
+ asection **input_list, **list;
+ bfd_size_type amt;
+ struct elf_metag_link_hash_table *htab = metag_link_hash_table (info);
+
+ /* Count the number of input BFDs and find the top input section id. */
+ for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
+ input_bfd != NULL;
+ input_bfd = input_bfd->link_next)
+ {
+ bfd_count += 1;
+ for (section = input_bfd->sections;
+ section != NULL;
+ section = section->next)
+ {
+ if (top_id < section->id)
+ top_id = section->id;
+ }
+ }
+
+ htab->bfd_count = bfd_count;
+
+ amt = sizeof (struct map_stub) * (top_id + 1);
+ htab->stub_group = bfd_zmalloc (amt);
+ if (htab->stub_group == NULL)
+ return -1;
+
+ /* We can't use output_bfd->section_count here to find the top output
+ section index as some sections may have been removed, and
+ strip_excluded_output_sections doesn't renumber the indices. */
+ for (section = output_bfd->sections, top_index = 0;
+ section != NULL;
+ section = section->next)
+ {
+ if (top_index < section->index)
+ top_index = section->index;
+ }
+
+ htab->top_index = top_index;
+ amt = sizeof (asection *) * (top_index + 1);
+ input_list = bfd_malloc (amt);
+ htab->input_list = input_list;
+ if (input_list == NULL)
+ return -1;
+
+ /* For sections we aren't interested in, mark their entries with a
+ value we can check later. */
+ list = input_list + top_index;
+ do
+ *list = bfd_abs_section_ptr;
+ while (list-- != input_list);
+
+ for (section = output_bfd->sections;
+ section != NULL;
+ section = section->next)
+ {
+ /* FIXME: This is a bit of hack. Currently our .ctors and .dtors
+ * have PC relative relocs in them but no code flag set. */
+ if (((section->flags & SEC_CODE) != 0) ||
+ strcmp(".ctors", section->name) ||
+ strcmp(".dtors", section->name))
+ input_list[section->index] = NULL;
+ }
+
+ return 1;
+}
+
+/* The linker repeatedly calls this function for each input section,
+ in the order that input sections are linked into output sections.
+ Build lists of input sections to determine groupings between which
+ we may insert linker stubs. */
+
+void
+elf_metag_next_input_section (struct bfd_link_info *info, asection *isec)
+{
+ struct elf_metag_link_hash_table *htab = metag_link_hash_table (info);
+
+ if (isec->output_section->index <= htab->top_index)
+ {
+ asection **list = htab->input_list + isec->output_section->index;
+ if (*list != bfd_abs_section_ptr)
+ {
+ /* Steal the link_sec pointer for our list. */
+#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
+ /* This happens to make the list in reverse order,
+ which is what we want. */
+ PREV_SEC (isec) = *list;
+ *list = isec;
+ }
+ }
+}
+
+/* See whether we can group stub sections together. Grouping stub
+ sections may result in fewer stubs. More importantly, we need to
+ put all .init* and .fini* stubs at the beginning of the .init or
+ .fini output sections respectively, because glibc splits the
+ _init and _fini functions into multiple parts. Putting a stub in
+ the middle of a function is not a good idea. */
+
+static void
+group_sections (struct elf_metag_link_hash_table *htab,
+ bfd_size_type stub_group_size,
+ bfd_boolean stubs_always_before_branch)
+{
+ asection **list = htab->input_list + htab->top_index;
+ do
+ {
+ asection *tail = *list;
+ if (tail == bfd_abs_section_ptr)
+ continue;
+ while (tail != NULL)
+ {
+ asection *curr;
+ asection *prev;
+ bfd_size_type total;
+ bfd_boolean big_sec;
+
+ curr = tail;
+ total = tail->size;
+ big_sec = total >= stub_group_size;
+
+ while ((prev = PREV_SEC (curr)) != NULL
+ && ((total += curr->output_offset - prev->output_offset)
+ < stub_group_size))
+ curr = prev;
+
+ /* OK, the size from the start of CURR to the end is less
+ than stub_group_size bytes and thus can be handled by one stub
+ section. (or the tail section is itself larger than
+ stub_group_size bytes, in which case we may be toast.)
+ We should really be keeping track of the total size of
+ stubs added here, as stubs contribute to the final output
+ section size. */
+ do
+ {
+ prev = PREV_SEC (tail);
+ /* Set up this stub group. */
+ htab->stub_group[tail->id].link_sec = curr;
+ }
+ while (tail != curr && (tail = prev) != NULL);
+
+ /* But wait, there's more! Input sections up to stub_group_size
+ bytes before the stub section can be handled by it too.
+ Don't do this if we have a really large section after the
+ stubs, as adding more stubs increases the chance that
+ branches may not reach into the stub section. */
+ if (!stubs_always_before_branch && !big_sec)
+ {
+ total = 0;
+ while (prev != NULL
+ && ((total += tail->output_offset - prev->output_offset)
+ < stub_group_size))
+ {
+ tail = prev;
+ prev = PREV_SEC (tail);
+ htab->stub_group[tail->id].link_sec = curr;
+ }
+ }
+ tail = prev;
+ }
+ }
+ while (list-- != htab->input_list);
+ free (htab->input_list);
+#undef PREV_SEC
+}
+
+/* Read in all local syms for all input bfds.
+ Returns -1 on error, 0 otherwise. */
+
+static int
+get_local_syms (bfd *output_bfd ATTRIBUTE_UNUSED, bfd *input_bfd,
+ struct bfd_link_info *info)
+{
+ unsigned int bfd_indx;
+ Elf_Internal_Sym *local_syms, **all_local_syms;
+ int stub_changed = 0;
+ struct elf_metag_link_hash_table *htab = metag_link_hash_table (info);
+
+ /* We want to read in symbol extension records only once. To do this
+ we need to read in the local symbols in parallel and save them for
+ later use; so hold pointers to the local symbols in an array. */
+ bfd_size_type amt = sizeof (Elf_Internal_Sym *) * htab->bfd_count;
+ all_local_syms = bfd_zmalloc (amt);
+ htab->all_local_syms = all_local_syms;
+ if (all_local_syms == NULL)
+ return -1;
+
+ /* Walk over all the input BFDs, swapping in local symbols. */
+ for (bfd_indx = 0;
+ input_bfd != NULL;
+ input_bfd = input_bfd->link_next, bfd_indx++)
+ {
+ Elf_Internal_Shdr *symtab_hdr;
+
+ /* We'll need the symbol table in a second. */
+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
+ if (symtab_hdr->sh_info == 0)
+ continue;
+
+ /* We need an array of the local symbols attached to the input bfd. */
+ local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
+ if (local_syms == NULL)
+ {
+ local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
+ symtab_hdr->sh_info, 0,
+ NULL, NULL, NULL);
+ /* Cache them for elf_link_input_bfd. */
+ symtab_hdr->contents = (unsigned char *) local_syms;
+ }
+ if (local_syms == NULL)
+ return -1;
+
+ all_local_syms[bfd_indx] = local_syms;
+ }
+
+ return stub_changed;
+}
+
+/* Determine and set the size of the stub section for a final link.
+
+The basic idea here is to examine all the relocations looking for
+PC-relative calls to a target that is unreachable with a "CALLR"
+instruction. */
+
+/* See elf32-hppa.c and elf64-ppc.c. */
+
+bfd_boolean
+elf_metag_size_stubs(bfd *output_bfd, bfd *stub_bfd,
+ struct bfd_link_info *info,
+ bfd_signed_vma group_size,
+ asection * (*add_stub_section) (const char *, asection *),
+ void (*layout_sections_again) (void))
+{
+ bfd_size_type stub_group_size;
+ bfd_boolean stubs_always_before_branch;
+ bfd_boolean stub_changed;
+ struct elf_metag_link_hash_table *htab = metag_link_hash_table (info);
+
+ /* Stash our params away. */
+ htab->stub_bfd = stub_bfd;
+ htab->add_stub_section = add_stub_section;
+ htab->layout_sections_again = layout_sections_again;
+ stubs_always_before_branch = group_size < 0;
+ if (group_size < 0)
+ stub_group_size = -group_size;
+ else
+ stub_group_size = group_size;
+ if (stub_group_size == 1)
+ {
+ /* Default values. */
+ /* FIXME: not sure what these values should be */
+ if (stubs_always_before_branch)
+ {
+ stub_group_size = (1 << BRANCH_BITS);
+ }
+ else
+ {
+ stub_group_size = (1 << BRANCH_BITS);
+ }
+ }
+
+ group_sections (htab, stub_group_size, stubs_always_before_branch);
+
+ switch (get_local_syms (output_bfd, info->input_bfds, info))
+ {
+ default:
+ if (htab->all_local_syms)
+ goto error_ret_free_local;
+ return FALSE;
+
+ case 0:
+ stub_changed = FALSE;
+ break;
+
+ case 1:
+ stub_changed = TRUE;
+ break;
+ }
+
+ while (1)
+ {
+ bfd *input_bfd;
+ unsigned int bfd_indx;
+ asection *stub_sec;
+
+ for (input_bfd = info->input_bfds, bfd_indx = 0;
+ input_bfd != NULL;
+ input_bfd = input_bfd->link_next, bfd_indx++)
+ {
+ Elf_Internal_Shdr *symtab_hdr;
+ asection *section;
+ Elf_Internal_Sym *local_syms;
+
+ /* We'll need the symbol table in a second. */
+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
+ if (symtab_hdr->sh_info == 0)
+ continue;
+
+ local_syms = htab->all_local_syms[bfd_indx];
+
+ /* Walk over each section attached to the input bfd. */
+ for (section = input_bfd->sections;
+ section != NULL;
+ section = section->next)
+ {
+ Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
+
+ /* If there aren't any relocs, then there's nothing more
+ to do. */
+ if ((section->flags & SEC_RELOC) == 0
+ || section->reloc_count == 0)
+ continue;
+
+ /* If this section is a link-once section that will be
+ discarded, then don't create any stubs. */
+ if (section->output_section == NULL
+ || section->output_section->owner != output_bfd)
+ continue;
+
+ /* Get the relocs. */
+ internal_relocs
+ = _bfd_elf_link_read_relocs (input_bfd, section, NULL, NULL,
+ info->keep_memory);
+ if (internal_relocs == NULL)
+ goto error_ret_free_local;
+
+ /* Now examine each relocation. */
+ irela = internal_relocs;
+ irelaend = irela + section->reloc_count;
+ for (; irela < irelaend; irela++)
+ {
+ unsigned int r_type, r_indx;
+ enum elf_metag_stub_type stub_type;
+ struct elf_metag_stub_hash_entry *hsh;
+ asection *sym_sec;
+ bfd_vma sym_value;
+ bfd_vma destination;
+ struct elf_metag_link_hash_entry *hh;
+ char *stub_name;
+ const asection *id_sec;
+
+ r_type = ELF32_R_TYPE (irela->r_info);
+ r_indx = ELF32_R_SYM (irela->r_info);
+
+ if (r_type >= (unsigned int) R_METAG_MAX)
+ {
+ bfd_set_error (bfd_error_bad_value);
+ error_ret_free_internal:
+ if (elf_section_data (section)->relocs == NULL)
+ free (internal_relocs);
+ goto error_ret_free_local;
+ }
+
+ /* Only look for stubs on CALLR and B instructions. */
+ if (!(r_type == (unsigned int) R_METAG_RELBRANCH ||
+ r_type == (unsigned int) R_METAG_RELBRANCH_PLT))
+ continue;
+
+ /* Now determine the call target, its name, value,
+ section. */
+ sym_sec = NULL;
+ sym_value = 0;
+ destination = 0;
+ hh = NULL;
+ if (r_indx < symtab_hdr->sh_info)
+ {
+ /* It's a local symbol. */
+ Elf_Internal_Sym *sym;
+ Elf_Internal_Shdr *hdr;
+ unsigned int shndx;
+
+ sym = local_syms + r_indx;
+ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
+ sym_value = sym->st_value;
+ shndx = sym->st_shndx;
+ if (shndx < elf_numsections (input_bfd))
+ {
+ hdr = elf_elfsections (input_bfd)[shndx];
+ sym_sec = hdr->bfd_section;
+ destination = (sym_value + irela->r_addend
+ + sym_sec->output_offset
+ + sym_sec->output_section->vma);
+ }
+ }
+ else
+ {
+ /* It's an external symbol. */
+ int e_indx;
+
+ e_indx = r_indx - symtab_hdr->sh_info;
+ hh = ((struct elf_metag_link_hash_entry *)
+ elf_sym_hashes (input_bfd)[e_indx]);
+
+ while (hh->eh.root.type == bfd_link_hash_indirect
+ || hh->eh.root.type == bfd_link_hash_warning)
+ hh = ((struct elf_metag_link_hash_entry *)
+ hh->eh.root.u.i.link);
+
+ if (hh->eh.root.type == bfd_link_hash_defined
+ || hh->eh.root.type == bfd_link_hash_defweak)
+ {
+ sym_sec = hh->eh.root.u.def.section;
+ sym_value = hh->eh.root.u.def.value;
+ if (hh->eh.plt.offset != (bfd_vma) -1
+ && hh->eh.dynindx != -1
+ && r_type == (unsigned int) R_METAG_RELBRANCH_PLT)
+ {
+ sym_sec = htab->splt;
+ sym_value = hh->eh.plt.offset;
+ }
+
+ if (sym_sec->output_section != NULL)
+ destination = (sym_value + irela->r_addend
+ + sym_sec->output_offset
+ + sym_sec->output_section->vma);
+ else
+ continue;
+ }
+ else if (hh->eh.root.type == bfd_link_hash_undefweak)
+ {
+ if (! info->shared)
+ continue;
+ }
+ else if (hh->eh.root.type == bfd_link_hash_undefined)
+ {
+ if (! (info->unresolved_syms_in_objects == RM_IGNORE
+ && (ELF_ST_VISIBILITY (hh->eh.other)
+ == STV_DEFAULT)))
+ continue;
+ }
+ else
+ {
+ bfd_set_error (bfd_error_bad_value);
+ goto error_ret_free_internal;
+ }
+ }
+
+ /* Determine what (if any) linker stub is needed. */
+ stub_type = metag_type_of_stub (section, irela, hh,
+ destination, info);
+ if (stub_type == metag_stub_none)
+ continue;
+
+ /* Support for grouping stub sections. */
+ id_sec = htab->stub_group[section->id].link_sec;
+
+ /* Get the name of this stub. */
+ stub_name = metag_stub_name (id_sec, sym_sec, hh, irela);
+ if (!stub_name)
+ goto error_ret_free_internal;
+
+ hsh = metag_stub_hash_lookup (&htab->bstab,
+ stub_name,
+ FALSE, FALSE);
+ if (hsh != NULL)
+ {
+ /* The proper stub has already been created. */
+ free (stub_name);
+ continue;
+ }
+
+ hsh = metag_add_stub (stub_name, section, htab);
+ if (hsh == NULL)
+ {
+ free (stub_name);
+ goto error_ret_free_internal;
+ }
+ hsh->target_value = sym_value;
+ hsh->target_section = sym_sec;
+ hsh->stub_type = stub_type;
+ hsh->hh = hh;
+ hsh->addend = irela->r_addend;
+ stub_changed = TRUE;
+ }
+
+ /* We're done with the internal relocs, free them. */
+ if (elf_section_data (section)->relocs == NULL)
+ free (internal_relocs);
+ }
+ }
+
+ if (!stub_changed)
+ break;
+
+ /* OK, we've added some stubs. Find out the new size of the
+ stub sections. */
+ for (stub_sec = htab->stub_bfd->sections;
+ stub_sec != NULL;
+ stub_sec = stub_sec->next)
+ stub_sec->size = 0;
+
+ bfd_hash_traverse (&htab->bstab, metag_size_one_stub, htab);
+
+ /* Ask the linker to do its stuff. */
+ (*htab->layout_sections_again) ();
+ stub_changed = FALSE;
+ }
+
+ free (htab->all_local_syms);
+ return TRUE;
+
+ error_ret_free_local:
+ free (htab->all_local_syms);
+ return FALSE;
+}
+
+/* Build all the stubs associated with the current output file. The
+ stubs are kept in a hash table attached to the main linker hash
+ table. This function is called via metagelf_finish in the linker. */
+
+bfd_boolean
+elf_metag_build_stubs (struct bfd_link_info *info)
+{
+ asection *stub_sec;
+ struct bfd_hash_table *table;
+ struct elf_metag_link_hash_table *htab;
+
+ htab = metag_link_hash_table (info);
+
+ for (stub_sec = htab->stub_bfd->sections;
+ stub_sec != NULL;
+ stub_sec = stub_sec->next)
+ {
+ bfd_size_type size;
+
+ /* Allocate memory to hold the linker stubs. */
+ size = stub_sec->size;
+ stub_sec->contents = bfd_zalloc (htab->stub_bfd, size);
+ if (stub_sec->contents == NULL && size != 0)
+ return FALSE;
+ stub_sec->size = 0;
+ }
+
+ /* Build the stubs as directed by the stub hash table. */
+ table = &htab->bstab;
+ bfd_hash_traverse (table, metag_build_one_stub, info);
+
+ return TRUE;
+}
+
+/* Return TRUE if SYM represents a local label symbol. */
+
+static bfd_boolean
+elf_metag_is_local_label_name (bfd *abfd ATTRIBUTE_UNUSED, const char *name)
+{
+ if (name[0] == '$' && name[1] == 'L')
+ return 1;
+ return _bfd_elf_is_local_label_name (abfd, name);
+}
+
+/* Return address for Ith PLT stub in section PLT, for relocation REL
+ or (bfd_vma) -1 if it should not be included. */
+
+static bfd_vma
+elf_metag_plt_sym_val (bfd_vma i, const asection *plt,
+ const arelent *rel ATTRIBUTE_UNUSED)
+{
+ return plt->vma + (i + 1) * PLT_ENTRY_SIZE;
+}
+
+#define ELF_ARCH bfd_arch_metag
+#define ELF_TARGET_ID METAG_ELF_DATA
+#define ELF_MACHINE_CODE EM_METAG
+#define ELF_MINPAGESIZE 0x1000
+#define ELF_MAXPAGESIZE 0x4000
+#define ELF_COMMONPAGESIZE 0x1000
+
+#define TARGET_LITTLE_SYM bfd_elf32_metag_vec
+#define TARGET_LITTLE_NAME "elf32-metag"
+
+#define elf_symbol_leading_char '_'
+
+#define elf_info_to_howto_rel NULL
+#define elf_info_to_howto metag_info_to_howto_rela
+
+#define bfd_elf32_bfd_is_local_label_name elf_metag_is_local_label_name
+#define bfd_elf32_bfd_link_hash_table_create \
+ elf_metag_link_hash_table_create
+#define bfd_elf32_bfd_link_hash_table_free elf_metag_link_hash_table_free
+#define elf_backend_relocate_section elf_metag_relocate_section
+#define elf_backend_gc_mark_hook elf_metag_gc_mark_hook
+#define elf_backend_gc_sweep_hook elf_metag_gc_sweep_hook
+#define elf_backend_check_relocs elf_metag_check_relocs
+#define elf_backend_create_dynamic_sections elf_metag_create_dynamic_sections
+#define elf_backend_adjust_dynamic_symbol elf_metag_adjust_dynamic_symbol
+#define elf_backend_finish_dynamic_symbol elf_metag_finish_dynamic_symbol
+#define elf_backend_finish_dynamic_sections elf_metag_finish_dynamic_sections
+#define elf_backend_size_dynamic_sections elf_metag_size_dynamic_sections
+#define elf_backend_omit_section_dynsym \
+ ((bfd_boolean (*) (bfd *, struct bfd_link_info *, asection *)) bfd_true)
+#define elf_backend_post_process_headers elf_metag_post_process_headers
+#define elf_backend_reloc_type_class elf_metag_reloc_type_class
+#define elf_backend_copy_indirect_symbol elf_metag_copy_indirect_symbol
+#define elf_backend_plt_sym_val elf_metag_plt_sym_val
+
+#define elf_backend_can_gc_sections 1
+#define elf_backend_can_refcount 1
+#define elf_backend_got_header_size 12
+#define elf_backend_rela_normal 1
+#define elf_backend_want_got_sym 0
+#define elf_backend_want_plt_sym 0
+#define elf_backend_plt_readonly 1
+
+#define bfd_elf32_bfd_reloc_type_lookup metag_reloc_type_lookup
+#define bfd_elf32_bfd_reloc_name_lookup metag_reloc_name_lookup
+
+#include "elf32-target.h"
--- /dev/null
+/* Meta support for 32-bit ELF
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#ifndef _ELF32_METAG_H
+#define _ELF32_METAG_H
+
+extern int elf_metag_setup_section_lists
+ (bfd *, struct bfd_link_info *);
+
+extern void elf_metag_next_input_section
+ (struct bfd_link_info *, asection *);
+
+extern bfd_boolean elf_metag_size_stubs
+ (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma,
+ asection * (*) (const char *, asection *), void (*) (void));
+
+extern bfd_boolean elf_metag_build_stubs
+ (struct bfd_link_info *);
+
+#endif /* _ELF32_METAG_H */
"BFD_RELOC_MEP_GNU_VTINHERIT",
"BFD_RELOC_MEP_GNU_VTENTRY",
+ "BFD_RELOC_METAG_HIADDR16",
+ "BFD_RELOC_METAG_LOADDR16",
+ "BFD_RELOC_METAG_RELBRANCH",
+ "BFD_RELOC_METAG_GETSETOFF",
+ "BFD_RELOC_METAG_HIOG",
+ "BFD_RELOC_METAG_LOOG",
+ "BFD_RELOC_METAG_REL8",
+ "BFD_RELOC_METAG_REL16",
+ "BFD_RELOC_METAG_HI16_GOTOFF",
+ "BFD_RELOC_METAG_LO16_GOTOFF",
+ "BFD_RELOC_METAG_GETSET_GOTOFF",
+ "BFD_RELOC_METAG_GETSET_GOT",
+ "BFD_RELOC_METAG_HI16_GOTPC",
+ "BFD_RELOC_METAG_LO16_GOTPC",
+ "BFD_RELOC_METAG_HI16_PLT",
+ "BFD_RELOC_METAG_LO16_PLT",
+ "BFD_RELOC_METAG_RELBRANCH_PLT",
+ "BFD_RELOC_METAG_GOTOFF",
+ "BFD_RELOC_METAG_PLT",
+ "BFD_RELOC_METAG_COPY",
+ "BFD_RELOC_METAG_JMP_SLOT",
+ "BFD_RELOC_METAG_RELATIVE",
+ "BFD_RELOC_METAG_GLOB_DAT",
+ "BFD_RELOC_METAG_TLS_GD",
+ "BFD_RELOC_METAG_TLS_LDM",
+ "BFD_RELOC_METAG_TLS_LDO_HI16",
+ "BFD_RELOC_METAG_TLS_LDO_LO16",
+ "BFD_RELOC_METAG_TLS_LDO",
+ "BFD_RELOC_METAG_TLS_IE",
+ "BFD_RELOC_METAG_TLS_IENONPIC",
+ "BFD_RELOC_METAG_TLS_IENONPIC_HI16",
+ "BFD_RELOC_METAG_TLS_IENONPIC_LO16",
+ "BFD_RELOC_METAG_TLS_TPOFF",
+ "BFD_RELOC_METAG_TLS_DTPMOD",
+ "BFD_RELOC_METAG_TLS_DTPOFF",
+ "BFD_RELOC_METAG_TLS_LE",
+ "BFD_RELOC_METAG_TLS_LE_HI16",
+ "BFD_RELOC_METAG_TLS_LE_LO16",
"BFD_RELOC_MMIX_GETA",
"BFD_RELOC_MMIX_GETA_1",
"BFD_RELOC_MMIX_GETA_2",
Toshiba Media Processor Relocations.
COMMENT
+ENUM
+ BFD_RELOC_METAG_HIADDR16
+ENUMX
+ BFD_RELOC_METAG_LOADDR16
+ENUMX
+ BFD_RELOC_METAG_RELBRANCH
+ENUMX
+ BFD_RELOC_METAG_GETSETOFF
+ENUMX
+ BFD_RELOC_METAG_HIOG
+ENUMX
+ BFD_RELOC_METAG_LOOG
+ENUMX
+ BFD_RELOC_METAG_REL8
+ENUMX
+ BFD_RELOC_METAG_REL16
+ENUMX
+ BFD_RELOC_METAG_HI16_GOTOFF
+ENUMX
+ BFD_RELOC_METAG_LO16_GOTOFF
+ENUMX
+ BFD_RELOC_METAG_GETSET_GOTOFF
+ENUMX
+ BFD_RELOC_METAG_GETSET_GOT
+ENUMX
+ BFD_RELOC_METAG_HI16_GOTPC
+ENUMX
+ BFD_RELOC_METAG_LO16_GOTPC
+ENUMX
+ BFD_RELOC_METAG_HI16_PLT
+ENUMX
+ BFD_RELOC_METAG_LO16_PLT
+ENUMX
+ BFD_RELOC_METAG_RELBRANCH_PLT
+ENUMX
+ BFD_RELOC_METAG_GOTOFF
+ENUMX
+ BFD_RELOC_METAG_PLT
+ENUMX
+ BFD_RELOC_METAG_COPY
+ENUMX
+ BFD_RELOC_METAG_JMP_SLOT
+ENUMX
+ BFD_RELOC_METAG_RELATIVE
+ENUMX
+ BFD_RELOC_METAG_GLOB_DAT
+ENUMX
+ BFD_RELOC_METAG_TLS_GD
+ENUMX
+ BFD_RELOC_METAG_TLS_LDM
+ENUMX
+ BFD_RELOC_METAG_TLS_LDO_HI16
+ENUMX
+ BFD_RELOC_METAG_TLS_LDO_LO16
+ENUMX
+ BFD_RELOC_METAG_TLS_LDO
+ENUMX
+ BFD_RELOC_METAG_TLS_IE
+ENUMX
+ BFD_RELOC_METAG_TLS_IENONPIC
+ENUMX
+ BFD_RELOC_METAG_TLS_IENONPIC_HI16
+ENUMX
+ BFD_RELOC_METAG_TLS_IENONPIC_LO16
+ENUMX
+ BFD_RELOC_METAG_TLS_TPOFF
+ENUMX
+ BFD_RELOC_METAG_TLS_DTPMOD
+ENUMX
+ BFD_RELOC_METAG_TLS_DTPOFF
+ENUMX
+ BFD_RELOC_METAG_TLS_LE
+ENUMX
+ BFD_RELOC_METAG_TLS_LE_HI16
+ENUMX
+ BFD_RELOC_METAG_TLS_LE_LO16
+ENUMDOC
+ Imagination Technologies Meta relocations.
+
ENUM
BFD_RELOC_MMIX_GETA
ENUMX
extern const bfd_target bfd_elf32_mcore_little_vec;
extern const bfd_target bfd_elf32_mep_vec;
extern const bfd_target bfd_elf32_mep_little_vec;
+extern const bfd_target bfd_elf32_metag_vec;
extern const bfd_target bfd_elf32_microblazeel_vec;
extern const bfd_target bfd_elf32_microblaze_vec;
extern const bfd_target bfd_elf32_mn10200_vec;
&bfd_elf32_mcore_big_vec,
&bfd_elf32_mcore_little_vec,
&bfd_elf32_mep_vec,
+ &bfd_elf32_metag_vec,
&bfd_elf32_microblaze_vec,
&bfd_elf32_mn10200_vec,
&bfd_elf32_mn10300_vec,
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * binutils/readelf.c: (guess_is_rela): Add EM_METAG.
+ (dump_relocations): Add EM_METAG.
+ (get_machine_name): Correct case for Meta.
+ (is_32bit_abs_reloc): Add support for Meta ADDR32 reloc.
+ (is_none_reloc): Add support for Meta NONE reloc.
+
2013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
* readelf.c (get_note_type): Handle NT_ARM_TLS, NT_ARM_HW_BREAK
#include "elf/m68hc11.h"
#include "elf/mcore.h"
#include "elf/mep.h"
+#include "elf/metag.h"
#include "elf/microblaze.h"
#include "elf/mips.h"
#include "elf/mmix.h"
case EM_M32R:
case EM_MCORE:
case EM_CYGNUS_MEP:
+ case EM_METAG:
case EM_MMIX:
case EM_MN10200:
case EM_CYGNUS_MN10200:
rtype = elf_rx_reloc_type (type);
break;
+ case EM_METAG:
+ rtype = elf_metag_reloc_type (type);
+ break;
+
case EM_XC16X:
case EM_C166:
rtype = elf_xc16x_reloc_type (type);
case EM_MICROBLAZE_OLD: return "Xilinx MicroBlaze";
case EM_RL78: return "Renesas RL78";
case EM_RX: return "Renesas RX";
- case EM_METAG: return "Imagination Technologies META processor architecture";
+ case EM_METAG: return "Imagination Technologies Meta processor architecture";
case EM_MCST_ELBRUS: return "MCST Elbrus general purpose hardware architecture";
case EM_ECOG16: return "Cyan Technology eCOG16 family";
case EM_ETPU: return "Freescale Extended Time Processing Unit";
return reloc_type == 1; /* R_MCORE_ADDR32. */
case EM_CYGNUS_MEP:
return reloc_type == 4; /* R_MEP_32. */
+ case EM_METAG:
+ return reloc_type == 2; /* R_METAG_ADDR32. */
case EM_MICROBLAZE:
return reloc_type == 1; /* R_MICROBLAZE_32. */
case EM_MIPS:
|| reloc_type == 17 /* R_XTENSA_DIFF8. */
|| reloc_type == 18 /* R_XTENSA_DIFF16. */
|| reloc_type == 19 /* R_XTENSA_DIFF32. */);
+ case EM_METAG:
+ return reloc_type == 3; /* R_METAG_NONE. */
}
return FALSE;
}
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * Makefile.am: Add Meta.
+ * Makefile.in: Regenerate.
+ * config/tc-metag.c: New file.
+ * config/tc-metag.h: New file.
+ * configure.tgt: Add Meta.
+ * doc/Makefile.am: Add Meta.
+ * doc/Makefile.in: Regenerate.
+ * doc/all.texi: Add Meta.
+ * doc/as.texiinfo: Document Meta options.
+ * doc/c-metag.texi: New file.
+
2013-01-09 Steve Ellcey <sellcey@mips.com>
* config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal
config/tc-m68k.c \
config/tc-mcore.c \
config/tc-mep.c \
+ config/tc-metag.c \
config/tc-microblaze.c \
config/tc-mips.c \
config/tc-mmix.c \
config/tc-m68k.h \
config/tc-mcore.h \
config/tc-mep.h \
+ config/tc-metag.h \
config/tc-microblaze.h \
config/tc-mips.h \
config/tc-mmix.h \
config/tc-m68k.c \
config/tc-mcore.c \
config/tc-mep.c \
+ config/tc-metag.c \
config/tc-microblaze.c \
config/tc-mips.c \
config/tc-mmix.c \
config/tc-m68k.h \
config/tc-mcore.h \
config/tc-mep.h \
+ config/tc-metag.h \
config/tc-microblaze.h \
config/tc-mips.h \
config/tc-mmix.h \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-m68k.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-mcore.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-mep.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-metag.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-microblaze.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-mips.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-mmix.Po@am__quote@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-mep.obj `if test -f 'config/tc-mep.c'; then $(CYGPATH_W) 'config/tc-mep.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-mep.c'; fi`
+tc-metag.o: config/tc-metag.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-metag.o -MD -MP -MF $(DEPDIR)/tc-metag.Tpo -c -o tc-metag.o `test -f 'config/tc-metag.c' || echo '$(srcdir)/'`config/tc-metag.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-metag.Tpo $(DEPDIR)/tc-metag.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-metag.c' object='tc-metag.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-metag.o `test -f 'config/tc-metag.c' || echo '$(srcdir)/'`config/tc-metag.c
+
+tc-metag.obj: config/tc-metag.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-metag.obj -MD -MP -MF $(DEPDIR)/tc-metag.Tpo -c -o tc-metag.obj `if test -f 'config/tc-metag.c'; then $(CYGPATH_W) 'config/tc-metag.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-metag.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-metag.Tpo $(DEPDIR)/tc-metag.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-metag.c' object='tc-metag.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-metag.obj `if test -f 'config/tc-metag.c'; then $(CYGPATH_W) 'config/tc-metag.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-metag.c'; fi`
+
tc-microblaze.o: config/tc-microblaze.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-microblaze.o -MD -MP -MF $(DEPDIR)/tc-microblaze.Tpo -c -o tc-microblaze.o `test -f 'config/tc-microblaze.c' || echo '$(srcdir)/'`config/tc-microblaze.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-microblaze.Tpo $(DEPDIR)/tc-microblaze.Po
-*- text -*-
+* Add support for the Imagination Technologies Meta processor.
+
* Add support for the v850e3v5.
Changes in 2.23:
--- /dev/null
+/* tc-metag.c -- Assembler for the Imagination Technologies Meta.
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#include "as.h"
+#include "subsegs.h"
+#include "symcat.h"
+#include "safe-ctype.h"
+#include "hashtab.h"
+#include "libbfd.h"
+
+#include <stdio.h>
+
+#include "opcode/metag.h"
+
+const char comment_chars[] = "!";
+const char line_comment_chars[] = "!#";
+const char line_separator_chars[] = ";";
+const char FLT_CHARS[] = "rRsSfFdDxXpP";
+const char EXP_CHARS[] = "eE";
+const char metag_symbol_chars[] = "[";
+
+static char register_chars[256];
+static char mnemonic_chars[256];
+
+#define is_register_char(x) (register_chars[(unsigned char) x])
+#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
+#define is_whitespace_char(x) (((x) == ' ') || ((x) == '\t'))
+#define is_space_char(x) ((x) == ' ')
+
+#define FPU_PREFIX_CHAR 'f'
+#define DSP_PREFIX_CHAR 'd'
+
+/* Instruction mnemonics that need disambiguating with respect to prefixes. */
+#define FFB_INSN "ffb"
+#define DCACHE_INSN "dcache"
+#define DEFR_INSN "defr"
+
+#define FPU_DOUBLE_CHAR 'd'
+#define FPU_PAIR_CHAR 'l'
+
+#define DSP_DUAL_CHAR 'l'
+
+#define END_OF_INSN '\0'
+
+/* Maximum length of a mnemonic including all suffixes. */
+#define MAX_MNEMONIC_LEN 16
+/* Maximum length of a register name. */
+#define MAX_REG_LEN 17
+
+/* Addressing modes must be enclosed with square brackets. */
+#define ADDR_BEGIN_CHAR '['
+#define ADDR_END_CHAR ']'
+/* Immediates must be prefixed with a hash. */
+#define IMM_CHAR '#'
+
+#define COMMA ','
+#define PLUS '+'
+#define MINUS '-'
+
+/* Short units are those that can be encoded with 2 bits. */
+#define SHORT_UNITS "D0, D1, A0 or A1"
+
+static unsigned int mcpu_opt = CoreMeta12;
+static unsigned int mfpu_opt = 0;
+static unsigned int mdsp_opt = 0;
+
+const char * md_shortopts = "m:";
+
+struct option md_longopts[] =
+{
+ {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+/* Parser hash tables. */
+static htab_t mnemonic_htab;
+static htab_t reg_htab;
+static htab_t dsp_reg_htab;
+static htab_t dsp_tmpl_reg_htab[2];
+static htab_t scond_htab;
+
+#define GOT_NAME "__GLOBAL_OFFSET_TABLE__"
+symbolS * GOT_symbol;
+
+enum fpu_insn_width {
+ FPU_WIDTH_SINGLE,
+ FPU_WIDTH_DOUBLE,
+ FPU_WIDTH_PAIR,
+};
+
+#define FPU_ACTION_ABS_CHAR 'a'
+#define FPU_ACTION_INV_CHAR 'i'
+#define FPU_ACTION_QUIET_CHAR 'q'
+#define FPU_ACTION_ZERO_CHAR 'z'
+
+#define FPU_ACTION_ABS 0x1
+#define FPU_ACTION_INV 0x2
+#define FPU_ACTION_QUIET 0x4
+#define FPU_ACTION_ZERO 0x8
+
+enum dsp_insn_width {
+ DSP_WIDTH_SINGLE,
+ DSP_WIDTH_DUAL,
+};
+
+#define DSP_ACTION_QR64_CHAR 'q'
+#define DSP_ACTION_UMUL_CHAR 'u'
+#define DSP_ACTION_ROUND_CHAR 'r'
+#define DSP_ACTION_CLAMP9_CHAR 'g'
+#define DSP_ACTION_CLAMP8_CHAR 'b'
+#define DSP_ACTION_MOD_CHAR 'm'
+#define DSP_ACTION_ACC_ZERO_CHAR 'z'
+#define DSP_ACTION_ACC_ADD_CHAR 'p'
+#define DSP_ACTION_ACC_SUB_CHAR 'n'
+#define DSP_ACTION_OV_CHAR 'o'
+
+#define DSP_ACTION_QR64 0x001
+#define DSP_ACTION_UMUL 0x002
+#define DSP_ACTION_ROUND 0x004
+#define DSP_ACTION_CLAMP9 0x008
+#define DSP_ACTION_CLAMP8 0x010
+#define DSP_ACTION_MOD 0x020
+#define DSP_ACTION_ACC_ZERO 0x040
+#define DSP_ACTION_ACC_ADD 0x080
+#define DSP_ACTION_ACC_SUB 0x100
+#define DSP_ACTION_OV 0x200
+
+#define DSP_DAOPPAME_8_CHAR 'b'
+#define DSP_DAOPPAME_16_CHAR 'w'
+#define DSP_DAOPPAME_TEMP_CHAR 't'
+#define DSP_DAOPPAME_HIGH_CHAR 'h'
+
+#define DSP_DAOPPAME_8 0x1
+#define DSP_DAOPPAME_16 0x2
+#define DSP_DAOPPAME_TEMP 0x4
+#define DSP_DAOPPAME_HIGH 0x8
+
+/* Structure holding information about a parsed instruction. */
+typedef struct {
+ /* Instruction type. */
+ enum insn_type type;
+ /* Split condition code. */
+ enum scond_code scond;
+
+ /* Instruction bits. */
+ unsigned int bits;
+ /* Size of the instruction in bytes. */
+ size_t len;
+
+ /* FPU instruction encoding. */
+ enum fpu_insn_width fpu_width;
+ unsigned int fpu_action_flags;
+
+ /* DSP instruction encoding. */
+ enum dsp_insn_width dsp_width;
+ unsigned int dsp_action_flags;
+ unsigned int dsp_daoppame_flags;
+
+ /* Reloc encoding information, maximum of one reloc per insn. */
+ enum bfd_reloc_code_real reloc_type;
+ int reloc_pcrel;
+ expressionS reloc_exp;
+ unsigned int reloc_size;
+} metag_insn;
+
+/* Structure holding information about a parsed addressing mode. */
+typedef struct {
+ const metag_reg *base_reg;
+ const metag_reg *offset_reg;
+
+ expressionS exp;
+
+ enum bfd_reloc_code_real reloc_type;
+
+ /* Whether we have an immediate or not. */
+ unsigned short immediate:1;
+ /* Whether or not the base register is updated. */
+ unsigned short update:1;
+ /* Whether the operation uses the address pre or post increment. */
+ unsigned short post_increment:1;
+ /* Whether the immediate should be negated. */
+ unsigned short negate:1;
+} metag_addr;
+
+/* Linked list of possible parsers for this instruction. */
+typedef struct _insn_templates {
+ const insn_template *template;
+ struct _insn_templates *next;
+} insn_templates;
+
+/* Parse an instruction that takes no operands. */
+static const char *
+parse_none (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ insn->bits = template->meta_opcode;
+ insn->len = 4;
+ return line;
+}
+
+/* Return the next non-whitespace character in LINE or NULL. */
+static const char *
+skip_whitespace (const char *line)
+{
+ const char *l = line;
+
+ if (is_whitespace_char (*l))
+ {
+ l++;
+ }
+
+ return l;
+}
+
+/* Return the next non-space character in LINE or NULL. */
+static const char *
+skip_space (const char *line)
+{
+ const char *l = line;
+
+ if (is_space_char (*l))
+ {
+ l++;
+ }
+
+ return l;
+}
+
+/* Return the character after the current one in LINE if the current
+ character is a comma, otherwise NULL. */
+static const char *
+skip_comma (const char *line)
+{
+ const char *l = line;
+
+ if (l == NULL || *l != COMMA)
+ return NULL;
+
+ l++;
+
+ return l;
+}
+
+/* Return the metag_reg struct corresponding to NAME or NULL if no such
+ register exists. */
+static const metag_reg *
+parse_gp_reg (const char *name)
+{
+ const metag_reg *reg;
+ metag_reg entry;
+
+ entry.name = name;
+
+ reg = (const metag_reg *) htab_find (reg_htab, &entry);
+
+ return reg;
+}
+
+/* Parse a list of up to COUNT GP registers from LINE, returning the
+ registers parsed in REGS and the number parsed in REGS_READ. Return
+ a pointer to the next character or NULL. */
+static const char *
+parse_gp_regs_list (const char *line, const metag_reg **regs, size_t count,
+ size_t *regs_read)
+{
+ const char *l = line;
+ char reg_buf[MAX_REG_LEN];
+ int seen_regs = 0;
+ size_t i;
+
+ for (i = 0; i < count; i++)
+ {
+ size_t len = 0;
+ const char *next;
+
+ next = l;
+
+ if (i > 0)
+ {
+ l = skip_comma (l);
+ if (l == NULL)
+ {
+ *regs_read = seen_regs;
+ return next;
+ }
+ }
+
+ while (is_register_char (*l))
+ {
+ reg_buf[len] = *l;
+ l++;
+ len++;
+ if (!(len < MAX_REG_LEN))
+ return NULL;
+ }
+
+ reg_buf[len] = '\0';
+
+ if (len)
+ {
+ const metag_reg *reg = parse_gp_reg (reg_buf);
+
+ if (!reg)
+ {
+ *regs_read = seen_regs;
+ return next;
+ }
+ else
+ {
+ regs[i] = reg;
+ seen_regs++;
+ }
+ }
+ else
+ {
+ *regs_read = seen_regs;
+ return next;
+ }
+ }
+
+ *regs_read = seen_regs;
+ return l;
+}
+
+/* Parse a list of exactly COUNT GP registers from LINE, returning the
+ registers parsed in REGS. Return a pointer to the next character or NULL. */
+static const char *
+parse_gp_regs (const char *line, const metag_reg **regs, size_t count)
+{
+ const char *l = line;
+ size_t regs_read = 0;
+
+ l = parse_gp_regs_list (l, regs, count, ®s_read);
+
+ if (regs_read != count)
+ return NULL;
+ else
+ return l;
+}
+
+/* Parse a list of exactly COUNT FPU registers from LINE, returning the
+ registers parsed in REGS. Return a pointer to the next character or NULL. */
+static const char *
+parse_fpu_regs (const char *line, const metag_reg **regs, size_t count)
+{
+ const char *l = line;
+ size_t regs_read = 0;
+
+ l = parse_gp_regs_list (l, regs, count, ®s_read);
+
+ if (regs_read != count)
+ return NULL;
+ else
+ {
+ size_t i;
+ for (i = 0; i < count; i++)
+ {
+ if (regs[i]->unit != UNIT_FX)
+ return NULL;
+ }
+ return l;
+ }
+}
+
+/* Return TRUE if REG1 and REG2 are in paired units. */
+static bfd_boolean
+is_unit_pair (const metag_reg *reg1, const metag_reg *reg2)
+{
+ if ((reg1->unit == UNIT_A0 &&
+ (reg2->unit == UNIT_A1)) ||
+ (reg1->unit == UNIT_A1 &&
+ (reg2->unit == UNIT_A0)) ||
+ (reg1->unit == UNIT_D0 &&
+ (reg2->unit == UNIT_D1)) ||
+ (reg1->unit == UNIT_D1 &&
+ (reg2->unit == UNIT_D0)))
+ return TRUE;
+
+ return FALSE;
+}
+
+/* Return TRUE if REG1 and REG2 form a register pair. */
+static bfd_boolean
+is_reg_pair (const metag_reg *reg1, const metag_reg *reg2)
+{
+ if (reg1->unit == UNIT_FX &&
+ reg2->unit == UNIT_FX &&
+ reg2->no == reg1->no + 1)
+ return TRUE;
+
+ if (reg1->no != reg2->no)
+ return FALSE;
+
+ return is_unit_pair (reg1, reg2);
+}
+
+/* Parse a pair of GP registers from LINE, returning the registers parsed
+ in REGS. Return a pointer to the next character or NULL. */
+static const char *
+parse_pair_gp_regs (const char *line, const metag_reg **regs)
+{
+ const char *l = line;
+
+ l = parse_gp_regs (line, regs, 2);
+
+ if (l == NULL)
+ {
+ l = parse_gp_regs (line, regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs[0]->unit == UNIT_RD)
+ return l;
+ else
+ return NULL;
+ }
+
+ if (is_reg_pair (regs[0], regs[1]))
+ return l;
+
+ return NULL;
+}
+
+/* Parse a unit-to-unit MOV instruction. */
+static const char *
+parse_mov_u2u (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const metag_reg *regs[2];
+
+ line = parse_gp_regs (line, regs, 2);
+
+ if (line == NULL)
+ return NULL;
+
+ if (!mfpu_opt && (regs[0]->unit == UNIT_FX || regs[1]->unit == UNIT_FX))
+ {
+ as_bad (_("no floating point unit specified"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (regs[1]->no << 19) |
+ (regs[0]->no << 14) |
+ (regs[1]->unit << 10) |
+ (regs[0]->unit << 5));
+ insn->len = 4;
+ return line;
+}
+
+/* Parse a MOV to port instruction. */
+static const char *
+parse_mov_port (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ unsigned int is_movl = MINOR_OPCODE (template->meta_opcode) == MOVL_MINOR;
+ const metag_reg *dest_regs[2];
+ const metag_reg *port_regs[1];
+
+ if (is_movl)
+ l = parse_gp_regs (l, dest_regs, 2);
+ else
+ l = parse_gp_regs (l, dest_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (template->insn_type == INSN_FPU && dest_regs[0]->unit != UNIT_FX)
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_gp_regs (l, port_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (port_regs[0]->unit != UNIT_RD ||
+ port_regs[0]->no != 0)
+ return NULL;
+
+ if (is_movl)
+ {
+ if (!is_unit_pair (dest_regs[0], dest_regs[1]))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 14) |
+ (dest_regs[1]->no << 9) |
+ ((dest_regs[0]->unit & SHORT_UNIT_MASK) << 5));
+ }
+ else
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 14) |
+ (dest_regs[0]->unit << 5));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a MOVL to TTREC instruction. */
+static const char *
+parse_movl_ttrec (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *src_regs[2];
+ const metag_reg *dest_regs[1];
+
+ l = parse_gp_regs (l, dest_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (dest_regs[0]->unit != UNIT_TT ||
+ dest_regs[0]->no != 3)
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_gp_regs (l, src_regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!is_unit_pair (src_regs[0], src_regs[1]))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (src_regs[0]->no << 19) |
+ (src_regs[1]->no << 14) |
+ ((src_regs[0]->unit & SHORT_UNIT_MASK) << 7));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an incrementing or decrementing addressing mode. */
+static const char *
+parse_addr_incr_op (const char *line, metag_addr *addr)
+{
+ const char *l = line;
+ const char *ll;
+
+ ll = l + 1;
+
+ if (*l == PLUS &&
+ *ll == PLUS)
+ {
+ addr->update = 1;
+ ll++;
+ return ll;
+ }
+ else if (*l == MINUS &&
+ *ll == MINUS)
+ {
+ addr->update = 1;
+ addr->negate = 1;
+ ll++;
+ return ll;
+ }
+ return NULL;
+}
+
+/* Parse an pre-incrementing or pre-decrementing addressing mode. */
+static const char *
+parse_addr_pre_incr_op (const char *line, metag_addr *addr)
+{
+ return parse_addr_incr_op (line, addr);
+}
+
+/* Parse an post-incrementing or post-decrementing addressing mode. */
+static const char *
+parse_addr_post_incr_op (const char *line, metag_addr *addr)
+{
+ const char *l;
+
+ l = parse_addr_incr_op (line, addr);
+
+ if (l == NULL)
+ return NULL;
+
+ addr->post_increment = 1;
+
+ return l;
+}
+
+/* Parse an infix addressing mode. */
+static const char *
+parse_addr_op (const char *line, metag_addr *addr)
+{
+ const char *l = line;
+ const char *ll;
+
+ ll = l + 1;
+
+ if (*l == PLUS)
+ {
+ if (*ll == PLUS)
+ {
+ addr->update = 1;
+ ll++;
+ return ll;
+ }
+ l++;
+ return l;
+ }
+ return NULL;
+}
+
+/* Parse the immediate portion of an addrssing mode. */
+static const char *
+parse_imm_addr (const char *line, metag_addr *addr)
+{
+ const char *l = line;
+ char *save_input_line_pointer;
+ expressionS *exp = &addr->exp;
+
+ /* Skip #. */
+ if (*l == '#')
+ l++;
+ else
+ return NULL;
+
+ save_input_line_pointer = input_line_pointer;
+ input_line_pointer = (char *) l;
+
+ expression (exp);
+
+ l = input_line_pointer;
+ input_line_pointer = save_input_line_pointer;
+
+ if (exp->X_op == O_absent || exp->X_op == O_big)
+ {
+ return NULL;
+ }
+ else if (exp->X_op == O_constant)
+ {
+ return l;
+ }
+ else
+ {
+ if (exp->X_op == O_PIC_reloc &&
+ exp->X_md == BFD_RELOC_METAG_GETSET_GOT)
+ {
+ exp->X_op = O_symbol;
+ addr->reloc_type = BFD_RELOC_METAG_GETSET_GOT;
+ }
+ else if (exp->X_op == O_PIC_reloc &&
+ exp->X_md == BFD_RELOC_METAG_TLS_IE)
+ {
+ exp->X_op = O_symbol;
+ addr->reloc_type = BFD_RELOC_METAG_TLS_IE;
+ }
+ else if (exp->X_op == O_PIC_reloc &&
+ exp->X_md == BFD_RELOC_METAG_GOTOFF)
+ {
+ exp->X_op = O_symbol;
+ addr->reloc_type = BFD_RELOC_METAG_GETSET_GOTOFF;
+ }
+ else
+ addr->reloc_type = BFD_RELOC_METAG_GETSETOFF;
+ return l;
+ }
+}
+
+/* Parse the offset portion of an addressing mode (register or immediate). */
+static const char *
+parse_addr_offset (const char *line, metag_addr *addr, int size)
+{
+ const char *l = line;
+ const metag_reg *regs[1];
+
+ if (*l == IMM_CHAR)
+ {
+ /* ++ is a valid operator in our addressing but not in an expr. Make
+ sure that the expression parser never sees it. */
+ char *ppp = strstr(l, "++");
+ char ppch = '+';
+
+ if (ppp)
+ *ppp = '\0';
+
+ l = parse_imm_addr (l, addr);
+
+ if (ppp)
+ *ppp = ppch;
+
+ if (l == NULL)
+ return NULL;
+
+ if (addr->exp.X_add_number % size)
+ {
+ as_bad (_("offset must be a multiple of %d"), size);
+ return NULL;
+ }
+
+ addr->immediate = 1;
+ return l;
+ }
+ else
+ {
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs[0]->unit != addr->base_reg->unit)
+ {
+ as_bad (_("offset and base must be from the same unit"));
+ return NULL;
+ }
+
+ addr->offset_reg = regs[0];
+ return l;
+ }
+}
+
+/* Parse an addressing mode. */
+static const char *
+parse_addr (const char *line, metag_addr *addr, unsigned int size)
+{
+ const char *l = line;
+ const char *ll;
+ const metag_reg *regs[1];
+
+ /* Skip opening square bracket. */
+ l++;
+
+ ll = parse_addr_pre_incr_op (l, addr);
+
+ if (ll != NULL)
+ l = ll;
+
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ addr->base_reg = regs[0];
+
+ if (*l == ADDR_END_CHAR)
+ {
+ addr->exp.X_op = O_constant;
+ addr->exp.X_add_symbol = NULL;
+ addr->exp.X_op_symbol = NULL;
+ if (addr->update == 1)
+ {
+ /* We have a pre increment/decrement. */
+ addr->exp.X_add_number = size;
+ }
+ else
+ {
+ /* Simple register with no offset (0 immediate). */
+ addr->exp.X_add_number = 0;
+ }
+ addr->immediate = 1;
+ l++;
+ return l;
+ }
+
+ /* We already had a pre increment/decrement. */
+ if (addr->update == 1)
+ return NULL;
+
+ ll = parse_addr_post_incr_op (l, addr);
+
+ if (ll && *ll == ADDR_END_CHAR)
+ {
+ if (addr->update == 1)
+ {
+ /* We have a post increment/decrement. */
+ addr->exp.X_op = O_constant;
+ addr->exp.X_add_number = size;
+ addr->exp.X_add_symbol = NULL;
+ addr->exp.X_op_symbol = NULL;
+ addr->post_increment = 1;
+ }
+ addr->immediate = 1;
+ ll++;
+ return ll;
+ }
+
+ addr->post_increment = 0;
+
+ l = parse_addr_op (l, addr);
+
+ if (l == NULL)
+ return NULL;
+
+ l = parse_addr_offset (l, addr, size);
+
+ if (l == NULL)
+ return NULL;
+
+ if (*l == ADDR_END_CHAR)
+ {
+ l++;
+ return l;
+ }
+
+ /* We already had a pre increment/decrement. */
+ if (addr->update == 1)
+ return NULL;
+
+ l = parse_addr_post_incr_op (l, addr);
+
+ if (l == NULL)
+ return NULL;
+
+ if (*l == ADDR_END_CHAR)
+ {
+ l++;
+ return l;
+ }
+
+ return NULL;
+}
+
+/* Parse a GET or pipeline MOV instruction. */
+static const char *
+parse_get (const char *line, const metag_reg **regs, metag_addr *addr,
+ unsigned int size, bfd_boolean is_mov)
+{
+ const char *l = line;
+
+ if (size == 8)
+ {
+ l = parse_pair_gp_regs (l, regs);
+
+ if (l == NULL)
+ return NULL;
+ }
+ else
+ {
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL)
+ {
+ if (!is_mov)
+ as_bad (_("invalid destination register"));
+ return NULL;
+ }
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_addr (l, addr, size);
+
+ if (l == NULL)
+ {
+ if (!is_mov)
+ as_bad (_("invalid memory operand"));
+ return NULL;
+ }
+
+ return l;
+}
+
+/* Parse a SET instruction. */
+static const char *
+parse_set (const char *line, const metag_reg **regs, metag_addr *addr,
+ unsigned int size)
+{
+ const char *l = line;
+
+ l = parse_addr (l, addr, size);
+
+ if (l == NULL)
+ {
+ as_bad (_("invalid memory operand"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ if (size == 8)
+ {
+ const char *ll = l;
+
+ ll = parse_pair_gp_regs (l, regs);
+
+ if (ll == NULL)
+ {
+ /* Maybe this is an RD register, which is 64 bits wide so needs no
+ pair. */
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL ||
+ regs[0]->unit != UNIT_RD)
+ {
+ return NULL;
+ }
+ }
+ else
+ l = ll;
+ }
+ else
+ {
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL)
+ {
+ as_bad (_("invalid source register"));
+ return NULL;
+ }
+ }
+
+ return l;
+}
+
+/* Check a signed integer value can be represented in the given number
+ of bits. */
+static bfd_boolean
+within_signed_range (int value, unsigned int bits)
+{
+ int min_val = -(1 << (bits - 1));
+ int max_val = (1 << (bits - 1)) - 1;
+ return (value <= max_val) && (value >= min_val);
+}
+
+/* Check an unsigned integer value can be represented in the given number
+ of bits. */
+static bfd_boolean
+within_unsigned_range (unsigned int value, unsigned int bits)
+{
+ return value < (unsigned int)(1 << bits);
+}
+
+/* Return TRUE if UNIT can be expressed using a short code. */
+static bfd_boolean
+is_short_unit (enum metag_unit unit)
+{
+ switch (unit)
+ {
+ case UNIT_A0:
+ case UNIT_A1:
+ case UNIT_D0:
+ case UNIT_D1:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+}
+
+/* Copy reloc data from ADDR to INSN. */
+static void
+copy_addr_reloc (metag_insn *insn, metag_addr *addr)
+{
+ memcpy (&insn->reloc_exp, &addr->exp, sizeof(insn->reloc_exp));
+ insn->reloc_type = addr->reloc_type;
+}
+
+/* Parse a GET, SET or pipeline MOV instruction. */
+static const char *
+parse_get_set (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+ metag_addr addr;
+ unsigned int size = metag_get_set_size_bytes (template->meta_opcode);
+ bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ unsigned int reg_no;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ if (is_get)
+ {
+ bfd_boolean is_mov = strncmp (template->name, "MOV", 3) == 0;
+
+ l = parse_get (l, regs, &addr, size, is_mov);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!(regs[0]->unit == UNIT_D0 ||
+ regs[0]->unit == UNIT_D1 ||
+ regs[0]->unit == UNIT_A0 ||
+ regs[0]->unit == UNIT_A1 ||
+ (regs[0]->unit == UNIT_RD && is_mov) ||
+ (regs[0]->unit == UNIT_CT && size == 4) ||
+ (regs[0]->unit == UNIT_PC && size == 4) ||
+ (regs[0]->unit == UNIT_TR && size == 4) ||
+ (regs[0]->unit == UNIT_TT && (size == 4 || size == 8)) ||
+ regs[0]->unit == UNIT_FX))
+ {
+ as_bad (_("invalid destination unit"));
+ return NULL;
+ }
+
+ if (regs[0]->unit == UNIT_RD)
+ {
+ if (regs[0]->no == 0)
+ {
+ as_bad (_("mov cannot use RD port as destination"));
+ return NULL;
+ }
+ }
+
+ reg_no = regs[0]->no;
+ }
+ else
+ {
+ l = parse_set (l, regs, &addr, size);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!(regs[0]->unit == UNIT_D0 ||
+ regs[0]->unit == UNIT_D1 ||
+ regs[0]->unit == UNIT_A0 ||
+ regs[0]->unit == UNIT_A1 ||
+ regs[0]->unit == UNIT_RD ||
+ (regs[0]->unit == UNIT_CT && size == 4) ||
+ (regs[0]->unit == UNIT_PC && size == 4) ||
+ (regs[0]->unit == UNIT_TR && size == 4) ||
+ (regs[0]->unit == UNIT_TT && (size == 4 || size == 8)) ||
+ regs[0]->unit == UNIT_FX))
+ {
+ as_bad (_("invalid source unit"));
+ return NULL;
+ }
+
+ if (addr.immediate == 0 &&
+ (regs[0]->unit == addr.base_reg->unit ||
+ (size == 8 && is_unit_pair (regs[0], addr.base_reg))))
+ {
+ as_bad (_("source and address units must not be shared for this addressing mode"));
+ return NULL;
+ }
+
+ if (regs[0]->unit == UNIT_RD)
+ {
+ if (regs[0]->no != 0)
+ {
+ as_bad (_("set can only use RD port as source"));
+ return NULL;
+ }
+ reg_no = 16;
+ }
+ else
+ reg_no = regs[0]->no;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (reg_no << 19) |
+ (regs[0]->unit << 1));
+
+ if (!is_short_unit (addr.base_reg->unit))
+ {
+ as_bad (_("base unit must be one of %s"), SHORT_UNITS);
+ return NULL;
+ }
+
+ insn->bits |= ((addr.base_reg->no << 14) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5));
+
+ if (addr.immediate)
+ {
+ int offset = addr.exp.X_add_number;
+
+ copy_addr_reloc (insn, &addr);
+
+ if (addr.negate)
+ offset = -offset;
+
+ offset = offset / (int)size;
+
+ if (!within_signed_range (offset, GET_SET_IMM_BITS))
+ {
+ /* We already tried to encode as an extended GET/SET. */
+ as_bad (_("offset value out of range"));
+ return NULL;
+ }
+
+ offset = offset & GET_SET_IMM_MASK;
+
+ insn->bits |= (0x1 << 25);
+ insn->bits |= (offset << 8);
+ }
+ else
+ {
+ insn->bits |= (addr.offset_reg->no << 9);
+ }
+
+ if (addr.update)
+ insn->bits |= (0x1 << 7);
+
+ if (addr.post_increment)
+ insn->bits |= 0x1;
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an extended GET or SET instruction. */
+static const char *
+parse_get_set_ext (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+ metag_addr addr;
+ unsigned int size = metag_get_set_ext_size_bytes (template->meta_opcode);
+ bfd_boolean is_get = MINOR_OPCODE (template->meta_opcode) == GET_EXT_MINOR;
+ bfd_boolean is_mov = MINOR_OPCODE (template->meta_opcode) == MOV_EXT_MINOR;
+ unsigned int reg_unit;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ if (is_get || is_mov)
+ {
+ l = parse_get (l, regs, &addr, size, is_mov);
+ }
+ else
+ {
+ l = parse_set (l, regs, &addr, size);
+ }
+
+ if (l == NULL)
+ return NULL;
+
+ /* Extended GET/SET does not support incrementing addressing. */
+ if (addr.update)
+ return NULL;
+
+ if (is_mov)
+ {
+ if (regs[0]->unit != UNIT_RD)
+ {
+ as_bad (_("destination unit must be RD"));
+ return NULL;
+ }
+ reg_unit = 0;
+ }
+ else
+ {
+ if (!is_short_unit (regs[0]->unit))
+ {
+ return NULL;
+ }
+ reg_unit = regs[0]->unit;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ ((reg_unit & SHORT_UNIT_MASK) << 3));
+
+ if (!is_short_unit (addr.base_reg->unit))
+ {
+ as_bad (_("base unit must be one of %s"), SHORT_UNITS);
+ return NULL;
+ }
+
+ if (addr.base_reg->no > 1)
+ {
+ return NULL;
+ }
+
+ insn->bits |= ((addr.base_reg->no & EXT_BASE_REG_MASK) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5));
+
+ if (addr.immediate)
+ {
+ int offset = addr.exp.X_add_number;
+
+ copy_addr_reloc (insn, &addr);
+
+ if (addr.negate)
+ offset = -offset;
+
+ offset = offset / (int)size;
+
+ if (!within_signed_range (offset, GET_SET_EXT_IMM_BITS))
+ {
+ /* Parsing as a standard GET/SET provides a smaller offset. */
+ as_bad (_("offset value out of range"));
+ return NULL;
+ }
+
+ offset = offset & GET_SET_EXT_IMM_MASK;
+
+ insn->bits |= (offset << 7);
+ }
+ else
+ {
+ return NULL;
+ }
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an MGET or MSET instruction addressing mode. */
+static const char *
+parse_mget_mset_addr (const char *line, metag_addr *addr)
+{
+ const char *l = line;
+ const char *ll;
+ const metag_reg *regs[1];
+
+ /* Skip opening square bracket. */
+ l++;
+
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ addr->base_reg = regs[0];
+
+ ll = parse_addr_post_incr_op (l, addr);
+
+ if (ll != NULL)
+ l = ll;
+
+ if (addr->negate == 1)
+ return NULL;
+
+ if (*l == ADDR_END_CHAR)
+ {
+ l++;
+ return l;
+ }
+
+ return NULL;
+}
+
+/* Parse an MGET instruction. */
+static const char *
+parse_mget (const char *line, const metag_reg **regs, metag_addr *addr,
+ size_t *regs_read)
+{
+ const char *l = line;
+
+ l = parse_gp_regs_list (l, regs, MGET_MSET_MAX_REGS, regs_read);
+
+ if (l == NULL ||
+ *regs_read == 0)
+ {
+ as_bad (_("invalid destination register list"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_mget_mset_addr (l, addr);
+
+ if (l == NULL)
+ {
+ as_bad (_("invalid memory operand"));
+ return NULL;
+ }
+
+ return l;
+}
+
+/* Parse an MSET instruction. */
+static const char *
+parse_mset (const char *line, const metag_reg **regs, metag_addr *addr,
+ size_t *regs_read)
+{
+ const char *l = line;
+
+ l = parse_mget_mset_addr (l, addr);
+
+ if (l == NULL)
+ {
+ as_bad (_("invalid memory operand"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_gp_regs_list (l, regs, MGET_MSET_MAX_REGS, regs_read);
+
+ if (l == NULL ||
+ *regs_read == 0)
+ {
+ as_bad (_("invalid source register list"));
+ return NULL;
+ }
+
+ return l;
+}
+
+/* Take a register list REGS of size REGS_READ and convert it into an
+ rmask value if possible. Return the rmask value in RMASK and the
+ lowest numbered register in LOWEST_REG. Return TRUE if the conversion
+ was successful. */
+static bfd_boolean
+check_rmask (const metag_reg **regs, size_t regs_read, bfd_boolean is_fpu,
+ bfd_boolean is_64bit, unsigned int *lowest_reg,
+ unsigned int *rmask)
+{
+ unsigned int reg_unit = regs[0]->unit;
+ size_t i;
+
+ for (i = 0; i < regs_read; i++)
+ {
+ if (is_fpu)
+ {
+ if (is_64bit && regs[i]->no % 2)
+ {
+ as_bad (_("register list must be even numbered"));
+ return FALSE;
+ }
+ }
+ else if (regs[i]->unit != reg_unit)
+ {
+ as_bad (_("register list must be from the same unit"));
+ return FALSE;
+ }
+
+ if (regs[i]->no < *lowest_reg)
+ *lowest_reg = regs[i]->no;
+ }
+
+ for (i = 0; i < regs_read; i++)
+ {
+ unsigned int next_bit, next_reg;
+ if (regs[i]->no == *lowest_reg)
+ continue;
+
+ if (is_fpu && is_64bit)
+ next_reg = ((regs[i]->no / 2) - ((*lowest_reg / 2) + 1));
+ else
+ next_reg = (regs[i]->no - (*lowest_reg + 1));
+
+ next_bit = (1 << next_reg);
+
+ if (*rmask & next_bit)
+ {
+ as_bad (_("register list must not contain duplicates"));
+ return FALSE;
+ }
+
+ *rmask |= next_bit;
+ }
+
+ return TRUE;
+}
+
+/* Parse an MGET or MSET instruction. */
+static const char *
+parse_mget_mset (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[MGET_MSET_MAX_REGS];
+ metag_addr addr;
+ bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bfd_boolean is_fpu = (MINOR_OPCODE (template->meta_opcode) & 0x6) == 0x6;
+ bfd_boolean is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) == 0x1;
+ size_t regs_read = 0;
+ unsigned int rmask = 0, reg_unit = 0, lowest_reg = 0xffffffff;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ if (is_get)
+ {
+ l = parse_mget (l, regs, &addr, ®s_read);
+ }
+ else
+ {
+ l = parse_mset (l, regs, &addr, ®s_read);
+ }
+
+ if (l == NULL)
+ return NULL;
+
+ if (!check_rmask (regs, regs_read, is_fpu, is_64bit, &lowest_reg, &rmask))
+ return NULL;
+
+ reg_unit = regs[0]->unit;
+
+ if (is_fpu)
+ {
+ if (reg_unit != UNIT_FX)
+ return NULL;
+
+ reg_unit = 0;
+ }
+ else if (reg_unit == UNIT_FX)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (lowest_reg << 19) |
+ ((reg_unit & SHORT_UNIT_MASK) << 3));
+
+ if (!is_short_unit (addr.base_reg->unit))
+ {
+ as_bad (_("base unit must be one of %s"), SHORT_UNITS);
+ return NULL;
+ }
+
+ insn->bits |= ((addr.base_reg->no << 14) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5));
+
+ insn->bits |= (rmask & RMASK_MASK) << 7;
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a list of registers for MMOV pipeline prime. */
+static const char *
+parse_mmov_prime_list (const char *line, const metag_reg **regs,
+ unsigned int *rmask)
+{
+ const char *l = line;
+ const metag_reg *ra_regs[MMOV_MAX_REGS];
+ size_t regs_read = 0, i;
+ unsigned int mask = 0;
+
+ l = parse_gp_regs_list (l, regs, 1, ®s_read);
+
+ /* First register must be a port. */
+ if (l == NULL || regs[0]->unit != UNIT_RD)
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL)
+ return NULL;
+
+ l = parse_gp_regs_list (l, ra_regs, MMOV_MAX_REGS, ®s_read);
+
+ if (l == NULL)
+ return NULL;
+
+ /* Check remaining registers match the first.
+
+ Note that we also accept RA (0x10) as input for the remaining registers.
+ Whilst this doesn't represent the instruction in any way we're stuck
+ with it because the embedded assembler accepts it. */
+ for (i = 0; i < regs_read; i++)
+ {
+ if (ra_regs[i]->unit != UNIT_RD ||
+ (ra_regs[i]->no != 0x10 && ra_regs[i]->no != regs[0]->no))
+ return NULL;
+
+ mask = (mask << 1) | 0x1;
+ }
+
+ *rmask = mask;
+
+ return l;
+}
+
+/* Parse a MMOV instruction. */
+static const char *
+parse_mmov (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ unsigned int is_fpu = template->insn_type == INSN_FPU;
+ unsigned int is_prime = ((MINOR_OPCODE (template->meta_opcode) & 0x2) &&
+ !is_fpu);
+ unsigned int is_64bit = MINOR_OPCODE (template->meta_opcode) & 0x1;
+ unsigned int rmask = 0;
+
+ if (is_prime)
+ {
+ const metag_reg *reg;
+ metag_addr addr;
+
+ memset (&addr, 0, sizeof(addr));
+
+ l = parse_mmov_prime_list (l, ®, &rmask);
+
+ if (l == NULL)
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL)
+ return NULL;
+
+ l = parse_mget_mset_addr (l, &addr);
+
+ if (l == NULL)
+ {
+ as_bad (_("invalid memory operand"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (reg->no << 19) |
+ (addr.base_reg->no << 14) |
+ ((rmask & RMASK_MASK) << 7) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5));
+ }
+ else
+ {
+ const metag_reg *regs[MMOV_MAX_REGS + 1];
+ unsigned int lowest_reg = 0xffffffff;
+ size_t regs_read = 0;
+
+ l = parse_gp_regs_list (l, regs, MMOV_MAX_REGS + 1, ®s_read);
+
+ if (l == NULL || regs_read == 0)
+ return NULL;
+
+ if (!is_short_unit (regs[0]->unit) &&
+ !(is_fpu && regs[0]->unit == UNIT_FX))
+ {
+ return NULL;
+ }
+
+ if (!(regs[regs_read-1]->unit == UNIT_RD &&
+ regs[regs_read-1]->no == 0))
+ {
+ return NULL;
+ }
+
+ if (!check_rmask (regs, regs_read - 1, is_fpu, is_64bit, &lowest_reg,
+ &rmask))
+ return NULL;
+
+ if (is_fpu)
+ {
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 14) |
+ ((rmask & RMASK_MASK) << 7));
+ }
+ else
+ {
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ ((rmask & RMASK_MASK) << 7) |
+ ((regs[0]->unit & SHORT_UNIT_MASK) << 3));
+ }
+ }
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an immediate constant. */
+static const char *
+parse_imm_constant (const char *line, metag_insn *insn, int *value)
+{
+ const char *l = line;
+ char *save_input_line_pointer;
+ expressionS *exp = &insn->reloc_exp;
+
+ /* Skip #. */
+ if (*l == '#')
+ l++;
+ else
+ return NULL;
+
+ save_input_line_pointer = input_line_pointer;
+ input_line_pointer = (char *) l;
+
+ expression (exp);
+
+ l = input_line_pointer;
+ input_line_pointer = save_input_line_pointer;
+
+ if (exp->X_op == O_constant)
+ {
+ *value = exp->X_add_number;
+
+ return l;
+ }
+ else
+ {
+ return NULL;
+ }
+}
+
+/* Parse an MDRD instruction. */
+static const char *
+parse_mdrd (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ unsigned int rmask = 0;
+ int value = 0, i;
+
+ l = parse_imm_constant (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (value < 1 || value > 8)
+ {
+ as_bad (_("MDRD value must be between 1 and 8"));
+ return NULL;
+ }
+
+ for (i = 1; i < value; i++)
+ {
+ rmask <<= 1;
+ rmask |= 1;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (rmask << 7));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a conditional SET instruction. */
+static const char *
+parse_cond_set (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+ metag_addr addr;
+ unsigned int size = metag_cond_set_size_bytes (template->meta_opcode);
+ unsigned int reg_no;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ l = parse_set (l, regs, &addr, size);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs[0]->unit == UNIT_RD)
+ {
+ if (regs[0]->no != 0)
+ {
+ as_bad (_("set can only use RD port as source"));
+ return NULL;
+ }
+ reg_no = 16;
+ }
+ else
+ reg_no = regs[0]->no;
+
+ if (addr.update)
+ return NULL;
+
+ if (!(addr.immediate &&
+ addr.exp.X_add_number == 0))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (reg_no << 19) |
+ (regs[0]->unit << 10));
+
+ if (!is_short_unit (addr.base_reg->unit))
+ {
+ as_bad (_("base unit must be one of %s"), SHORT_UNITS);
+ return NULL;
+ }
+
+ insn->bits |= ((addr.base_reg->no << 14) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an XFR instruction. */
+static const char *
+parse_xfr (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ metag_addr dest_addr, src_addr;
+ unsigned int size = 4;
+
+ memset(&dest_addr, 0, sizeof(dest_addr));
+ memset(&src_addr, 0, sizeof(src_addr));
+ dest_addr.reloc_type = BFD_RELOC_UNUSED;
+ src_addr.reloc_type = BFD_RELOC_UNUSED;
+
+ l = parse_addr (l, &dest_addr, size);
+
+ if (l == NULL ||
+ dest_addr.immediate == 1)
+ {
+ as_bad (_("invalid destination memory operand"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_addr (l, &src_addr, size);
+
+ if (l == NULL ||
+ src_addr.immediate == 1)
+ {
+ as_bad (_("invalid source memory operand"));
+ return NULL;
+ }
+
+ if (!is_short_unit (dest_addr.base_reg->unit) ||
+ !is_short_unit (src_addr.base_reg->unit))
+ {
+ as_bad (_("address units must be one of %s"), SHORT_UNITS);
+ return NULL;
+ }
+
+ if ((dest_addr.base_reg->unit != dest_addr.offset_reg->unit) ||
+ (src_addr.base_reg->unit != src_addr.offset_reg->unit))
+ {
+ as_bad (_("base and offset must be from the same unit"));
+ return NULL;
+ }
+
+ if (dest_addr.update == 1 &&
+ src_addr.update == 1 &&
+ dest_addr.post_increment != src_addr.post_increment)
+ {
+ as_bad (_("source and destination increment mode must agree"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (src_addr.base_reg->no << 19) |
+ (src_addr.offset_reg->no << 14) |
+ ((src_addr.base_reg->unit & SHORT_UNIT_MASK) << 2));
+
+ insn->bits |= ((dest_addr.base_reg->no << 9) |
+ (dest_addr.offset_reg->no << 4) |
+ ((dest_addr.base_reg->unit & SHORT_UNIT_MASK)));
+
+ if (dest_addr.update == 1)
+ insn->bits |= (1 << 26);
+
+ if (src_addr.update == 1)
+ insn->bits |= (1 << 27);
+
+ if (dest_addr.post_increment == 1 ||
+ src_addr.post_increment == 1)
+ insn->bits |= (1 << 24);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an 8bit immediate value. */
+static const char *
+parse_imm8 (const char *line, metag_insn *insn, int *value)
+{
+ const char *l = line;
+ char *save_input_line_pointer;
+ expressionS *exp = &insn->reloc_exp;
+
+ /* Skip #. */
+ if (*l == '#')
+ l++;
+ else
+ return NULL;
+
+ save_input_line_pointer = input_line_pointer;
+ input_line_pointer = (char *) l;
+
+ expression (exp);
+
+ l = input_line_pointer;
+ input_line_pointer = save_input_line_pointer;
+
+ if (exp->X_op == O_absent || exp->X_op == O_big)
+ {
+ return NULL;
+ }
+ else if (exp->X_op == O_constant)
+ {
+ *value = exp->X_add_number;
+ }
+ else
+ {
+ insn->reloc_type = BFD_RELOC_METAG_REL8;
+ insn->reloc_pcrel = 0;
+ }
+
+ return l;
+}
+
+/* Parse a 16bit immediate value. */
+static const char *
+parse_imm16 (const char *line, metag_insn *insn, int *value)
+{
+ const char *l = line;
+ char *save_input_line_pointer;
+ expressionS *exp = &insn->reloc_exp;
+ bfd_boolean is_hi = FALSE;
+ bfd_boolean is_lo = FALSE;
+
+ /* Skip #. */
+ if (*l == '#')
+ l++;
+ else
+ return NULL;
+
+ if (strncasecmp (l, "HI", 2) == 0)
+ {
+ is_hi = TRUE;
+ l += 2;
+ }
+ else if (strncasecmp (l, "LO", 2) == 0)
+ {
+ is_lo = TRUE;
+ l += 2;
+ }
+
+ save_input_line_pointer = input_line_pointer;
+ input_line_pointer = (char *) l;
+
+ expression (exp);
+
+ l = input_line_pointer;
+ input_line_pointer = save_input_line_pointer;
+
+ if (exp->X_op == O_absent || exp->X_op == O_big)
+ {
+ return NULL;
+ }
+ else if (exp->X_op == O_constant)
+ {
+ if (is_hi)
+ *value = (exp->X_add_number >> 16) & IMM16_MASK;
+ else if (is_lo)
+ *value = exp->X_add_number & IMM16_MASK;
+ else
+ *value = exp->X_add_number;
+ }
+ else
+ {
+ if (exp->X_op == O_PIC_reloc)
+ {
+ exp->X_op = O_symbol;
+
+ if (exp->X_md == BFD_RELOC_METAG_GOTOFF)
+ {
+ if (is_hi)
+ insn->reloc_type = BFD_RELOC_METAG_HI16_GOTOFF;
+ else if (is_lo)
+ insn->reloc_type = BFD_RELOC_METAG_LO16_GOTOFF;
+ else
+ return NULL;
+ }
+ else if (exp->X_md == BFD_RELOC_METAG_PLT)
+ {
+ if (is_hi)
+ insn->reloc_type = BFD_RELOC_METAG_HI16_PLT;
+ else if (is_lo)
+ insn->reloc_type = BFD_RELOC_METAG_LO16_PLT;
+ else
+ return NULL;
+ }
+ else if (exp->X_md == BFD_RELOC_METAG_TLS_LDO)
+ {
+ if (is_hi)
+ insn->reloc_type = BFD_RELOC_METAG_TLS_LDO_HI16;
+ else if (is_lo)
+ insn->reloc_type = BFD_RELOC_METAG_TLS_LDO_LO16;
+ else
+ return NULL;
+ }
+ else if (exp->X_md == BFD_RELOC_METAG_TLS_IENONPIC)
+ {
+ if (is_hi)
+ insn->reloc_type = BFD_RELOC_METAG_TLS_IENONPIC_HI16;
+ else if (is_lo)
+ insn->reloc_type = BFD_RELOC_METAG_TLS_IENONPIC_LO16;
+ else
+ return NULL;
+ }
+ else if (exp->X_md == BFD_RELOC_METAG_TLS_LE)
+ {
+ if (is_hi)
+ insn->reloc_type = BFD_RELOC_METAG_TLS_LE_HI16;
+ else if (is_lo)
+ insn->reloc_type = BFD_RELOC_METAG_TLS_LE_LO16;
+ else
+ return NULL;
+ }
+ else if (exp->X_md == BFD_RELOC_METAG_TLS_GD ||
+ exp->X_md == BFD_RELOC_METAG_TLS_LDM)
+ insn->reloc_type = exp->X_md;
+ }
+ else
+ {
+ if (exp->X_op == O_symbol && exp->X_add_symbol == GOT_symbol)
+ {
+ if (is_hi)
+ insn->reloc_type = BFD_RELOC_METAG_HI16_GOTPC;
+ else if (is_lo)
+ insn->reloc_type = BFD_RELOC_METAG_LO16_GOTPC;
+ else
+ return NULL;
+ }
+ else
+ {
+ if (is_hi)
+ insn->reloc_type = BFD_RELOC_METAG_HIADDR16;
+ else if (is_lo)
+ insn->reloc_type = BFD_RELOC_METAG_LOADDR16;
+ else
+ insn->reloc_type = BFD_RELOC_METAG_REL16;
+ }
+ }
+
+ insn->reloc_pcrel = 0;
+ }
+
+ return l;
+}
+
+/* Parse a MOV to control unit instruction. */
+static const char *
+parse_mov_ct (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[1];
+ unsigned int top = template->meta_opcode & 0x1;
+ unsigned int is_trace = (template->meta_opcode >> 2) & 0x1;
+ unsigned int sign_extend = 0;
+ int value = 0;
+
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (is_trace)
+ {
+ if (regs[0]->unit != UNIT_TT)
+ return NULL;
+ }
+ else
+ {
+ if (regs[0]->unit != UNIT_CT)
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_imm16 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (value < 0)
+ sign_extend = 1;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ ((value & IMM16_MASK) << 3));
+
+ if (sign_extend == 1 && top == 0)
+ insn->bits |= (1 << 1);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a SWAP instruction. */
+static const char *
+parse_swap (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+
+ l = parse_gp_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[1]->no << 19) |
+ (regs[0]->no << 14) |
+ (regs[1]->unit << 10) |
+ (regs[0]->unit << 5));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a JUMP instruction. */
+static const char *
+parse_jump (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[1];
+ int value = 0;
+
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!is_short_unit (regs[0]->unit))
+ {
+ as_bad (_("register unit must be one of %s"), SHORT_UNITS);
+ return FALSE;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_imm16 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[0]->unit & SHORT_UNIT_MASK) |
+ ((value & IMM16_MASK) << 3));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a 19bit immediate value. */
+static const char *
+parse_imm19 (const char *line, metag_insn *insn, int *value)
+{
+ const char *l = line;
+ char *save_input_line_pointer;
+ expressionS *exp = &insn->reloc_exp;
+
+ /* Skip #. */
+ if (*l == '#')
+ l++;
+
+ save_input_line_pointer = input_line_pointer;
+ input_line_pointer = (char *) l;
+
+ expression (exp);
+
+ l = input_line_pointer;
+ input_line_pointer = save_input_line_pointer;
+
+ if (exp->X_op == O_absent || exp->X_op == O_big)
+ {
+ return NULL;
+ }
+ else if (exp->X_op == O_constant)
+ {
+ *value = exp->X_add_number;
+ }
+ else
+ {
+ if (exp->X_op == O_PIC_reloc)
+ {
+ exp->X_op = O_symbol;
+
+ if (exp->X_md == BFD_RELOC_METAG_PLT)
+ insn->reloc_type = BFD_RELOC_METAG_RELBRANCH_PLT;
+ else
+ return NULL;
+ }
+ else
+ insn->reloc_type = BFD_RELOC_METAG_RELBRANCH;
+ insn->reloc_pcrel = 1;
+ }
+
+ return l;
+}
+
+/* Parse a CALLR instruction. */
+static const char *
+parse_callr (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[1];
+ int value = 0;
+
+ l = parse_gp_regs (l, regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!is_short_unit (regs[0]->unit))
+ {
+ as_bad (_("link register unit must be one of %s"), SHORT_UNITS);
+ return NULL;
+ }
+
+ if (regs[0]->no & ~CALLR_REG_MASK)
+ {
+ as_bad (_("link register must be in a low numbered register"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_imm19 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!within_signed_range (value / 4, IMM19_BITS))
+ {
+ as_bad (_("target out of range"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no & CALLR_REG_MASK) |
+ ((regs[0]->unit & SHORT_UNIT_MASK) << 3) |
+ ((value & IMM19_MASK) << 5));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Return the value for the register field if we apply the O2R modifier
+ to operand 2 REG, combined with UNIT_BIT derived from the destination
+ register or source1. Uses address unit O2R if IS_ADDR is set. */
+static int
+lookup_o2r (unsigned int is_addr, unsigned int unit_bit, const metag_reg *reg)
+{
+ if (reg->no & ~O2R_REG_MASK)
+ return -1;
+
+ if (is_addr)
+ {
+ if (unit_bit)
+ {
+ switch (reg->unit)
+ {
+ case UNIT_D1:
+ return reg->no;
+ case UNIT_D0:
+ return (1 << 3) | reg->no;
+ case UNIT_RD:
+ return (2 << 3) | reg->no;
+ case UNIT_A0:
+ return (3 << 3) | reg->no;
+ default:
+ return -1;
+ }
+ }
+ else
+ {
+ switch (reg->unit)
+ {
+ case UNIT_A1:
+ return reg->no;
+ case UNIT_D0:
+ return (1 << 3) | reg->no;
+ case UNIT_RD:
+ return (2 << 3) | reg->no;
+ case UNIT_D1:
+ return (3 << 3) | reg->no;
+ default:
+ return -1;
+ }
+ }
+ }
+ else
+ {
+ if (unit_bit)
+ {
+ switch (reg->unit)
+ {
+ case UNIT_A1:
+ return reg->no;
+ case UNIT_D0:
+ return (1 << 3) | reg->no;
+ case UNIT_RD:
+ return (2 << 3) | reg->no;
+ case UNIT_A0:
+ return (3 << 3) | reg->no;
+ default:
+ return -1;
+ }
+ }
+ else
+ {
+ switch (reg->unit)
+ {
+ case UNIT_A1:
+ return reg->no;
+ case UNIT_D1:
+ return (1 << 3) | reg->no;
+ case UNIT_RD:
+ return (2 << 3) | reg->no;
+ case UNIT_A0:
+ return (3 << 3) | reg->no;
+ default:
+ return -1;
+ }
+ }
+ }
+}
+
+/* Parse GP ALU instruction. */
+static const char *
+parse_alu (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *dest_regs[1];
+ const metag_reg *src_regs[2];
+ int value = 0;
+ unsigned int o1z = 0;
+ unsigned int imm = (template->meta_opcode >> 25) & 0x1;
+ unsigned int cond = (template->meta_opcode >> 26) & 0x1;
+ unsigned int ca = (template->meta_opcode >> 5) & 0x1;
+ unsigned int top = template->meta_opcode & 0x1;
+ unsigned int sign_extend = 0;
+ unsigned int is_addr_op = MAJOR_OPCODE (template->meta_opcode) == OPC_ADDR;
+ unsigned int is_mul = MAJOR_OPCODE (template->meta_opcode) == OPC_MUL;
+ unsigned int unit_bit = 0;
+ bfd_boolean is_quickrot = template->arg_type & GP_ARGS_QR;
+
+ l = parse_gp_regs (l, dest_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ if (is_addr_op)
+ {
+ if (dest_regs[0]->unit == UNIT_A0)
+ unit_bit = 0;
+ else if (dest_regs[0]->unit == UNIT_A1)
+ unit_bit = 1;
+ }
+ else
+ {
+ if (dest_regs[0]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (dest_regs[0]->unit == UNIT_D1)
+ unit_bit = 1;
+ }
+
+ if ((MAJOR_OPCODE (template->meta_opcode) == OPC_ADDR ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_ADD ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_SUB) &&
+ ((template->meta_opcode >> 2) & 0x1))
+ o1z = 1;
+
+ if (imm)
+ {
+ if (!cond)
+ {
+ if (is_addr_op)
+ {
+ if (dest_regs[0]->unit == UNIT_A0)
+ unit_bit = 0;
+ else if (dest_regs[0]->unit == UNIT_A1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+ else
+ {
+ if (dest_regs[0]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (dest_regs[0]->unit == UNIT_D1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+ }
+
+ if (cond)
+ {
+ l = parse_gp_regs (l, src_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ if (is_addr_op)
+ {
+ if (src_regs[0]->unit == UNIT_A0)
+ unit_bit = 0;
+ else if (src_regs[0]->unit == UNIT_A1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+ else
+ {
+ if (src_regs[0]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (src_regs[0]->unit == UNIT_D1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+
+ if (src_regs[0]->unit != dest_regs[0]->unit && !ca)
+ return NULL;
+
+ l = parse_imm8 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!within_unsigned_range (value, IMM8_BITS))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ (src_regs[0]->no << 14) |
+ ((value & IMM8_MASK) << 6));
+
+ if (ca)
+ {
+ if (is_addr_op)
+ {
+ if (src_regs[0]->unit == UNIT_A0)
+ unit_bit = 0;
+ else if (src_regs[0]->unit == UNIT_A1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+ else
+ {
+ if (src_regs[0]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (src_regs[0]->unit == UNIT_D1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+
+ insn->bits |= dest_regs[0]->unit << 1;
+ }
+ }
+ else if (o1z)
+ {
+ l = parse_imm16 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (value < 0)
+ {
+ if (!within_signed_range (value, IMM16_BITS))
+ {
+ as_bad (_("immediate out of range"));
+ return NULL;
+ }
+ sign_extend = 1;
+ }
+ else
+ {
+ if (!within_unsigned_range (value, IMM16_BITS))
+ {
+ as_bad (_("immediate out of range"));
+ return NULL;
+ }
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ ((value & IMM16_MASK) << 3));
+ }
+ else
+ {
+ l = parse_gp_regs (l, src_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!(src_regs[0]->unit == dest_regs[0]->unit))
+ return NULL;
+
+ /* CPC is valid for address ops. */
+ if (src_regs[0]->no != dest_regs[0]->no &&
+ !(is_addr_op && src_regs[0]->no == 0x10))
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_imm16 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (value < 0)
+ {
+ if (!within_signed_range (value, IMM16_BITS))
+ {
+ as_bad (_("immediate out of range"));
+ return NULL;
+ }
+ sign_extend = 1;
+ }
+ else
+ {
+ if (!within_unsigned_range (value, IMM16_BITS))
+ {
+ as_bad (_("immediate out of range"));
+ return NULL;
+ }
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ (src_regs[0]->no << 19) |
+ ((value & IMM16_MASK) << 3));
+ }
+ }
+ else
+ {
+ unsigned int o2r = 0;
+ int rs2;
+
+ if (cond || !o1z)
+ l = parse_gp_regs (l, src_regs, 2);
+ else
+ l = parse_gp_regs (l, src_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (cond || !o1z)
+ {
+ if (is_addr_op)
+ {
+ if (src_regs[0]->unit == UNIT_A0)
+ unit_bit = 0;
+ else if (src_regs[0]->unit == UNIT_A1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+ else
+ {
+ if (src_regs[0]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (src_regs[0]->unit == UNIT_D1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+ }
+ else
+ {
+ if (is_addr_op)
+ {
+ if (dest_regs[0]->unit == UNIT_A0)
+ unit_bit = 0;
+ else if (dest_regs[0]->unit == UNIT_A1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+ else
+ {
+ if (dest_regs[0]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (dest_regs[0]->unit == UNIT_D1)
+ unit_bit = 1;
+ else
+ return NULL;
+ }
+ }
+
+ if (cond)
+ {
+ if (src_regs[0]->unit != src_regs[1]->unit)
+ {
+ rs2 = lookup_o2r (is_addr_op, unit_bit, src_regs[1]);
+
+ if (rs2 < 0)
+ return NULL;
+
+ o2r = 1;
+ }
+ else
+ {
+ rs2 = src_regs[1]->no;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ (src_regs[0]->no << 14) |
+ (rs2 << 9));
+
+ if (is_mul)
+ {
+ if (dest_regs[0]->unit != src_regs[0]->unit && is_mul)
+ {
+ if (ca)
+ {
+ insn->bits |= dest_regs[0]->unit << 1;
+ }
+ else
+ return NULL;
+ }
+ }
+ else
+ insn->bits |= dest_regs[0]->unit << 5;
+ }
+ else if (o1z)
+ {
+ if (dest_regs[0]->unit != src_regs[0]->unit)
+ {
+ rs2 = lookup_o2r (is_addr_op, unit_bit, src_regs[0]);
+
+ if (rs2 < 0)
+ return NULL;
+
+ o2r = 1;
+ }
+ else
+ {
+ rs2 = src_regs[0]->no;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ (rs2 << 9));
+ }
+ else
+ {
+ if (dest_regs[0]->unit != src_regs[0]->unit)
+ return NULL;
+
+ if (dest_regs[0]->unit != src_regs[1]->unit)
+ {
+ rs2 = lookup_o2r (is_addr_op, unit_bit, src_regs[1]);
+
+ if (rs2 < 0)
+ return NULL;
+
+ o2r = 1;
+ }
+ else
+ {
+ rs2 = src_regs[1]->no;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ (src_regs[0]->no << 14) |
+ (rs2 << 9));
+ }
+
+ if (o2r)
+ insn->bits |= 1;
+ }
+
+ if (is_quickrot)
+ {
+ const metag_reg *qr_regs[1];
+ bfd_boolean limit_regs = imm && cond;
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_gp_regs (l, qr_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!((unit_bit == 0 && qr_regs[0]->unit != UNIT_A0) ||
+ !(unit_bit == 1 && qr_regs[0]->unit != UNIT_A1)))
+ {
+ as_bad (_("invalid quickrot unit specified"));
+ return NULL;
+ }
+
+ switch (qr_regs[0]->no)
+ {
+ case 2:
+ break;
+ case 3:
+ if (!limit_regs)
+ {
+ insn->bits |= (1 << 7);
+ break;
+ }
+ default:
+ as_bad (_("invalid quickrot register specified"));
+ return NULL;
+ }
+ }
+
+ if (sign_extend == 1 && top == 0)
+ insn->bits |= (1 << 1);
+
+ insn->bits |= unit_bit << 24;
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a B instruction. */
+static const char *
+parse_branch (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ int value = 0;
+
+ l = parse_imm19 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!within_signed_range (value / 4, IMM19_BITS))
+ {
+ as_bad (_("target out of range"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ ((value & IMM19_MASK) << 5));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a KICK instruction. */
+static const char *
+parse_kick (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+
+ l = parse_gp_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs[1]->unit != UNIT_TR)
+ {
+ as_bad (_("source register must be in the trigger unit"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (regs[1]->no << 19) |
+ (regs[0]->no << 14) |
+ (regs[0]->unit << 5));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a SWITCH instruction. */
+static const char *
+parse_switch (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ int value = 0;
+
+ l = parse_imm_constant (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!within_unsigned_range (value, IMM24_BITS))
+ {
+ as_bad (_("target out of range"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (value & IMM24_MASK));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a shift instruction. */
+static const char *
+parse_shift (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+ const metag_reg *src2_regs[1];
+ int value = 0;
+ unsigned int cond = (template->meta_opcode >> 26) & 0x1;
+ unsigned int ca = (template->meta_opcode >> 5) & 0x1;
+ unsigned int unit_bit = 0;
+
+ l = parse_gp_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ if (regs[1]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (regs[1]->unit == UNIT_D1)
+ unit_bit = 1;
+ else
+ return NULL;
+
+ if (regs[0]->unit != regs[1]->unit && !(cond && ca))
+ return NULL;
+
+ if (*l == '#')
+ {
+ l = parse_imm_constant (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!within_unsigned_range (value, IMM5_BITS))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (1 << 25) |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14) |
+ ((value & IMM5_MASK) << 9));
+ }
+ else
+ {
+ l = parse_gp_regs (l, src2_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14) |
+ (src2_regs[0]->no << 9));
+
+ if (src2_regs[0]->unit != regs[1]->unit)
+ {
+ as_bad(_("Source registers must be in the same unit"));
+ return NULL;
+ }
+ }
+
+ if (regs[0]->unit != regs[1]->unit)
+ {
+ if (cond && ca)
+ {
+ if (regs[1]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (regs[1]->unit == UNIT_D1)
+ unit_bit = 1;
+ else
+ return NULL;
+
+ insn->bits |= ((1 << 5) |
+ (regs[0]->unit << 1));
+ }
+ else
+ return NULL;
+ }
+
+ insn->bits |= unit_bit << 24;
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a MIN or MAX instruction. */
+static const char *
+parse_min_max (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[3];
+
+ l = parse_gp_regs (l, regs, 3);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!(regs[0]->unit == UNIT_D0 ||
+ regs[0]->unit == UNIT_D1))
+ return NULL;
+
+ if (!(regs[0]->unit == regs[1]->unit &&
+ regs[1]->unit == regs[2]->unit))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14) |
+ (regs[2]->no << 9));
+
+ if (regs[0]->unit == UNIT_D1)
+ insn->bits |= (1 << 24);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a bit operation instruction. */
+static const char *
+parse_bitop (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+ unsigned int swap_inst = MAJOR_OPCODE (template->meta_opcode) == OPC_MISC;
+ unsigned int is_bexl = 0;
+
+ if (swap_inst &&
+ ((template->meta_opcode >> 1) & 0xb) == 0xa)
+ is_bexl = 1;
+
+ l = parse_gp_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!(regs[0]->unit == UNIT_D0 ||
+ regs[0]->unit == UNIT_D1))
+ return NULL;
+
+ if (is_bexl)
+ {
+ if (regs[0]->unit == UNIT_D0 &&
+ regs[1]->unit != UNIT_D1)
+ return NULL;
+ else if (regs[0]->unit == UNIT_D1 &&
+ regs[1]->unit != UNIT_D0)
+ return NULL;
+ }
+ else if (!(regs[0]->unit == regs[1]->unit))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14));
+
+ if (swap_inst)
+ {
+ if (regs[1]->unit == UNIT_D1)
+ insn->bits |= 1;
+ }
+ else
+ {
+ if (regs[1]->unit == UNIT_D1)
+ insn->bits |= (1 << 24);
+ }
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a CMP or TST instruction. */
+static const char *
+parse_cmp (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *dest_regs[1];
+ const metag_reg *src_regs[1];
+ int value = 0;
+ unsigned int imm = (template->meta_opcode >> 25) & 0x1;
+ unsigned int cond = (template->meta_opcode >> 26) & 0x1;
+ unsigned int top = template->meta_opcode & 0x1;
+ unsigned int sign_extend = 0;
+ unsigned int unit_bit = 0;
+
+ l = parse_gp_regs (l, dest_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ if (dest_regs[0]->unit == UNIT_D0)
+ unit_bit = 0;
+ else if (dest_regs[0]->unit == UNIT_D1)
+ unit_bit = 1;
+ else
+ return NULL;
+
+ if (imm)
+ {
+ if (cond)
+ {
+ l = parse_imm_constant (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!within_unsigned_range (value, IMM8_BITS))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 14) |
+ ((value & IMM8_MASK) << 6));
+
+ }
+ else
+ {
+ l = parse_imm16 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ if (value < 0)
+ {
+ if (!within_signed_range (value, IMM16_BITS))
+ {
+ as_bad (_("immediate out of range"));
+ return NULL;
+ }
+ sign_extend = 1;
+ }
+ else
+ {
+ if (!within_unsigned_range (value, IMM16_BITS))
+ {
+ as_bad (_("immediate out of range"));
+ return NULL;
+ }
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ ((value & IMM16_MASK) << 3));
+ }
+ }
+ else
+ {
+ unsigned int o2r = 0;
+ int rs2;
+
+ l = parse_gp_regs (l, src_regs, 1);
+
+ if (l == NULL)
+ return NULL;
+
+ if (dest_regs[0]->unit != src_regs[0]->unit)
+ {
+ rs2 = lookup_o2r (0, unit_bit, src_regs[0]);
+
+ if (rs2 < 0)
+ return NULL;
+
+ o2r = 1;
+ }
+ else
+ {
+ rs2 = src_regs[0]->no;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 14) |
+ (rs2 << 9));
+
+ if (o2r)
+ insn->bits |= 1;
+ }
+
+ if (sign_extend == 1 && top == 0)
+ insn->bits |= (1 << 1);
+
+ insn->bits |= unit_bit << 24;
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a CACHEW instruction. */
+static const char *
+parse_cachew (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *src_regs[2];
+ unsigned int size = ((template->meta_opcode >> 1) & 0x1) ? 8 : 4;
+ metag_addr addr;
+ int offset;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ l = parse_addr (l, &addr, size);
+
+ if (l == NULL ||
+ !is_short_unit (addr.base_reg->unit) ||
+ addr.update ||
+ !addr.immediate)
+ {
+ as_bad (_("invalid memory operand"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ if (size == 4)
+ l = parse_gp_regs (l, src_regs, 1);
+ else
+ l = parse_pair_gp_regs (l, src_regs);
+
+ if (l == NULL ||
+ !is_short_unit (src_regs[0]->unit))
+ {
+ as_bad (_("invalid source register"));
+ return NULL;
+ }
+
+ offset = addr.exp.X_add_number;
+
+ if (addr.negate)
+ offset = -offset;
+
+ offset = offset / 64;
+
+ if (!within_signed_range (offset, GET_SET_IMM_BITS))
+ {
+ as_bad (_("offset value out of range"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (src_regs[0]->no << 19) |
+ (addr.base_reg->no << 14) |
+ ((offset & GET_SET_IMM_MASK) << 8) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5) |
+ ((src_regs[0]->unit & SHORT_UNIT_MASK) << 3));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a CACHEW instruction. */
+static const char *
+parse_cacher (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *dest_regs[2];
+ unsigned int size = ((template->meta_opcode >> 1) & 0x1) ? 8 : 4;
+ metag_addr addr;
+ int offset;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ if (size == 4)
+ l = parse_gp_regs (l, dest_regs, 1);
+ else
+ l = parse_pair_gp_regs (l, dest_regs);
+
+ if (l == NULL ||
+ !is_short_unit (dest_regs[0]->unit))
+ {
+ as_bad (_("invalid destination register"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_addr (l, &addr, size);
+
+ if (l == NULL ||
+ !is_short_unit (addr.base_reg->unit) ||
+ addr.update ||
+ !addr.immediate)
+ {
+ as_bad (_("invalid memory operand"));
+ return NULL;
+ }
+
+ offset = addr.exp.X_add_number;
+
+ if (addr.negate)
+ offset = -offset;
+
+ offset = offset / (int)size;
+
+ if (!within_signed_range (offset, GET_SET_IMM_BITS))
+ {
+ as_bad (_("offset value out of range"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ (addr.base_reg->no << 14) |
+ ((offset & GET_SET_IMM_MASK) << 8) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5) |
+ ((dest_regs[0]->unit & SHORT_UNIT_MASK) << 3));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an ICACHE instruction. */
+static const char *
+parse_icache (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ int offset;
+ int pfcount;
+
+ l = parse_imm_constant (l, insn, &offset);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!within_signed_range (offset, IMM15_BITS))
+ return NULL;
+
+ l = skip_comma (l);
+
+ l = parse_imm_constant (l, insn, &pfcount);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!within_unsigned_range (pfcount, IMM4_BITS))
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ ((offset & IMM15_MASK) << 9) |
+ ((pfcount & IMM4_MASK) << 1));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a LNKGET instruction. */
+static const char *
+parse_lnkget (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *dest_regs[2];
+ unsigned int size = metag_get_set_ext_size_bytes (template->meta_opcode);
+ metag_addr addr;
+ int offset;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ if (size == 8)
+ l = parse_pair_gp_regs (l, dest_regs);
+ else
+ l = parse_gp_regs (l, dest_regs, 1);
+
+ if (l == NULL ||
+ !is_short_unit (dest_regs[0]->unit))
+ {
+ as_bad (_("invalid destination register"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_addr (l, &addr, size);
+
+ if (l == NULL ||
+ !is_short_unit (addr.base_reg->unit) ||
+ addr.update ||
+ !addr.immediate)
+ {
+ as_bad (_("invalid memory operand"));
+ return NULL;
+ }
+
+ offset = addr.exp.X_add_number;
+
+ if (addr.negate)
+ offset = -offset;
+
+ offset = offset / size;
+
+ if (!within_signed_range (offset, GET_SET_IMM_BITS))
+ {
+ as_bad (_("offset value out of range"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (dest_regs[0]->no << 19) |
+ (addr.base_reg->no << 14) |
+ ((offset & GET_SET_IMM_MASK) << 8) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5) |
+ ((dest_regs[0]->unit & SHORT_UNIT_MASK) << 3));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU MOV instruction. */
+static const char *
+parse_fmov (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+
+ l = parse_fpu_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14));
+
+ if (insn->fpu_width == FPU_WIDTH_DOUBLE)
+ insn->bits |= (1 << 5);
+ else if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 6);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU MMOV instruction. */
+static const char *
+parse_fmmov (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ bfd_boolean to_fpu = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bfd_boolean is_mmovl = MINOR_OPCODE (template->meta_opcode) & 0x1;
+ size_t regs_read = 0;
+ const metag_reg *regs[16];
+ unsigned int lowest_data_reg = 0xffffffff;
+ unsigned int lowest_fpu_reg = 0xffffffff;
+ unsigned int rmask = 0, data_unit;
+ size_t i;
+ int last_reg = -1;
+
+ if (insn->fpu_width != FPU_WIDTH_SINGLE)
+ return NULL;
+
+ l = parse_gp_regs_list (l, regs, 16, ®s_read);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs_read % 2)
+ return NULL;
+
+ if (to_fpu)
+ {
+ for (i = 0; i < regs_read / 2; i++)
+ {
+ if (regs[i]->unit != UNIT_FX)
+ return NULL;
+
+ if (last_reg == -1)
+ {
+ last_reg = regs[i]->no;
+ lowest_fpu_reg = last_reg;
+ }
+ else
+ {
+ if (is_mmovl)
+ {
+ if (regs[i]->no != (unsigned int)(last_reg + 2))
+ return NULL;
+ }
+ else if (regs[i]->no != (unsigned int)(last_reg + 1))
+ return NULL;
+
+ last_reg = regs[i]->no;
+ }
+ }
+
+ if (regs[i]->unit == UNIT_D0)
+ data_unit = 0;
+ else if (regs[i]->unit == UNIT_D1)
+ data_unit = 1;
+ else
+ return NULL;
+
+ if (!check_rmask (®s[i], regs_read / 2, TRUE, FALSE, &lowest_data_reg,
+ &rmask))
+ return NULL;
+ }
+ else
+ {
+ if (regs[0]->unit == UNIT_D0)
+ data_unit = 0;
+ else if (regs[0]->unit == UNIT_D1)
+ data_unit = 1;
+ else
+ return NULL;
+
+ if (!check_rmask (regs, regs_read / 2, TRUE, FALSE, &lowest_data_reg,
+ &rmask))
+ return NULL;
+
+ for (i = regs_read / 2; i < regs_read; i++)
+ {
+ if (regs[i]->unit != UNIT_FX)
+ return NULL;
+
+ if (last_reg == -1)
+ {
+ last_reg = regs[i]->no;
+ lowest_fpu_reg = last_reg;
+ }
+ else
+ {
+ if (is_mmovl)
+ {
+ if (regs[i]->no != (unsigned int)(last_reg + 2))
+ return NULL;
+ }
+ else if (regs[i]->no != (unsigned int)(last_reg + 1))
+ return NULL;
+
+ last_reg = regs[i]->no;
+ }
+ }
+ }
+
+ insn->bits = (template->meta_opcode |
+ ((lowest_data_reg & REG_MASK) << 19) |
+ ((lowest_fpu_reg & REG_MASK) << 14) |
+ ((rmask & RMASK_MASK) << 7) |
+ data_unit);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU data unit MOV instruction. */
+static const char *
+parse_fmov_data (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ unsigned int to_fpu = ((template->meta_opcode >> 7) & 0x1);
+ const metag_reg *regs[2];
+ unsigned int base_unit;
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ return NULL;
+
+ l = parse_gp_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ if (to_fpu)
+ {
+ if (regs[0]->unit != UNIT_FX)
+ return NULL;
+
+ if (regs[1]->unit == UNIT_D0)
+ base_unit = 0;
+ else if (regs[1]->unit == UNIT_D1)
+ base_unit = 1;
+ else
+ return NULL;
+ }
+ else
+ {
+ if (regs[0]->unit == UNIT_D0)
+ base_unit = 0;
+ else if (regs[0]->unit == UNIT_D1)
+ base_unit = 1;
+ else
+ return NULL;
+
+ if (regs[1]->unit != UNIT_FX)
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (base_unit << 24) |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 9));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU immediate MOV instruction. */
+static const char *
+parse_fmov_i (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[1];
+ int value = 0;
+
+ l = parse_fpu_regs (l, regs, 1);
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_imm16 (l, insn, &value);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ ((value & IMM16_MASK) << 3));
+
+ if (insn->fpu_width == FPU_WIDTH_DOUBLE)
+ insn->bits |= (1 << 1);
+ else if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 2);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU PACK instruction. */
+static const char *
+parse_fpack (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[3];
+
+ l = parse_fpu_regs (l, regs, 3);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs[0]->no % 2)
+ {
+ as_bad (_("destination register should be even numbered"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14) |
+ (regs[2]->no << 9));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU SWAP instruction. */
+static const char *
+parse_fswap (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+
+ if (insn->fpu_width != FPU_WIDTH_PAIR)
+ return NULL;
+
+ l = parse_fpu_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs[0]->no % 2)
+ return NULL;
+
+ if (regs[1]->no % 2)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU CMP instruction. */
+static const char *
+parse_fcmp (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line, *l2;
+ const metag_reg *regs1[1];
+ const metag_reg *regs2[1];
+
+ l = parse_fpu_regs (l, regs1, 1);
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l2 = parse_fpu_regs (l, regs2, 1);
+
+ if (l2 != NULL)
+ {
+ insn->bits = (regs2[0]->no << 9);
+ }
+ else
+ {
+ int constant = 0;
+ l2 = parse_imm_constant (l, insn, &constant);
+ if (!l2 || constant != 0)
+ {
+ as_bad (_("comparison must be with register or #0"));
+ return NULL;
+ }
+ insn->bits = (1 << 8);
+ }
+
+ insn->bits |= (template->meta_opcode |
+ (regs1[0]->no << 14));
+
+ if (insn->fpu_action_flags & FPU_ACTION_ABS)
+ insn->bits |= (1 << 19);
+
+ if (insn->fpu_action_flags & FPU_ACTION_QUIET)
+ insn->bits |= (1 << 7);
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 6);
+ else if (insn->fpu_width == FPU_WIDTH_DOUBLE)
+ insn->bits |= (1 << 5);
+
+ insn->len = 4;
+ return l2;
+}
+
+/* Parse an FPU MIN or MAX instruction. */
+static const char *
+parse_fminmax (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[3];
+
+ l = parse_fpu_regs (l, regs, 3);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14) |
+ (regs[2]->no << 9));
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 6);
+ else if (insn->fpu_width == FPU_WIDTH_DOUBLE)
+ insn->bits |= (1 << 5);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU data conversion instruction. */
+static const char *
+parse_fconv (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ {
+ if (strncasecmp (template->name, "FTOH", 4) &&
+ strncasecmp (template->name, "HTOF", 4) &&
+ strncasecmp (template->name, "FTOI", 4) &&
+ strncasecmp (template->name, "ITOF", 4))
+ {
+ as_bad (_("instruction cannot operate on pair values"));
+ return NULL;
+ }
+ }
+
+ if (insn->fpu_action_flags & FPU_ACTION_ZERO)
+ {
+ if (strncasecmp (template->name, "FTOI", 4) &&
+ strncasecmp (template->name, "DTOI", 4) &&
+ strncasecmp (template->name, "DTOL", 4))
+ {
+ as_bad (_("zero flag is not valid for this instruction"));
+ return NULL;
+ }
+ }
+
+ l = parse_fpu_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!strncasecmp (template->name, "DTOL", 4) ||
+ !strncasecmp (template->name, "LTOD", 4))
+ {
+ if (regs[0]->no % 2)
+ {
+ as_bad (_("destination register should be even numbered"));
+ return NULL;
+ }
+
+ if (regs[1]->no % 2)
+ {
+ as_bad (_("source register should be even numbered"));
+ return NULL;
+ }
+ }
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14));
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 6);
+
+ if (insn->fpu_action_flags & FPU_ACTION_ZERO)
+ insn->bits |= (1 << 12);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU extended data conversion instruction. */
+static const char *
+parse_fconvx (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+ int fraction_bits = 0;
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ {
+ if (strncasecmp (template->name, "FTOX", 4) &&
+ strncasecmp (template->name, "XTOF", 4))
+ {
+ as_bad (_("instruction cannot operate on pair values"));
+ return NULL;
+ }
+ }
+
+ l = parse_fpu_regs (l, regs, 2);
+
+ l = skip_comma (l);
+
+ if (l == NULL ||
+ *l == END_OF_INSN)
+ return NULL;
+
+ l = parse_imm_constant (l, insn, &fraction_bits);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14));
+
+ if (strncasecmp (template->name, "DTOXL", 5) &&
+ strncasecmp (template->name, "XLTOD", 5))
+ {
+ if (!within_unsigned_range (fraction_bits, IMM5_BITS))
+ {
+ as_bad (_("fraction bits value out of range"));
+ return NULL;
+ }
+ insn->bits |= ((fraction_bits & IMM5_MASK) << 9);
+ }
+ else
+ {
+ if (!within_unsigned_range (fraction_bits, IMM6_BITS))
+ {
+ as_bad (_("fraction bits value out of range"));
+ return NULL;
+ }
+ insn->bits |= ((fraction_bits & IMM6_MASK) << 8);
+ }
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 6);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU basic arithmetic instruction. */
+static const char *
+parse_fbarith (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[3];
+
+ l = parse_fpu_regs (l, regs, 3);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14) |
+ (regs[2]->no << 9));
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 6);
+ else if (insn->fpu_width == FPU_WIDTH_DOUBLE)
+ insn->bits |= (1 << 5);
+
+ if (insn->fpu_action_flags & FPU_ACTION_INV)
+ insn->bits |= (1 << 7);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse a floating point accumulator name. */
+static const char *
+parse_acf (const char *line, int *part)
+{
+ const char *l = line;
+ size_t i;
+
+ for (i = 0; i < sizeof(metag_acftab)/sizeof(metag_acftab[0]); i++)
+ {
+ const metag_acf *acf = &metag_acftab[i];
+ size_t name_len = strlen (acf->name);
+
+ if (strncasecmp (l, acf->name, name_len) == 0)
+ {
+ l += name_len;
+ *part = acf->part;
+ return l;
+ }
+ }
+ return NULL;
+}
+
+/* Parse an FPU extended arithmetic instruction. */
+static const char *
+parse_fearith (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[3];
+ bfd_boolean is_muz = (MINOR_OPCODE (template->meta_opcode) == 0x6 &&
+ ((template->meta_opcode >> 4) & 0x1));
+ unsigned int is_o3o = template->meta_opcode & 0x1;
+ unsigned int is_mac = 0;
+ unsigned int is_maw = 0;
+
+ if (!strncasecmp (template->name, "MAW", 3))
+ is_maw = 1;
+
+ if (!strncasecmp (template->name, "MAC", 3))
+ {
+ int part;
+ l = parse_acf (l, &part);
+
+ if (l == NULL || part != 0)
+ return NULL;
+
+ l = skip_comma (l);
+
+ l = parse_fpu_regs (l, ®s[1], 2);
+
+ is_mac = 1;
+ }
+ else
+ {
+ if (is_o3o && is_maw)
+ l = parse_fpu_regs (l, regs, 2);
+ else
+ l = parse_fpu_regs (l, regs, 3);
+ }
+
+ if (l == NULL)
+ return NULL;
+
+ if (is_o3o && is_maw)
+ insn->bits = (template->meta_opcode |
+ (regs[1]->no << 9));
+ else
+ insn->bits = (template->meta_opcode |
+ (regs[1]->no << 14));
+
+ if (!(is_o3o && is_maw))
+ insn->bits |= (regs[2]->no << 9);
+
+ if (is_o3o && is_maw)
+ insn->bits |= (regs[0]->no << 14);
+ else if (!is_mac)
+ insn->bits |= (regs[0]->no << 19);
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 6);
+ else if (insn->fpu_width == FPU_WIDTH_DOUBLE)
+ insn->bits |= (1 << 5);
+
+ if (!is_mac && !is_maw)
+ if (insn->fpu_action_flags & FPU_ACTION_INV)
+ insn->bits |= (1 << 7);
+
+ if (is_muz)
+ if (insn->fpu_action_flags & FPU_ACTION_QUIET)
+ insn->bits |= (1 << 1);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU RCP or RSQ instruction. */
+static const char *
+parse_frec (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[2];
+
+ l = parse_fpu_regs (l, regs, 2);
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14));
+
+ if (insn->fpu_width == FPU_WIDTH_PAIR)
+ insn->bits |= (1 << 6);
+ else if (insn->fpu_width == FPU_WIDTH_DOUBLE)
+ insn->bits |= (1 << 5);
+
+ if (insn->fpu_action_flags & FPU_ACTION_ZERO)
+ insn->bits |= (1 << 10);
+ else if (insn->fpu_action_flags & FPU_ACTION_QUIET)
+ insn->bits |= (1 << 9);
+
+ if (insn->fpu_action_flags & FPU_ACTION_INV)
+ insn->bits |= (1 << 7);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU vector arithmetic instruction. */
+static const char *
+parse_fsimd (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[3];
+
+ if (insn->fpu_width != FPU_WIDTH_PAIR)
+ {
+ as_bad (_("simd instructions operate on pair values (L prefix)"));
+ return NULL;
+ }
+
+ l = parse_fpu_regs (l, regs, 3);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs[0]->no % 2)
+ {
+ as_bad (_("destination register should be even numbered"));
+ return NULL;
+ }
+
+ if ((regs[1]->no % 2) ||
+ (regs[2]->no % 2))
+ {
+ as_bad (_("source registers should be even numbered"));
+ return NULL;
+ }
+
+ insn->bits = (template->meta_opcode |
+ (regs[0]->no << 19) |
+ (regs[1]->no << 14) |
+ (regs[2]->no << 9));
+
+ if (insn->fpu_action_flags & FPU_ACTION_INV)
+ insn->bits |= (1 << 7);
+
+ insn->len = 4;
+ return l;
+}
+
+/* Parse an FPU accumulator GET or SET instruction. */
+static const char *
+parse_fget_set_acf (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ int part;
+ metag_addr addr;
+ bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ if (is_get)
+ {
+ l = parse_acf (l, &part);
+
+ l = skip_comma (l);
+
+ if (l == NULL)
+ return NULL;
+
+ l = parse_mget_mset_addr (l, &addr);
+ }
+ else
+ {
+ l = parse_mget_mset_addr (l, &addr);
+
+ l = skip_comma (l);
+
+ if (l == NULL)
+ return NULL;
+
+ l = parse_acf (l, &part);
+ }
+
+ if (l == NULL)
+ return NULL;
+
+ insn->bits = (template->meta_opcode |
+ (part << 19));
+
+ if (!is_short_unit (addr.base_reg->unit))
+ {
+ as_bad (_("base unit must be one of %s"), SHORT_UNITS);
+ return NULL;
+ }
+
+ insn->bits |= ((addr.base_reg->no << 14) |
+ ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5));
+
+ insn->len = 4;
+ return l;
+}
+
+/* Copy the name of the next register in LINE to REG_BUF. */
+static size_t
+strip_reg_name(const char *line, char *reg_buf)
+{
+ const char *l = line;
+ size_t len = 0;
+
+ while (is_register_char (*l))
+ {
+ reg_buf[len] = *l;
+ l++;
+ len++;
+ if (!(len < MAX_REG_LEN))
+ return 0;
+ }
+
+ if (len)
+ reg_buf[len] = '\0';
+
+ return len;
+}
+
+/* Parse a DSP register from LINE into REG using only the registers
+ from DSP_REGTAB. Return the next character or NULL. */
+static const char *
+__parse_dsp_reg (const char *line, const metag_reg **reg, htab_t dsp_regtab)
+{
+ const char *l = line;
+ char name[MAX_REG_LEN];
+ size_t len = 0;
+ metag_reg entry;
+ const metag_reg *_reg;
+
+ /* We don't entirely strip the register name because we might
+ actually want to match whole string in the register table,
+ e.g. "D0AW.1++" not just "D0AW.1". The string length of the table
+ entry limits our comaprison to a reasonable bound anyway. */
+ while (is_register_char (*l) || *l == PLUS)
+ {
+ name[len] = *l;
+ l++;
+ len++;
+ if (!(len < MAX_REG_LEN))
+ return NULL;
+ }
+
+ if (!len)
+ return NULL;
+
+ name[len] = '\0';
+ entry.name = name;
+
+ _reg = (const metag_reg *) htab_find (dsp_regtab, &entry);
+ if (!_reg)
+ return NULL;
+
+ *reg = _reg;
+
+ return l;
+}
+
+/* Parse a DSP register and setup "reg" with a metag_reg whose "no"
+ member is suitable for encoding into a DSP insn register field. */
+static const char *
+parse_dsp_insn_reg (const char *line, const metag_reg **reg)
+{
+ return __parse_dsp_reg (line, reg, dsp_reg_htab);
+}
+
+/* Parse a DSP register and setup "reg" with a metag_reg whose "no"
+ member is suitable for encoding into a DSP template definition insn
+ register field.
+
+ There is a separate table for whether we're doing a load or a store
+ definition. "load" specifies which table to look at. */
+static const char *
+parse_dsp_template_reg (const char *line, const metag_reg **reg,
+ bfd_boolean load)
+{
+ return __parse_dsp_reg (line, reg, dsp_tmpl_reg_htab[load]);
+}
+
+/* Parse a single DSP register from LINE. */
+static const char *
+parse_dsp_reg (const char *line, const metag_reg **reg,
+ bfd_boolean tmpl, bfd_boolean load)
+{
+ if (tmpl)
+ return parse_dsp_template_reg (line, reg, load);
+ else
+ return parse_dsp_insn_reg (line, reg);
+}
+
+/* Return TRUE if UNIT is an address unit. */
+static bfd_boolean
+is_addr_unit (enum metag_unit unit)
+{
+ switch (unit)
+ {
+ case UNIT_A0:
+ case UNIT_A1:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+}
+
+/* Return TRUE if UNIT1 and UNIT2 are equivalent units. */
+static bfd_boolean
+is_same_data_unit (enum metag_unit unit1, enum metag_unit unit2)
+{
+ if (unit1 == unit2)
+ return TRUE;
+
+ switch (unit1)
+ {
+ case UNIT_D0:
+ if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_RAM_D0)
+ return TRUE;
+ break;
+ case UNIT_D1:
+ if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_RAM_D1)
+ return TRUE;
+ break;
+ case UNIT_ACC_D0:
+ if (unit2 == UNIT_D0 || unit2 == UNIT_RAM_D0)
+ return TRUE;
+ break;
+ case UNIT_ACC_D1:
+ if (unit2 == UNIT_D1 || unit2 == UNIT_RAM_D1)
+ return TRUE;
+ break;
+ case UNIT_RAM_D0:
+ if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_D0)
+ return TRUE;
+ break;
+ case UNIT_RAM_D1:
+ if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_D1)
+ return TRUE;
+ break;
+ default:
+ return FALSE;
+ }
+
+ return FALSE;
+}
+
+/* Return TRUE if the register NUM is a quickrot control register. */
+static bfd_boolean
+is_quickrot_reg (unsigned int num)
+{
+ switch (num)
+ {
+ case 2:
+ case 3:
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/* Return TRUE if REG is an accumulator register. */
+static bfd_boolean
+is_accumulator_reg (const metag_reg *reg)
+{
+ if (reg->unit == UNIT_ACC_D0 || reg->unit == UNIT_ACC_D1)
+ return TRUE;
+
+ return FALSE;
+}
+
+/* Return TRUE if REG is a DSP RAM register. */
+static bfd_boolean
+is_dspram_reg (const metag_reg *reg)
+{
+ if (reg->unit == UNIT_RAM_D0 || reg->unit == UNIT_RAM_D1)
+ return TRUE;
+
+ return FALSE;
+}
+
+static const char *
+__parse_gp_reg (const char *line, const metag_reg **reg, bfd_boolean load)
+{
+ const char *l = line;
+ char reg_buf[MAX_REG_LEN];
+ size_t len = 0;
+
+ if (l == NULL)
+ return NULL;
+
+ /* Parse [DSPRAM.x]. */
+ if (*l == ADDR_BEGIN_CHAR)
+ {
+ l++;
+
+ if (l == NULL)
+ return NULL;
+
+ l = parse_dsp_reg (l, reg, TRUE, load);
+ if (l == NULL)
+ return NULL;
+
+ if (*l == ADDR_END_CHAR)
+ l++;
+ else
+ {
+ as_bad (_("expected ']', not %c in %s"), *l, l);
+ return NULL;
+ }
+
+ return l;
+ }
+ else
+ {
+
+ len = strip_reg_name (l, reg_buf);
+ if (!len)
+ return NULL;
+
+ l += len;
+ *reg = parse_gp_reg (reg_buf);
+ if (*reg == NULL)
+ return NULL;
+ }
+
+ return l;
+}
+
+/* Parse a list of DSP/GP registers. TRY_GP indicates whether we
+ should try to parse the register as a general-purpose register if
+ we fail to parse it as a DSP one. TMPL indicates whether the
+ registers are part of a template definition instruction. If this is
+ a template definition instruction LOAD says whether it's a load
+ template insn. FIRST_DST indicates whether the first register is
+ a destination operand. */
+static const char *
+parse_dsp_regs_list (const char *line, const metag_reg **regs, size_t count,
+ size_t *regs_read, bfd_boolean try_gp, bfd_boolean tmpl,
+ bfd_boolean load, bfd_boolean first_dst)
+{
+ const char *l = line;
+ int seen_regs = 0;
+ size_t i;
+ const metag_reg *reg;
+
+ for (i = 0; i < count; i++)
+ {
+ const char *next, *ll;
+
+ next = l;
+
+ if (i > 0)
+ {
+ l = skip_comma (l);
+ if (l == NULL)
+ {
+ *regs_read = seen_regs;
+ return next;
+ }
+ }
+
+ ll = parse_dsp_reg (l, ®, tmpl, load);
+
+ if (!ll)
+ {
+ if (try_gp)
+ {
+ l = __parse_gp_reg (l, ®, !(first_dst && i == 0));
+ if (l == NULL)
+ {
+ *regs_read = seen_regs;
+ return next;
+ }
+ regs[i] = reg;
+ seen_regs++;
+ }
+ else
+ {
+ *regs_read = seen_regs;
+ return l;
+ }
+ }
+ else
+ {
+ regs[i] = reg;
+ seen_regs++;
+ l = ll;
+ }
+ }
+
+ *regs_read = seen_regs;
+ return l;
+}
+
+/* Parse the following memory references:
+
+ - [Ax.r]
+ - [Ax.r++]
+ - [Ax.r--]
+ - [Ax.r+Ax.r++]
+ - [Ax.r-Ax.r--]
+
+ - [DSPRam]
+ - [DSPRam++]
+ - [DSPRam+DSPRam++]
+ - [DSPRam-DSPRam--] */
+static const char *
+parse_dsp_addr (const char *line, metag_addr *addr, unsigned int size,
+ bfd_boolean load)
+{
+ const char *l = line, *ll;
+ const metag_reg *regs[1];
+ size_t regs_read;
+
+ /* Skip opening square bracket. */
+ l++;
+
+ l = parse_dsp_regs_list (l, regs, 1, ®s_read, TRUE, TRUE, load, FALSE);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!is_addr_unit (regs[0]->unit) &&
+ !is_dspram_reg (regs[0]))
+ {
+ as_bad (_("invalid register for memory access"));
+ return NULL;
+ }
+
+ addr->base_reg = regs[0];
+
+ if (*l == ADDR_END_CHAR)
+ {
+ addr->exp.X_op = O_constant;
+ addr->exp.X_add_symbol = NULL;
+ addr->exp.X_op_symbol = NULL;
+
+ /* Simple register with no offset (0 immediate). */
+ addr->exp.X_add_number = 0;
+
+ addr->immediate = 1;
+ l++;
+
+ return l;
+ }
+
+ ll = parse_addr_post_incr_op (l, addr);
+
+ if (ll && *ll == ADDR_END_CHAR)
+ {
+ if (addr->update == 1)
+ {
+ /* We have a post increment/decrement. */
+ addr->exp.X_op = O_constant;
+ addr->exp.X_add_number = size;
+ addr->exp.X_add_symbol = NULL;
+ addr->exp.X_op_symbol = NULL;
+ addr->post_increment = 1;
+ }
+ addr->immediate = 1;
+ ll++;
+ return ll;
+ }
+
+ addr->post_increment = 0;
+
+ l = parse_addr_op (l, addr);
+
+ if (l == NULL)
+ return NULL;
+
+ l = parse_dsp_regs_list (l, regs, 1, ®s_read, TRUE, TRUE, load, FALSE);
+
+ if (l == NULL)
+ return NULL;
+
+ if (regs[0]->unit != addr->base_reg->unit)
+ {
+ as_bad (_("offset and base must be from the same unit"));
+ return NULL;
+ }
+
+ addr->offset_reg = regs[0];
+
+ if (*l == ADDR_END_CHAR)
+ {
+ l++;
+ return l;
+ }
+
+ l = parse_addr_post_incr_op (l, addr);
+
+ if (l == NULL)
+ return NULL;
+
+ if (*l == ADDR_END_CHAR)
+ {
+ l++;
+ return l;
+ }
+
+ return NULL;
+}
+
+/* Parse a DSP GET or SET instruction. */
+static const char *
+parse_dget_set (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ metag_addr addr;
+ int unit = 0;
+ int rd_reg = 0;
+ bfd_boolean is_get = (template->meta_opcode & 0x100);
+ bfd_boolean is_dual = (template->meta_opcode & 0x4);
+ bfd_boolean is_template = FALSE;
+ const metag_reg *regs[2];
+ unsigned int size;
+ size_t count, regs_read;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.reloc_type = BFD_RELOC_UNUSED;
+
+ size = is_dual ? 8 : 4;
+ count = is_dual ? 2 : 1;
+
+ if (is_get)
+ {
+ /* GETL can be used on one template table entry. */
+ if (*l == 'T')
+ count = 1;
+
+ l = parse_dsp_regs_list (l, regs, count, ®s_read, FALSE,
+ FALSE, FALSE, FALSE);
+ l = skip_comma (l);
+
+ if (l == NULL)
+ {
+ as_bad (_("unexpected end of line"));
+ return NULL;
+ }
+
+ l = parse_addr (l, &addr, size);
+ }
+ else
+ {
+ l = parse_addr (l, &addr, size);
+
+ l = skip_comma (l);
+
+ if (l == NULL)
+ return NULL;
+
+ /* GETL can be used on one template table entry. */
+ if (*l == 'T')
+ count = 1;
+
+ l = parse_dsp_regs_list (l, regs, count, ®s_read, FALSE, FALSE,
+ FALSE, FALSE);
+ }
+
+ if (l == NULL)
+ return NULL;
+
+ /* The first register dictates the unit. */
+ if (regs[0]->unit == UNIT_DT)
+ is_template = TRUE;
+ else
+ {
+ if (regs[0]->unit == UNIT_D0 || regs[0]->unit == UNIT_RAM_D0 ||
+ regs[0]->unit == UNIT_ACC_D0)
+ unit = 0;
+ else
+ unit = 1;
+ }
+
+ rd_reg = regs[0]->no;
+
+ /* The 'H' modifier allows a DSP GET/SET instruction to target the
+ upper 8-bits of an accumulator. It is _only_ valid for the
+ accumulators. */
+ if (insn->dsp_daoppame_flags & DSP_DAOPPAME_HIGH)
+ {
+ if (is_template || !(rd_reg >= 16 && rd_reg < 20))
+ {
+ as_bad (_("'H' modifier only valid for accumulator registers"));
+ return NULL;
+ }
+
+ /* Top 8-bits of the accumulator. */
+ rd_reg |= 8;
+ }
+
+ if (is_template)
+ {
+ insn->bits = (template->meta_opcode | (1 << 1));
+ }
+ else
+ {
+ insn->bits = (template->meta_opcode | unit);
+ }
+
+ insn->bits |= (rd_reg << 19);
+
+ if (addr.immediate)
+ {
+ int offset = addr.exp.X_add_number;
+
+ if (addr.negate)
+ offset = -offset;
+
+ offset = offset / (int)size;
+
+ if (!within_signed_range (offset, DGET_SET_IMM_BITS))
+ {
+ as_bad (_("offset value out of range"));
+ return NULL;
+ }
+
+ offset = offset & DGET_SET_IMM_MASK;
+
+ insn->bits |= (1 << 13);
+ insn->bits |= (offset << 9);
+ }
+ else
+ {
+ int au = (addr.base_reg->unit == UNIT_A1);
+
+ insn->bits |= (au << 18);
+ insn->bits |= ((addr.base_reg->no & REG_MASK) << 14);
+ insn->bits |= ((addr.offset_reg->no & REG_MASK) << 9);
+ }
+
+ if (is_dual)
+ insn->bits |= (1 << 2);
+
+ if (!is_addr_unit (addr.base_reg->unit))
+ {
+ as_bad (_("base unit must be either A0 or A1"));
+ return NULL;
+ }
+
+ unit = (addr.base_reg->unit == UNIT_A0) ? 0 : 1;
+ insn->bits |= ((addr.base_reg->no << 14) | (unit << 18));
+
+ insn->len = 4;
+
+ return l;
+}
+
+/* Parse a DSP template instruction. */
+static const char *
+parse_dtemplate (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const metag_reg *regs[TEMPLATE_NUM_REGS];
+ bfd_boolean daop_only = FALSE;
+ int regs_val[4];
+ int regs_which[4] = { -1, -1, -1, -1}; /* Register or immediate? */
+ int i;
+
+ for (i = 0; i < TEMPLATE_NUM_REGS; i++)
+ {
+ if (l == NULL)
+ {
+ as_bad (_("unexpected end of line"));
+ return NULL;
+ }
+
+ /* We may only have 3 register operands. */
+ if (*l == END_OF_INSN && i == 3)
+ {
+ daop_only = TRUE;
+ break;
+ }
+
+ if (i != 0)
+ {
+ l = skip_comma (l);
+ if (l == NULL)
+ return NULL;
+ }
+
+ if (*l == IMM_CHAR)
+ {
+ l = parse_imm_constant (l, insn, ®s_val[i]);
+ if (l == NULL)
+ {
+ as_bad (_("invalid immediate"));
+ return NULL;
+ }
+ regs_which[i] = 0;
+ }
+ else
+ {
+ /* We can't tell from the template instantiation whether
+ this is a load or store. So we have to try looking up the
+ register name in both the load and store tables. */
+ const char *l2 = l;
+ l = __parse_gp_reg (l, ®s[i], TRUE);
+ if (l == NULL)
+ {
+ /* Try the store table too. */
+ l = __parse_gp_reg (l2, ®s[i], FALSE);
+ if (l == NULL)
+ {
+ /* Then try a DSP register. */
+ l = parse_dsp_insn_reg (l2, ®s[i]);
+ if (l == NULL || regs[i]->unit == UNIT_DT)
+ {
+ as_bad (_("invalid register"));
+ return NULL;
+ }
+ }
+ }
+ regs_which[i] = 1;
+ }
+ }
+
+ insn->bits = template->meta_opcode;
+
+ if (regs_which[0] == 0)
+ insn->bits |= (regs_val[0] << 19);
+ else if (regs_which[0] == 1)
+ insn->bits |= (regs[0]->no << 19);
+
+ if (regs_which[1] == 0)
+ insn->bits |= (regs_val[1] << 14);
+ else if (regs_which[1] == 1)
+ insn->bits |= (regs[1]->no << 14);
+
+ if (regs_which[2] == 0)
+ insn->bits |= (regs_val[2] << 9);
+ else if (regs_which[2] == 1)
+ insn->bits |= (regs[2]->no << 9);
+
+ if (regs_which[3] == 0)
+ insn->bits |= (regs_val[3] << 4);
+ else if (regs_which[3] == 1)
+ insn->bits |= (regs[3]->no << 4);
+
+ /* DaOp only. */
+ if (daop_only)
+ insn->bits |= (0x3 << 24); /* Set the minor opcode. */
+ else if (insn->dsp_daoppame_flags & DSP_DAOPPAME_HIGH) /* Half Load/Store. */
+ insn->bits |= (0x5 << 24); /* Set the minor opcode. */
+
+ insn->len = 4;
+
+ return l;
+}
+
+/* Parse a DSP Template definiton memory reference, e.g
+ [A0.7+A0.5++]. DSPRAM is set to true by this function if this
+ template definition is a DSP RAM template definition. */
+static const char *
+template_mem_ref(const char *line, metag_addr *addr,
+ bfd_boolean *dspram, int size, bfd_boolean load)
+{
+ const char *l = line;
+
+ l = parse_dsp_addr (l, addr, size, load);
+
+ if (l != NULL)
+ {
+ if (is_addr_unit(addr->base_reg->unit))
+ *dspram = FALSE;
+ else
+ *dspram = TRUE;
+ }
+
+ return l;
+}
+
+/* Sets LOAD to TRUE if this is a Template load definiton (otherwise
+ it's a store). Fills out ADDR, TEMPLATE_REG and ADDR_UNIT. */
+static const char *
+parse_template_regs (const char *line, bfd_boolean *load,
+ unsigned int *addr_unit,
+ const metag_reg **template_reg, metag_addr *addr,
+ bfd_boolean *dspram, int size)
+{
+ const char *l = line;
+
+ if (l == NULL)
+ return NULL;
+
+ /* DSP Template load definition (Tx, [Ax]) */
+ if (*l == 'T')
+ {
+ *load = TRUE;
+ l = parse_dsp_reg (l, &template_reg[0], FALSE, FALSE);
+ if (l == NULL)
+ return NULL;
+
+ l = skip_comma (l);
+
+ l = template_mem_ref (l, addr, dspram, size, *load);
+
+ if (addr->base_reg->unit == UNIT_A1)
+ *addr_unit = 1;
+
+ }
+ else if (*l == ADDR_BEGIN_CHAR) /* DSP Template store ([Ax], Tx) */
+ {
+ *load = FALSE;
+ l = template_mem_ref (l, addr, dspram, size, *load);
+ l = skip_comma(l);
+
+ if (l == NULL)
+ return NULL;
+
+ l = parse_dsp_reg (l, &template_reg[0], FALSE, FALSE);
+ if (l == NULL)
+ return NULL;
+
+ if (addr->base_reg->unit == UNIT_A1)
+ *addr_unit = 1;
+ }
+ else
+ {
+ as_bad (_("invalid register operand"));
+ return NULL;
+ }
+
+ return l;
+}
+
+#define INVALID_SHIFT (-1)
+
+static metag_reg _reg;
+
+/* Parse a template instruction definition. */
+static const char *
+interpret_template_regs(const char *line, metag_insn *insn,
+ const metag_reg **regs,
+ int *regs_shift, bfd_boolean *load, bfd_boolean *dspram,
+ int size, int *ls_shift, int *au_shift,
+ unsigned int *au, int *imm, int *imm_shift,
+ unsigned int *imm_mask)
+{
+ const char *l = line;
+ metag_addr addr;
+ const metag_reg *template_reg[1];
+
+ memset (&addr, 0, sizeof(addr));
+
+ regs_shift[0] = 19;
+ regs_shift[1] = INVALID_SHIFT;
+
+ insn->bits |= (1 << 1);
+
+ l = skip_whitespace (l);
+
+ l = parse_template_regs (l, load, au, template_reg,
+ &addr, dspram, size);
+ if (l == NULL)
+ {
+ as_bad (_("could not parse template definition"));
+ return NULL;
+ }
+
+ regs[2] = template_reg[0];
+ regs_shift[2] = 9;
+
+ /* DSPRAM definition. */
+ if (*dspram)
+ {
+
+ _reg = *addr.base_reg;
+
+ if (addr.immediate)
+ {
+ /* Set the post-increment bit in the register field. */
+ if (addr.update)
+ _reg.no |= 0x1;
+ }
+ else
+ {
+ /* The bottom bit of the increment register tells us
+ whether it's increment register 0 or 1. */
+ if (addr.offset_reg->no & 0x1)
+ _reg.no |= 0x3;
+ else
+ _reg.no |= 0x2;
+ }
+
+ regs[0] = &_reg;
+
+ insn->bits |= (0x3 << 17); /* This signifies a DSPRAM definition. */
+ }
+ else /* DaOpPaMe definition. */
+ {
+ regs[0] = addr.base_reg;
+ if (addr.immediate)
+ {
+ /* Set the I bit. */
+ insn->bits |= (1 << 18);
+
+ if (addr.update == 1)
+ {
+ if (addr.negate == 1)
+ *imm = 0x3;
+ else
+ *imm = 0x1;
+ }
+
+ *imm_shift = 14;
+ *imm_mask = 0x3;
+ }
+ else
+ {
+ /* Setup the offset register. */
+ regs[1] = addr.offset_reg;
+ regs_shift[1] = 14;
+ }
+ *au_shift = 23;
+ }
+
+ *ls_shift = 13;
+
+ return l;
+}
+
+/* Does this combination of units need the O2R bit and can it be encoded? */
+static bfd_boolean
+units_need_o2r (enum metag_unit unit1, enum metag_unit unit2)
+{
+ if (unit1 == unit2)
+ return FALSE;
+
+ if (unit1 == UNIT_D0 || unit1 == UNIT_ACC_D0 || unit1 == UNIT_RAM_D0)
+ {
+ if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_RAM_D0 || unit2 == UNIT_D0)
+ return FALSE;
+
+ switch (unit2)
+ {
+ case UNIT_A1:
+ case UNIT_D1:
+ case UNIT_RD:
+ case UNIT_A0:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+ }
+
+ if (unit1 == UNIT_D1 || unit1 == UNIT_ACC_D1 || unit1 == UNIT_RAM_D1)
+ {
+ if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_RAM_D1 || unit2 == UNIT_D1)
+ return FALSE;
+
+ switch (unit2)
+ {
+ case UNIT_A1:
+ case UNIT_D0:
+ case UNIT_RD:
+ case UNIT_A0:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+ }
+
+ return FALSE;
+}
+
+/* Return TRUE if this is a DSP data unit. */
+static bfd_boolean
+is_dsp_data_unit (const metag_reg *reg)
+{
+ switch (reg->unit)
+ {
+ case UNIT_D0:
+ case UNIT_D1:
+ case UNIT_ACC_D0:
+ case UNIT_ACC_D1:
+ case UNIT_RAM_D0:
+ case UNIT_RAM_D1:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+}
+
+static metag_reg o2r_reg;
+
+/* Parse a DaOpPaMe load template definition. */
+static const char *
+parse_dalu (const char *line, metag_insn *insn,
+ const insn_template *template)
+{
+ const char *l = line;
+ const char *ll;
+ const metag_reg *regs[4];
+ metag_addr addr;
+ size_t regs_read;
+ bfd_boolean is_mov = MAJOR_OPCODE (template->meta_opcode) == OPC_ADD;
+ bfd_boolean is_cmp = ((MAJOR_OPCODE (template->meta_opcode) == OPC_CMP) &&
+ ((template->meta_opcode & 0xee) == 0));
+ bfd_boolean is_dual = (insn->dsp_width == DSP_WIDTH_DUAL);
+ bfd_boolean is_quickrot64 = ((insn->dsp_action_flags & DSP_ACTION_QR64) != 0);
+ int l1_shift = INVALID_SHIFT;
+ bfd_boolean load = FALSE;
+ int ls_shift = INVALID_SHIFT;
+ bfd_boolean ar = FALSE;
+ int ar_shift = INVALID_SHIFT;
+ int regs_shift[3] = { INVALID_SHIFT, INVALID_SHIFT, INVALID_SHIFT };
+ int imm = 0;
+ int imm_shift = INVALID_SHIFT;
+ unsigned int imm_mask = 0;
+ unsigned int au = 0;
+ int au_shift = INVALID_SHIFT;
+ unsigned int du = 0;
+ int du_shift = INVALID_SHIFT;
+ unsigned int sc = ((insn->dsp_action_flags & DSP_ACTION_OV) != 0);
+ int sc_shift = INVALID_SHIFT;
+ unsigned int om = ((insn->dsp_action_flags & DSP_ACTION_MOD) != 0);
+ int om_shift = INVALID_SHIFT;
+ unsigned int o2r = 0;
+ int o2r_shift = INVALID_SHIFT;
+ unsigned int qr = 0;
+ int qr_shift = INVALID_SHIFT;
+ int qd_shift = INVALID_SHIFT;
+ unsigned int qn = 0;
+ int qn_shift = INVALID_SHIFT;
+ unsigned int a1 = ((insn->dsp_action_flags & (DSP_ACTION_ACC_SUB|DSP_ACTION_ACC_ZERO)) != 0);
+ int a1_shift = INVALID_SHIFT;
+ unsigned int a2 = ((insn->dsp_action_flags & (DSP_ACTION_ACC_SUB|DSP_ACTION_ACC_ADD)) != 0);
+ int a2_shift = INVALID_SHIFT;
+ unsigned su = ((insn->dsp_action_flags & DSP_ACTION_UMUL) != 0);
+ int su_shift = INVALID_SHIFT;
+ unsigned int ac;
+ int ac_shift = INVALID_SHIFT;
+ unsigned int mx = (((insn->dsp_daoppame_flags & DSP_DAOPPAME_8) != 0) ||
+ (insn->dsp_daoppame_flags & DSP_DAOPPAME_16) != 0);
+ int mx_shift = INVALID_SHIFT;
+ int size = is_dual ? 8 : 4;
+ bfd_boolean dspram;
+ bfd_boolean conditional = (MINOR_OPCODE (template->meta_opcode) & 0x4);
+
+ /* XFIXME: check the flags are valid with the instruction. */
+ if (is_quickrot64 && !(template->arg_type & DSP_ARGS_QR))
+ {
+ as_bad (_("QUICKRoT 64-bit extension not applicable to this instruction"));
+ return NULL;
+ }
+
+ insn->bits = template->meta_opcode;
+
+ memset (regs, 0, sizeof (regs));
+ memset (&addr, 0, sizeof (addr));
+
+ /* There are the following forms of DSP ALU instructions,
+
+ * Group 1:
+ 19. D[T] Op De.r,Dx.r,De.r
+ 1. D[T] Op De.r,Dx.r,De.r|ACe.r [Accumulator in src 2]
+ 3. D[T] Op De.r,Dx.r,De.r[,Ae.r] [QUICKRoT]
+ 2. D[T] Op ACe.e,ACx.r,ACo.e [cross-unit accumulator op]
+ 5. D[T] Op De.r|ACe.r,Dx.r,De.r
+ 20. D[T] Op De.r,Dx.r|ACx.r,De.r
+ 8. D Opcc De.r,Dx.r,Rx.r
+ 6. D Op De.r,Dx.r,Rx.r|RD
+ 17. D Op De.r|ACe.r,Dx.r,Rx.r|RD
+ 7. D Op De.e,Dx.r,#I16
+
+ * Group 2:
+ 4. D[T] Op Dx.r,De.r
+ 10. D Op Dx.r,Rx.r|RD
+ 13. D Op Dx.r,Rx.r
+ 11. D Op Dx.r,#I16
+ 12. D[T] Op De.r,Dx.r
+ 14. D Op DSPe.r,Dx.r
+ 15. D Op DSPx.r,#I16
+ 16. D Op De.r,DSPx.r
+ 18. D Op De.r,Dx.r|ACx.r
+
+ * Group 3:
+ 22. D Op De.r,Dx.r|ACx.r,De.r|#I5
+ 23. D Op Ux.r,Dx.r|ACx.r,De.r|#I5
+ 21. D Op De.r,Dx.r|ACx.r,#I5 */
+
+ /* Group 1. */
+ if (template->arg_type & DSP_ARGS_1)
+ {
+ du_shift = 24;
+
+ /* Could this be a cross-unit accumulator op,
+ e.g. ACe.e,ACx.r,ACo.e */
+ if (template->arg_type & DSP_ARGS_XACC)
+ {
+ ll = parse_dsp_regs_list (l, regs, 3, ®s_read, FALSE, FALSE,
+ FALSE, FALSE);
+ if (ll != NULL && regs_read == 3
+ && is_accumulator_reg (regs[0]))
+ {
+ if (regs[0]->unit != regs[1]->unit ||
+ regs[2]->unit == regs[1]->unit)
+ {
+ as_bad (_("invalid operands for cross-unit op"));
+ return NULL;
+ }
+
+ du = (regs[1]->unit == UNIT_ACC_D1);
+ regs_shift[1] = 19;
+ l = ll;
+
+ /* All cross-unit accumulator ops have bits 8 and 6 set. */
+ insn->bits |= (5 << 6);
+
+ goto check_for_template;
+ }
+
+ /* If we reach here, this instruction is not a
+ cross-unit accumulator op. */
+ }
+
+ if (template->arg_type & DSP_ARGS_SPLIT8)
+ om_shift = 7;
+
+ sc_shift = 5;
+ l1_shift = 4;
+ o2r_shift = 0;
+
+ /* De.r|ACe.r,Dx.r,De.r */
+ if (template->arg_type & DSP_ARGS_DACC)
+ {
+ /* XFIXME: these need moving? */
+ a2_shift = 7;
+ su_shift = 6;
+ a1_shift = 2;
+ om_shift = 3;
+
+ ll = parse_dsp_reg (l, ®s[0], FALSE, FALSE);
+ if (ll != NULL)
+ {
+ /* Using ACe.r as the dst requires one of the P,N or Z
+ flags to be used. */
+ if (!(insn->dsp_action_flags &
+ (DSP_ACTION_ACC_SUB|DSP_ACTION_ACC_ADD|DSP_ACTION_ACC_ZERO)))
+ {
+ as_bad (_("missing flags: one of 'P', 'N' or 'Z' required"));
+ return NULL;
+ }
+
+ l = ll;
+ l = skip_comma (l);
+ l = parse_dsp_regs_list (l, ®s[1], 2, ®s_read,
+ TRUE, FALSE, FALSE, FALSE);
+ if (l == NULL || regs_read != 2)
+ {
+ as_bad (_("invalid register"));
+ return NULL;
+ }
+
+ if (regs[1]->unit == UNIT_D1 || regs[1]->unit == UNIT_RAM_D1)
+ du = 1;
+
+ regs_shift[0] = 19;
+ regs_shift[1] = 14;
+ regs_shift[2] = 9;
+ goto check_for_template;
+ }
+
+ /* If we reach here, this instruction does not use the
+ accumulator as the destination register. */
+ if ((insn->dsp_action_flags &
+ (DSP_ACTION_ACC_SUB|DSP_ACTION_ACC_ADD|DSP_ACTION_ACC_ZERO)))
+ {
+ as_bad (_("'P', 'N' or 'Z' flags may only be specified when accumulating"));
+ return NULL;
+ }
+ }
+
+ regs_shift[0] = 19;
+
+
+ l = parse_dsp_regs_list (l, regs, 2, ®s_read, TRUE, FALSE, FALSE, TRUE);
+ if (l == NULL || regs_read != 2)
+ return NULL;
+
+ l = skip_comma (l);
+ if (l == NULL)
+ return NULL;
+
+ if (regs[1]->unit == UNIT_D1 || regs[1]->unit == UNIT_RAM_D1)
+ du = 1;
+
+ if (is_accumulator_reg(regs[0]) && !(template->arg_type & DSP_ARGS_DACC))
+ {
+ as_bad (_("accumulator not a valid destination"));
+ return NULL;
+ }
+
+ /* Check for immediate, e.g. De.r,Dx.r,#I16 */
+ if (*l == IMM_CHAR)
+ {
+ l = parse_imm16 (l, insn, &imm);
+ if (l == NULL)
+ {
+ as_bad (_("invalid immediate value"));
+ return NULL;
+ }
+
+ if (!within_signed_range (imm, IMM16_BITS))
+ {
+ as_bad (_("immediate value out of range"));
+ return NULL;
+ }
+
+ if (regs[0]->unit != regs[1]->unit || regs[0]->no != regs[1]->no)
+ {
+ as_bad (_("immediate value not allowed when source & dest differ"));
+ return NULL;
+ }
+
+ imm_mask = 0xffff;
+ imm_shift = 3;
+
+ /* Set the I-bit */
+ insn->bits |= (1 << 25);
+
+ insn->bits |= (0x3 << 0);
+
+ l1_shift = 2;
+
+ /* Remove any bits that have been set in the immediate
+ field. */
+ insn->bits &= ~(imm_mask << imm_shift);
+ }
+ else
+ {
+
+ regs_shift[1] = 14;
+ regs_shift[2] = 9;
+
+ /* Is Rs2 an accumulator reg, e.g. De.r,Dx.r,De.r|ACe.r */
+ ll = parse_dsp_reg (l, ®s[2], FALSE, FALSE);
+ if (ll != NULL)
+ {
+ l = ll;
+
+ if (!(template->arg_type & DSP_ARGS_ACC2))
+ {
+ as_bad (_("invalid register operand: %s"), regs[2]->name);
+ return NULL;
+ }
+
+ om_shift = 3;
+ ar_shift = 7;
+ ar = TRUE;
+ }
+ else
+ {
+ /* De.r,Dx.r,De.r */
+ l = __parse_gp_reg (l, ®s[2], TRUE);
+ if (l == NULL)
+ return NULL;
+ }
+
+ if (template->arg_type & DSP_ARGS_ACC2)
+ om_shift = 3;
+
+ /* Is this a QUICKRoT instruction? De.r,Dx.r,De.r[,Ae.r] */
+ if (template->arg_type & DSP_ARGS_QR)
+ {
+ if (conditional)
+ qn_shift = 5;
+ else
+ {
+ qn_shift = 7;
+ qr_shift = 6;
+ qd_shift = 5;
+ }
+
+ l = skip_comma (l);
+ if (l == NULL)
+ {
+ as_bad (_("QUICKRoT extension requires 4 registers"));
+ return NULL;
+ }
+
+ l = __parse_gp_reg (l, ®s[3], TRUE);
+ if (l == NULL)
+ {
+ as_bad (_("invalid fourth register"));
+ return NULL;
+ }
+
+ if (!is_addr_unit (regs[3]->unit) ||
+ !is_quickrot_reg (regs[3]->no))
+ {
+ as_bad (_("A0.2,A0.3,A1.2,A1.3 required for QUICKRoT register"));
+ return NULL;
+ }
+
+ qn = (regs[3]->no == 3);
+ }
+ }
+
+ check_for_template:
+ /* This is the common exit path. Check for o2r. */
+ if (regs[2] != NULL)
+ {
+ o2r = units_need_o2r (regs[1]->unit, regs[2]->unit);
+ if (o2r)
+ {
+ o2r_reg.no = lookup_o2r (0, du, regs[2]);
+ o2r_reg.unit = regs[2]->unit;
+ regs[2] = &o2r_reg;
+ }
+ }
+
+ /* Check any DSP RAM pointers are valid for this unit. */
+ if ((du && (regs[0]->unit == UNIT_RAM_D0)) ||
+ (!du && (regs[0]->unit == UNIT_RAM_D1)) ||
+ (du && (regs[1]->unit == UNIT_RAM_D0)) ||
+ (!du && (regs[1]->unit == UNIT_RAM_D1)) ||
+ (du && regs[2] && (regs[2]->unit == UNIT_RAM_D0)) ||
+ (!du && regs[2] && (regs[2]->unit == UNIT_RAM_D1))) {
+ as_bad (_("DSP RAM pointer in incorrect unit"));
+ return NULL;
+ }
+
+ /* Is this a template definition? */
+ if (IS_TEMPLATE_DEF (insn))
+ {
+ l = interpret_template_regs(l, insn, regs, regs_shift, &load,
+ &dspram, size, &ls_shift, &au_shift,
+ &au, &imm, &imm_shift, &imm_mask);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!dspram)
+ mx_shift = 0;
+ }
+
+ goto matched;
+ }
+
+ /* Group 2. */
+ if (template->arg_type & DSP_ARGS_2)
+ {
+ bfd_boolean is_xsd = ((MAJOR_OPCODE (template->meta_opcode) == OPC_MISC) &&
+ (MINOR_OPCODE (template->meta_opcode) == 0xa));
+ bfd_boolean is_fpu_mov = template->insn_type == INSN_DSP_FPU;
+ bfd_boolean to_fpu = (template->meta_opcode >> 7) & 0x1;
+
+ if (is_xsd)
+ du_shift = 0;
+ else
+ du_shift = 24;
+
+ l1_shift = 4;
+
+ /* CMPs and TSTs don't store to their destination operand. */
+ ll = __parse_gp_reg (l, regs, is_cmp);
+ if (ll == NULL)
+ {
+ /* DSPe.r,Dx.r or DSPx.r,#I16 */
+ if (template->arg_type & DSP_ARGS_DSP_SRC1)
+ {
+ l = parse_dsp_reg (l, regs, FALSE, FALSE);
+ if (l == NULL)
+ {
+ as_bad (_("invalid register operand #1"));
+ return NULL;
+ }
+
+ /* Only MOV instructions have a DSP register as a
+ destination. Set the MOV DSPe.r opcode. The simple
+ OR'ing is OK because the usual MOV opcode is 0x00. */
+ insn->bits = (0x91 << 24);
+ du_shift = 0;
+ l1_shift = 2;
+ regs_shift[0] = 19;
+ }
+ else
+ {
+ as_bad (_("invalid register operand #2"));
+ return NULL;
+ }
+ }
+ else
+ {
+ l = ll;
+
+ /* Everything but CMP and TST. */
+ if (MAJOR_OPCODE (template->meta_opcode) == OPC_ADD ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_SUB ||
+ MAJOR_OPCODE (insn->bits) == OPC_9 ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_MISC ||
+ ((template->meta_opcode & 0x0000002c) != 0))
+ regs_shift[0] = 19;
+ else
+ regs_shift[0] = 14;
+ }
+
+ if (!is_dsp_data_unit (regs[0]) && !(regs[0]->unit == UNIT_FX &&
+ is_fpu_mov && to_fpu))
+ return NULL;
+
+ du = (regs[0]->unit == UNIT_D1 || regs[0]->unit == UNIT_RAM_D1 ||
+ regs[0]->unit == UNIT_ACC_D1);
+
+ l = skip_comma (l);
+
+ if (*l == IMM_CHAR)
+ {
+ if (template->arg_type & DSP_ARGS_IMM &&
+ !(is_mov && (MAJOR_OPCODE (insn->bits) != OPC_9)))
+ {
+ l = parse_imm16 (l, insn, &imm);
+ if (l == NULL)
+ {
+ as_bad (_("invalid immediate value"));
+ return NULL;
+ }
+
+ if (!within_signed_range (imm, IMM16_BITS))
+ return NULL;
+
+ l1_shift = 2;
+ regs_shift[0] = 19;
+
+ imm_mask = 0xffff;
+ imm_shift = 3;
+
+ /* Set the I-bit unless it's a MOV because they're
+ different. */
+ if (!(is_mov && MAJOR_OPCODE (insn->bits) == OPC_9))
+ insn->bits |= (1 << 25);
+
+ /* All instructions that takes immediates also have bit 1 set. */
+ insn->bits |= (1 << 1);
+
+ if (MAJOR_OPCODE (insn->bits) != OPC_9)
+ insn->bits |= (1 << 0);
+
+ insn->bits &= ~(1 << 8);
+ }
+ else
+ {
+ as_bad (_("this instruction does not accept an immediate"));
+ return NULL;
+ }
+ }
+ else
+ {
+ if (MAJOR_OPCODE (insn->bits) != OPC_9)
+ {
+ insn->bits |= (1 << 8);
+ l1_shift = 4;
+ }
+
+ ll = __parse_gp_reg (l, ®s[1], TRUE);
+ if (ll == NULL)
+ {
+ if (template->arg_type & DSP_ARGS_DSP_SRC2)
+ {
+ l = parse_dsp_reg (l, ®s[1], FALSE, FALSE);
+ if (l == NULL)
+ {
+ as_bad (_("invalid register operand #3"));
+ return NULL;
+ }
+
+ /* MOV and NEG. */
+ if ((is_mov && (MAJOR_OPCODE (insn->bits) != OPC_9)) ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_SUB)
+ {
+ if (is_accumulator_reg (regs[1]))
+ {
+ if (is_fpu_mov)
+ {
+ as_bad (_("this instruction does not accept an accumulator"));
+ return NULL;
+ }
+ ar_shift = 7;
+ ar = 1;
+ regs_shift[1] = 9;
+ }
+ else
+ {
+ du_shift = 0;
+ l1_shift = 2;
+ regs_shift[1] = 14;
+ insn->bits = (0x92 << 24); /* Set opcode. */
+ }
+ }
+ }
+ else
+ {
+ as_bad (_("invalid register operand #4"));
+ return NULL;
+ }
+ }
+ else
+ {
+ /* Set the o2r bit if required. */
+ if (!is_fpu_mov && units_need_o2r (regs[0]->unit, regs[1]->unit))
+ {
+ o2r_reg = *regs[1];
+ o2r_reg.no = lookup_o2r (0, du, regs[1]);
+ regs[1] = &o2r_reg;
+ o2r_shift = 0;
+ o2r = 1;
+ }
+ else if (!is_dsp_data_unit (regs[1]) &&
+ !(is_fpu_mov && !to_fpu && regs[1]->unit == UNIT_FX))
+ return NULL;
+
+ if (is_fpu_mov && to_fpu)
+ du = (regs[1]->unit == UNIT_D1 ||
+ regs[1]->unit == UNIT_RAM_D1 ||
+ regs[1]->unit == UNIT_ACC_D1);
+
+ l = ll;
+
+ if (MAJOR_OPCODE (insn->bits) == OPC_ADD ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_SUB ||
+ (((template->meta_opcode & 0x0000002c) == 0) &&
+ MAJOR_OPCODE (template->meta_opcode) != OPC_MISC))
+ regs_shift[1] = 9;
+ else
+ regs_shift[1] = 14;
+ }
+ }
+
+ /* If it's an 0x0 MOV or NEG set some lower bits. */
+ if ((MAJOR_OPCODE (insn->bits) == OPC_ADD ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_SUB) && !is_fpu_mov)
+ {
+ om_shift = 3;
+ sc_shift = 5;
+ insn->bits |= (1 << 2);
+ }
+
+ /* Check for template definitons. */
+ if (IS_TEMPLATE_DEF (insn))
+ {
+ l = interpret_template_regs(l, insn, regs, regs_shift, &load,
+ &dspram, size, &ls_shift, &au_shift,
+ &au, &imm, &imm_shift, &imm_mask);
+ mx_shift = 0;
+
+ if (l == NULL)
+ return NULL;
+ }
+ goto matched;
+ }
+
+ /* Group 3. */
+ du_shift = 24;
+ l1_shift = 4;
+
+ l = __parse_gp_reg (l, regs, FALSE);
+ if (l == NULL)
+ {
+ as_bad (_("invalid register operand"));
+ return NULL;
+ }
+
+ l = skip_comma (l);
+
+ if (*l == 'A')
+ {
+ l = parse_dsp_reg (l, ®s[1], FALSE, FALSE);
+ if (l == NULL)
+ {
+ as_bad (_("invalid accumulator register"));
+ return NULL;
+ }
+ ac = 1;
+ ac_shift = 0;
+ }
+ else
+ {
+ l = __parse_gp_reg (l, ®s[1], TRUE);
+ if (l == NULL)
+ {
+ as_bad (_("invalid register operand"));
+ return NULL;
+ }
+ }
+
+ regs_shift[0] = 19;
+ regs_shift[1] = 14;
+
+ du = (regs[1]->unit == UNIT_D1 || regs[1]->unit == UNIT_ACC_D1
+ || regs[1]->unit == UNIT_RAM_D1);
+
+ l = skip_comma (l);
+
+ if (*l == IMM_CHAR)
+ {
+ l = parse_imm_constant (l, insn, &imm);
+ if (l == NULL)
+ {
+ as_bad (_("invalid immediate value"));
+ return NULL;
+ }
+
+ if (!within_unsigned_range (imm, IMM5_BITS))
+ return NULL;
+
+ imm_mask = 0x1f;
+ imm_shift = 9;
+
+ /* Set the I-bit */
+ insn->bits |= (1 << 25);
+ }
+ else
+ {
+ regs_shift[2] = 9;
+ l = __parse_gp_reg (l, ®s[2], TRUE);
+ if (l == NULL)
+ return NULL;
+ }
+
+ /* Check for post-processing R,G,B flags. Conditional instructions
+ do not have these bits. */
+ if (insn->dsp_action_flags & DSP_ACTION_CLAMP9)
+ {
+ if ((template->meta_opcode >> 26) & 0x1)
+ {
+ as_bad (_("conditional instruction cannot use G flag"));
+ return NULL;
+ }
+
+ insn->bits |= (1 << 3);
+ }
+
+ if (insn->dsp_action_flags & DSP_ACTION_CLAMP8)
+ {
+ if ((template->meta_opcode >> 26) & 0x1)
+ {
+ as_bad (_("conditional instruction cannot use B flag"));
+ return NULL;
+ }
+
+ insn->bits |= (0x3 << 2);
+ }
+
+ if (insn->dsp_action_flags & DSP_ACTION_ROUND)
+ {
+ if ((template->meta_opcode >> 26) & 0x1)
+ {
+ as_bad (_("conditional instruction cannot use R flag"));
+ return NULL;
+ }
+ insn->bits |= (1 << 2);
+ }
+
+ /* Conditional Data Unit Shift instructions cannot be dual unit. */
+ if ((template->meta_opcode >> 26) & 0x1)
+ ls_shift = INVALID_SHIFT;
+
+ /* The Condition Is Always (CA) bit must be set if we're targetting a
+ Ux.r register as the destination. This means that we can't have
+ any other condition bits set. */
+ if (!is_same_data_unit (regs[1]->unit, regs[0]->unit))
+ {
+ /* Set both the Conditional bit and the Condition is Always bit. */
+ insn->bits |= (1 << 26);
+ insn->bits |= (1 << 5);
+
+ /* Fill out the Ud field. */
+ insn->bits |= (regs[0]->unit << 1);
+ }
+
+ if (IS_TEMPLATE_DEF (insn))
+ {
+ l = interpret_template_regs(l, insn, regs, regs_shift, &load,
+ &dspram, size, &ls_shift, &au_shift,
+ &au, &imm, &imm_shift, &imm_mask);
+
+ if (l == NULL)
+ return NULL;
+
+ if (!dspram)
+ mx_shift = 5;
+ }
+
+ /* Fall through. */
+ matched:
+
+ /* Set the registers and immediate values. */
+ if (regs_shift[0] != INVALID_SHIFT)
+ insn->bits |= (regs[0]->no << regs_shift[0]);
+
+ if (regs_shift[1] != INVALID_SHIFT)
+ insn->bits |= (regs[1]->no << regs_shift[1]);
+
+ if (regs_shift[2] != INVALID_SHIFT)
+ insn->bits |= (regs[2]->no << regs_shift[2]);
+
+ /* Does this insn have an 'IMM' bit? The immediate value should
+ already have been masked. */
+ if (imm_shift != INVALID_SHIFT)
+ insn->bits |= ((imm & imm_mask) << imm_shift);
+
+ /* Does this insn have an 'AU' bit? */
+ if (au_shift != INVALID_SHIFT)
+ insn->bits |= (au << au_shift);
+
+ /* Does this instruction have an 'LS' bit? */
+ if (ls_shift != INVALID_SHIFT)
+ insn->bits |= (load << ls_shift);
+
+ /* Does this instruction have an 'AR' bit? */
+ if (ar)
+ insn->bits |= (1 << ar_shift);
+
+ if (du_shift != INVALID_SHIFT)
+ insn->bits |= (du << du_shift);
+
+ if (sc_shift != INVALID_SHIFT)
+ insn->bits |= (sc << sc_shift);
+
+ if (om_shift != INVALID_SHIFT)
+ insn->bits |= (om << om_shift);
+
+ if (o2r_shift != INVALID_SHIFT)
+ insn->bits |= (o2r << o2r_shift);
+
+ if (qn_shift != INVALID_SHIFT)
+ insn->bits |= (qn << qn_shift);
+
+ if (qr_shift != INVALID_SHIFT)
+ insn->bits |= (qr << qr_shift);
+
+ if (qd_shift != INVALID_SHIFT)
+ insn->bits |= (is_quickrot64 << qd_shift);
+
+ if (a1_shift != INVALID_SHIFT)
+ insn->bits |= (a1 << a1_shift);
+
+ if (a2_shift != INVALID_SHIFT)
+ insn->bits |= (a2 << a2_shift);
+
+ if (su_shift != INVALID_SHIFT)
+ insn->bits |= (su << su_shift);
+
+ if (imm_shift != INVALID_SHIFT)
+ insn->bits |= ((imm & imm_mask) << imm_shift);
+
+ if (ac_shift != INVALID_SHIFT)
+ insn->bits |= (ac << ac_shift);
+
+ if (mx_shift != INVALID_SHIFT)
+ insn->bits |= (mx << mx_shift);
+
+ if (is_dual)
+ {
+ if (l1_shift == INVALID_SHIFT)
+ {
+ as_bad (_("'L' modifier not valid for this instruction"));
+ return NULL;
+ }
+
+ insn->bits |= (1 << l1_shift);
+ }
+
+ insn->len = 4;
+
+ return l;
+}
+
+typedef const char *(*insn_parser)(const char *, metag_insn *,
+ const insn_template *);
+
+/* Parser table. */
+static const insn_parser insn_parsers[ENC_MAX] =
+ {
+ [ENC_NONE] = parse_none,
+ [ENC_MOV_U2U] = parse_mov_u2u,
+ [ENC_MOV_PORT] = parse_mov_port,
+ [ENC_MMOV] = parse_mmov,
+ [ENC_MDRD] = parse_mdrd,
+ [ENC_MOVL_TTREC] = parse_movl_ttrec,
+ [ENC_GET_SET] = parse_get_set,
+ [ENC_GET_SET_EXT] = parse_get_set_ext,
+ [ENC_MGET_MSET] = parse_mget_mset,
+ [ENC_COND_SET] = parse_cond_set,
+ [ENC_XFR] = parse_xfr,
+ [ENC_MOV_CT] = parse_mov_ct,
+ [ENC_SWAP] = parse_swap,
+ [ENC_JUMP] = parse_jump,
+ [ENC_CALLR] = parse_callr,
+ [ENC_ALU] = parse_alu,
+ [ENC_SHIFT] = parse_shift,
+ [ENC_MIN_MAX] = parse_min_max,
+ [ENC_BITOP] = parse_bitop,
+ [ENC_CMP] = parse_cmp,
+ [ENC_BRANCH] = parse_branch,
+ [ENC_KICK] = parse_kick,
+ [ENC_SWITCH] = parse_switch,
+ [ENC_CACHER] = parse_cacher,
+ [ENC_CACHEW] = parse_cachew,
+ [ENC_ICACHE] = parse_icache,
+ [ENC_LNKGET] = parse_lnkget,
+ [ENC_FMOV] = parse_fmov,
+ [ENC_FMMOV] = parse_fmmov,
+ [ENC_FMOV_DATA] = parse_fmov_data,
+ [ENC_FMOV_I] = parse_fmov_i,
+ [ENC_FPACK] = parse_fpack,
+ [ENC_FSWAP] = parse_fswap,
+ [ENC_FCMP] = parse_fcmp,
+ [ENC_FMINMAX] = parse_fminmax,
+ [ENC_FCONV] = parse_fconv,
+ [ENC_FCONVX] = parse_fconvx,
+ [ENC_FBARITH] = parse_fbarith,
+ [ENC_FEARITH] = parse_fearith,
+ [ENC_FREC] = parse_frec,
+ [ENC_FSIMD] = parse_fsimd,
+ [ENC_FGET_SET_ACF] = parse_fget_set_acf,
+ [ENC_DGET_SET] = parse_dget_set,
+ [ENC_DTEMPLATE] = parse_dtemplate,
+ [ENC_DALU] = parse_dalu,
+ };
+
+struct metag_core_option
+{
+ char *name;
+ unsigned int value;
+};
+
+/* CPU type options. */
+static const struct metag_core_option metag_cpus[] =
+ {
+ {"all", CoreMeta11|CoreMeta12|CoreMeta21},
+ {"metac11", CoreMeta11},
+ {"metac12", CoreMeta12},
+ {"metac21", CoreMeta21},
+ {NULL, 0},
+ };
+
+/* FPU type options. */
+static const struct metag_core_option metag_fpus[] =
+ {
+ {"metac21", FpuMeta21},
+ {NULL, 0},
+ };
+
+/* DSP type options. */
+static const struct metag_core_option metag_dsps[] =
+ {
+ {"metac21", DspMeta21},
+ {NULL, 0},
+ };
+
+/* Parse a CPU command line option. */
+static int
+metag_parse_cpu (char * str)
+{
+ const struct metag_core_option * opt;
+ int optlen;
+
+ optlen = strlen (str);
+
+ if (optlen == 0)
+ {
+ as_bad (_("missing cpu name `%s'"), str);
+ return 0;
+ }
+
+ for (opt = metag_cpus; opt->name != NULL; opt++)
+ if (strncmp (opt->name, str, optlen) == 0)
+ {
+ mcpu_opt = opt->value;
+ return 1;
+ }
+
+ as_bad (_("unknown cpu `%s'"), str);
+ return 0;
+}
+
+/* Parse an FPU command line option. */
+static int
+metag_parse_fpu (char * str)
+{
+ const struct metag_core_option * opt;
+ int optlen;
+
+ optlen = strlen (str);
+
+ if (optlen == 0)
+ {
+ as_bad (_("missing fpu name `%s'"), str);
+ return 0;
+ }
+
+ for (opt = metag_fpus; opt->name != NULL; opt++)
+ if (strncmp (opt->name, str, optlen) == 0)
+ {
+ mfpu_opt = opt->value;
+ return 1;
+ }
+
+ as_bad (_("unknown fpu `%s'"), str);
+ return 0;
+}
+
+/* Parse a DSP command line option. */
+static int
+metag_parse_dsp (char * str)
+{
+ const struct metag_core_option * opt;
+ int optlen;
+
+ optlen = strlen (str);
+
+ if (optlen == 0)
+ {
+ as_bad (_("missing DSP name `%s'"), str);
+ return 0;
+ }
+
+ for (opt = metag_dsps; opt->name != NULL; opt++)
+ if (strncmp (opt->name, str, optlen) == 0)
+ {
+ mdsp_opt = opt->value;
+ return 1;
+ }
+
+ as_bad (_("unknown DSP `%s'"), str);
+ return 0;
+}
+
+struct metag_long_option
+{
+ char * option; /* Substring to match. */
+ char * help; /* Help information. */
+ int (* func) (char * subopt); /* Function to decode sub-option. */
+ char * deprecated; /* If non-null, print this message. */
+};
+
+struct metag_long_option metag_long_opts[] =
+ {
+ {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
+ metag_parse_cpu, NULL},
+ {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
+ metag_parse_fpu, NULL},
+ {"mdsp=", N_("<dsp name>\t assemble for DSP architecture <dsp name>"),
+ metag_parse_dsp, NULL},
+ {NULL, NULL, 0, NULL}
+ };
+
+int
+md_parse_option (int c, char * arg)
+{
+ struct metag_long_option *lopt;
+
+ for (lopt = metag_long_opts; lopt->option != NULL; lopt++)
+ {
+ /* These options are expected to have an argument. */
+ if (c == lopt->option[0]
+ && arg != NULL
+ && strncmp (arg, lopt->option + 1,
+ strlen (lopt->option + 1)) == 0)
+ {
+#if WARN_DEPRECATED
+ /* If the option is deprecated, tell the user. */
+ if (lopt->deprecated != NULL)
+ as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
+ _(lopt->deprecated));
+#endif
+
+ /* Call the sup-option parser. */
+ return lopt->func (arg + strlen (lopt->option) - 1);
+ }
+ }
+
+ return 0;
+}
+
+void
+md_show_usage (FILE * stream)
+{
+ struct metag_long_option *lopt;
+
+ fprintf (stream, _(" Meta specific command line options:\n"));
+
+ for (lopt = metag_long_opts; lopt->option != NULL; lopt++)
+ if (lopt->help != NULL)
+ fprintf (stream, " -%s%s\n", lopt->option, _(lopt->help));
+}
+
+/* The target specific pseudo-ops which we support. */
+const pseudo_typeS md_pseudo_table[] =
+{
+ { "word", cons, 2 },
+ { NULL, NULL, 0 }
+};
+
+void
+md_begin (void)
+{
+ int c;
+
+ for (c = 0; c < 256; c++)
+ {
+ if (ISDIGIT (c))
+ {
+ register_chars[c] = c;
+ /* LOCK0, LOCK1, LOCK2. */
+ mnemonic_chars[c] = c;
+ }
+ else if (ISLOWER (c))
+ {
+ register_chars[c] = c;
+ mnemonic_chars[c] = c;
+ }
+ else if (ISUPPER (c))
+ {
+ register_chars[c] = c;
+ mnemonic_chars[c] = c;
+ }
+ else if (c == '.')
+ {
+ register_chars[c] = c;
+ }
+ }
+}
+
+/* Parse a split condition code prefix. */
+static const char *
+parse_split_condition (const char *line, metag_insn *insn)
+{
+ const char *l = line;
+ const split_condition *scond;
+ split_condition entry;
+ char buf[4];
+
+ memcpy (buf, l, 4);
+ buf[3] = '\0';
+
+ entry.name = buf;
+
+ scond = (const split_condition *) htab_find (scond_htab, &entry);
+
+ if (!scond)
+ return NULL;
+
+ insn->scond = scond->code;
+
+ return l + strlen (scond->name);
+}
+
+/* Parse an instruction prefix - F for float, D for DSP - and associated
+ flags and condition codes. */
+static const char *
+parse_prefix (const char *line, metag_insn *insn)
+{
+ const char *l = line;
+
+ l = skip_whitespace (l);
+
+ insn->type = INSN_GP;
+
+ if (TOLOWER (*l) == FPU_PREFIX_CHAR)
+ {
+ if (strncasecmp (l, FFB_INSN, strlen(FFB_INSN)))
+ {
+ insn->type = INSN_FPU;
+
+ l++;
+
+ if (*l == END_OF_INSN)
+ {
+ as_bad (_("premature end of floating point prefix"));
+ return NULL;
+ }
+
+ if (TOLOWER (*l) == FPU_DOUBLE_CHAR)
+ {
+ insn->fpu_width = FPU_WIDTH_DOUBLE;
+ l++;
+ }
+ else if (TOLOWER (*l) == FPU_PAIR_CHAR)
+ {
+ const char *l2 = l;
+
+ /* Check this isn't a split condition beginning with L. */
+ l2 = parse_split_condition (l2, insn);
+
+ if (l2 && is_whitespace_char (*l2))
+ {
+ l = l2;
+ }
+ else
+ {
+ insn->fpu_width = FPU_WIDTH_PAIR;
+ l++;
+ }
+ }
+ else
+ {
+ insn->fpu_width = FPU_WIDTH_SINGLE;
+ }
+
+ if (TOLOWER (*l) == FPU_ACTION_ABS_CHAR)
+ {
+ insn->fpu_action_flags |= FPU_ACTION_ABS;
+ l++;
+ }
+ else if (TOLOWER (*l) == FPU_ACTION_INV_CHAR)
+ {
+ insn->fpu_action_flags |= FPU_ACTION_INV;
+ l++;
+ }
+
+ if (TOLOWER (*l) == FPU_ACTION_QUIET_CHAR)
+ {
+ insn->fpu_action_flags |= FPU_ACTION_QUIET;
+ l++;
+ }
+
+ if (TOLOWER (*l) == FPU_ACTION_ZERO_CHAR)
+ {
+ insn->fpu_action_flags |= FPU_ACTION_ZERO;
+ l++;
+ }
+
+ if (! is_whitespace_char (*l))
+ {
+ l = parse_split_condition (l, insn);
+
+ if (!l)
+ {
+ as_bad (_("unknown floating point prefix character"));
+ return NULL;
+ }
+ }
+
+ l = skip_space (l);
+ }
+ }
+ else if (TOLOWER (*l) == DSP_PREFIX_CHAR)
+ {
+ if (strncasecmp (l, DCACHE_INSN, strlen (DCACHE_INSN)) &&
+ strncasecmp (l, DEFR_INSN, strlen (DEFR_INSN)))
+ {
+ const char *ll = l;
+ insn->type = INSN_DSP;
+
+ l++;
+
+ insn->dsp_width = DSP_WIDTH_SINGLE;
+
+ while (!is_whitespace_char (*l))
+ {
+ /* We have to check for split condition codes first
+ because they are the longest strings to match,
+ e.g. if the string contains "LLS" we want it to match
+ the split condition code "LLS", not the dual unit
+ character "L". */
+ ll = l;
+ l = parse_split_condition (l, insn);
+
+ if (l == NULL)
+ l = ll;
+ else
+ continue;
+
+ /* Accept an FPU prefix char which may be used when doing
+ template MOV with FPU registers. */
+ if (TOLOWER(*l) == FPU_PREFIX_CHAR)
+ {
+ insn->type = INSN_DSP_FPU;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_DUAL_CHAR)
+ {
+ insn->dsp_width = DSP_WIDTH_DUAL;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_QR64_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_QR64;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_UMUL_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_UMUL;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_ROUND_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_ROUND;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_CLAMP9_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_CLAMP9;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_CLAMP8_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_CLAMP8;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_MOD_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_MOD;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_ACC_ZERO_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_ACC_ZERO;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_ACC_ADD_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_ACC_ADD;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_ACC_SUB_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_ACC_SUB;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_ACTION_OV_CHAR)
+ {
+ insn->dsp_action_flags |= DSP_ACTION_OV;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_DAOPPAME_8_CHAR)
+ {
+ insn->dsp_daoppame_flags |= DSP_DAOPPAME_8;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_DAOPPAME_16_CHAR)
+ {
+ insn->dsp_daoppame_flags |= DSP_DAOPPAME_16;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_DAOPPAME_TEMP_CHAR)
+ {
+ insn->dsp_daoppame_flags |= DSP_DAOPPAME_TEMP;
+ l++;
+ continue;
+ }
+
+ if (TOLOWER(*l) == DSP_DAOPPAME_HIGH_CHAR)
+ {
+ insn->dsp_daoppame_flags |= DSP_DAOPPAME_HIGH;
+ l++;
+ continue;
+ }
+
+ as_bad (_("unknown DSP prefix character %c %s"), *l, l);
+ return NULL;
+ }
+
+ l = skip_space (l);
+ }
+ }
+
+ return l;
+}
+
+/* Return a list of appropriate instruction parsers for MNEMONIC. */
+static insn_templates *
+find_insn_templates (const char *mnemonic)
+{
+ insn_template template;
+ insn_templates entry;
+ insn_templates *slot;
+
+ entry.template = &template;
+
+ memcpy ((void *)&entry.template->name, &mnemonic, sizeof (char *));
+
+ slot = (insn_templates *) htab_find (mnemonic_htab, &entry);
+
+ if (slot)
+ return slot;
+
+ return NULL;
+}
+
+/* Make an uppercase copy of SRC into DST and return DST. */
+static char *
+strupper (char * dst, const char *src)
+{
+ size_t i = 0;
+
+ while (src[i])
+ {
+ dst[i] = TOUPPER (src[i]);
+ i++;
+ }
+
+ dst[i] = 0;
+
+ return dst;
+}
+
+/* Calculate a hash value for a template. */
+static hashval_t
+hash_templates (const void *p)
+{
+ insn_templates *tp = (insn_templates *)p;
+ char buf[MAX_MNEMONIC_LEN];
+
+ strupper (buf, tp->template->name);
+
+ return htab_hash_string (buf);
+}
+
+/* Check if two templates are equal. */
+static int
+eq_templates (const void *a, const void *b)
+{
+ insn_templates *ta = (insn_templates *)a;
+ insn_templates *tb = (insn_templates *)b;
+ return strcasecmp (ta->template->name, tb->template->name) == 0;
+}
+
+/* Create the hash table required for parsing instructions. */
+static void
+create_mnemonic_htab (void)
+{
+ size_t i, num_templates = sizeof(metag_optab)/sizeof(metag_optab[0]);
+
+ mnemonic_htab = htab_create_alloc (num_templates, hash_templates,
+ eq_templates, NULL, xcalloc, free);
+
+ for (i = 0; i < num_templates; i++)
+ {
+ const insn_template *template = &metag_optab[i];
+ insn_templates **slot = NULL;
+ insn_templates *new_entry;
+
+ new_entry = xmalloc (sizeof (insn_templates));
+
+ new_entry->template = template;
+ new_entry->next = NULL;
+
+ slot = (insn_templates **) htab_find_slot (mnemonic_htab, new_entry,
+ INSERT);
+
+ if (*slot)
+ {
+ insn_templates *last_entry = *slot;
+
+ while (last_entry->next)
+ last_entry = last_entry->next;
+
+ last_entry->next = new_entry;
+ }
+ else
+ {
+ *slot = new_entry;
+ }
+ }
+}
+
+/* Calculate a hash value for a register. */
+static hashval_t
+hash_regs (const void *p)
+{
+ metag_reg *rp = (metag_reg *)p;
+ char buf[MAX_REG_LEN];
+
+ strupper (buf, rp->name);
+
+ return htab_hash_string (buf);
+}
+
+/* Check if two registers are equal. */
+static int
+eq_regs (const void *a, const void *b)
+{
+ metag_reg *ra = (metag_reg *)a;
+ metag_reg *rb = (metag_reg *)b;
+ return strcasecmp (ra->name, rb->name) == 0;
+}
+
+/* Create the hash table required for parsing registers. */
+static void
+create_reg_htab (void)
+{
+ size_t i, num_regs = sizeof(metag_regtab)/sizeof(metag_regtab[0]);
+
+ reg_htab = htab_create_alloc (num_regs, hash_regs,
+ eq_regs, NULL, xcalloc, free);
+
+ for (i = 0; i < num_regs; i++)
+ {
+ const metag_reg *reg = &metag_regtab[i];
+ const metag_reg **slot;
+
+ slot = (const metag_reg **) htab_find_slot (reg_htab, reg, INSERT);
+
+ if (!*slot)
+ *slot = reg;
+ }
+}
+
+/* Create the hash table required for parsing DSP registers. */
+static void
+create_dspreg_htabs (void)
+{
+ size_t i, num_regs = sizeof(metag_dsp_regtab)/sizeof(metag_dsp_regtab[0]);
+ size_t h;
+
+ dsp_reg_htab = htab_create_alloc (num_regs, hash_regs,
+ eq_regs, NULL, xcalloc, free);
+
+ for (i = 0; i < num_regs; i++)
+ {
+ const metag_reg *reg = &metag_dsp_regtab[i];
+ const metag_reg **slot;
+
+ slot = (const metag_reg **) htab_find_slot (dsp_reg_htab, reg, INSERT);
+
+ /* Make sure there are no hash table collisions, which would
+ require chaining entries. */
+ BFD_ASSERT (*slot == NULL);
+ *slot = reg;
+ }
+
+ num_regs = sizeof(metag_dsp_tmpl_regtab[0])/sizeof(metag_dsp_tmpl_regtab[0][0]);
+
+ for (h = 0; h < 2; h++)
+ {
+ dsp_tmpl_reg_htab[h] = htab_create_alloc (num_regs, hash_regs,
+ eq_regs, NULL, xcalloc, free);
+ }
+
+ for (h = 0; h < 2; h++)
+ {
+ for (i = 0; i < num_regs; i++)
+ {
+ const metag_reg *reg = &metag_dsp_tmpl_regtab[h][i];
+ const metag_reg **slot;
+ slot = (const metag_reg **) htab_find_slot (dsp_tmpl_reg_htab[h],
+ reg, INSERT);
+
+ /* Make sure there are no hash table collisions, which would
+ require chaining entries. */
+ BFD_ASSERT (*slot == NULL);
+ *slot = reg;
+ }
+ }
+}
+
+/* Calculate a hash value for a split condition code. */
+static hashval_t
+hash_scond (const void *p)
+{
+ split_condition *cp = (split_condition *)p;
+ char buf[4];
+
+ strupper (buf, cp->name);
+
+ return htab_hash_string (buf);
+}
+
+/* Check if two split condition codes are equal. */
+static int
+eq_scond (const void *a, const void *b)
+{
+ split_condition *ra = (split_condition *)a;
+ split_condition *rb = (split_condition *)b;
+
+ return strcasecmp (ra->name, rb->name) == 0;
+}
+
+/* Create the hash table required for parsing split condition codes. */
+static void
+create_scond_htab (void)
+{
+ size_t i, nentries;
+
+ nentries = sizeof (metag_scondtab) / sizeof (metag_scondtab[0]);
+
+ scond_htab = htab_create_alloc (nentries, hash_scond, eq_scond,
+ NULL, xcalloc, free);
+ for (i = 0; i < nentries; i++)
+ {
+ const split_condition *scond = &metag_scondtab[i];
+ const split_condition **slot;
+
+ slot = (const split_condition **) htab_find_slot (scond_htab,
+ scond, INSERT);
+ /* Make sure there are no hash table collisions, which would
+ require chaining entries. */
+ BFD_ASSERT (*slot == NULL);
+ *slot = scond;
+ }
+}
+
+/* Entry point for instruction parsing. */
+static bfd_boolean
+parse_insn (const char *line, metag_insn *insn)
+{
+ char mnemonic[MAX_MNEMONIC_LEN];
+ const char *l = line;
+ size_t mnemonic_len = 0;
+ insn_templates *templates;
+
+ l = skip_space (l);
+
+ while (is_mnemonic_char(*l))
+ {
+ l++;
+ mnemonic_len++;
+ }
+
+ if (mnemonic_len >= MAX_MNEMONIC_LEN)
+ {
+ as_bad (_("instruction mnemonic too long: %s"), line);
+ return FALSE;
+ }
+
+ strncpy(mnemonic, line, mnemonic_len);
+
+ mnemonic[mnemonic_len] = '\0';
+
+ templates = find_insn_templates (mnemonic);
+
+ if (templates)
+ {
+ insn_templates *current_template = templates;
+
+ l = skip_space (l);
+
+ while (current_template)
+ {
+ const insn_template *template = current_template->template;
+ enum insn_encoding encoding = template->encoding;
+ insn_parser parser = insn_parsers[encoding];
+
+ current_template = current_template->next;
+
+ if (template->insn_type == INSN_GP &&
+ !(template->core_flags & mcpu_opt))
+ continue;
+
+ if (template->insn_type == INSN_FPU &&
+ !(template->core_flags & mfpu_opt))
+ continue;
+
+ if (template->insn_type == INSN_DSP &&
+ !(template->core_flags & mdsp_opt))
+ continue;
+
+ if (template->insn_type == INSN_DSP_FPU &&
+ !((template->core_flags & mdsp_opt) &&
+ (template->core_flags & mfpu_opt)))
+ continue;
+
+ /* DSP instructions always require special decoding */
+ if ((insn->type == INSN_DSP && (template->insn_type != INSN_DSP)) ||
+ ((template->insn_type == INSN_DSP) && insn->type != INSN_DSP) ||
+ (insn->type == INSN_DSP_FPU && (template->insn_type != INSN_DSP_FPU)) ||
+ ((template->insn_type == INSN_DSP_FPU) && insn->type != INSN_DSP_FPU))
+ continue;
+
+ if (parser)
+ {
+ const char *end = parser(l, insn, template);
+
+ if (end != NULL)
+ {
+ if (*end != END_OF_INSN)
+ as_bad (_("junk at end of line: \"%s\""), line);
+ else
+ return TRUE;
+ }
+ }
+ }
+
+ as_bad (_("failed to assemble instruction: \"%s\""), line);
+ }
+ else
+ {
+ if (insn->type == INSN_FPU)
+ as_bad (_("unknown floating point mnemonic: \"%s\""), mnemonic);
+ else
+ as_bad (_("unknown mnemonic: \"%s\""), mnemonic);
+ }
+ return FALSE;
+}
+
+static void
+output_insn (metag_insn *insn)
+{
+ char *output;
+
+ output = frag_more (insn->len);
+ dwarf2_emit_insn (insn->len);
+
+ if (insn->reloc_type != BFD_RELOC_UNUSED)
+ {
+ fix_new_exp (frag_now, output - frag_now->fr_literal,
+ insn->reloc_size, &insn->reloc_exp,
+ insn->reloc_pcrel, insn->reloc_type);
+ }
+
+ md_number_to_chars (output, insn->bits, insn->len);
+}
+
+void
+md_assemble (char *line)
+{
+ const char *l = line;
+ metag_insn insn;
+
+ memset (&insn, 0, sizeof(insn));
+
+ insn.reloc_type = BFD_RELOC_UNUSED;
+ insn.reloc_pcrel = 0;
+ insn.reloc_size = 4;
+
+ if (!mnemonic_htab)
+ {
+ create_mnemonic_htab ();
+ create_reg_htab ();
+ create_dspreg_htabs ();
+ create_scond_htab ();
+ }
+
+ l = parse_prefix (l, &insn);
+
+ if (l == NULL)
+ return;
+
+ if (insn.type == INSN_DSP &&
+ !mdsp_opt)
+ {
+ as_bad (_("cannot assemble DSP instruction, DSP option not set: %s"),
+ line);
+ return;
+ }
+ else if (insn.type == INSN_FPU &&
+ !mfpu_opt)
+ {
+ as_bad (_("cannot assemble FPU instruction, FPU option not set: %s"),
+ line);
+ return;
+ }
+
+ if (!parse_insn (l, &insn))
+ return;
+
+ output_insn (&insn);
+}
+
+void
+md_operand (expressionS * expressionP)
+{
+ if (* input_line_pointer == IMM_CHAR)
+ {
+ input_line_pointer ++;
+ expression (expressionP);
+ }
+}
+
+valueT
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
+{
+ return size;
+}
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+ return NULL;
+}
+
+/* Functions concerning relocs. */
+
+/* The location from which a PC relative jump should be calculated,
+ given a PC relative reloc. */
+
+long
+md_pcrel_from_section (fixS * fixP, segT sec)
+{
+ if ((fixP->fx_addsy != (symbolS *) NULL
+ && (! S_IS_DEFINED (fixP->fx_addsy)
+ || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+ || metag_force_relocation (fixP))
+ {
+ /* The symbol is undefined (or is defined but not in this section).
+ Let the linker figure it out. */
+ return 0;
+ }
+
+ return fixP->fx_frag->fr_address + fixP->fx_where;
+}
+
+/* Write a value out to the object file, using the appropriate endianness. */
+
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+ number_to_chars_littleendian (buf, val, n);
+}
+
+/* Turn a string in input_line_pointer into a floating point constant of type
+ type, and store the appropriate bytes in *litP. The number of LITTLENUMS
+ emitted is stored in *sizeP . An error message is returned, or NULL on OK.
+*/
+
+/* Equal to MAX_PRECISION in atof-ieee.c */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (int type, char * litP, int * sizeP)
+{
+ int i;
+ int prec;
+ LITTLENUM_TYPE words [MAX_LITTLENUMS];
+ char * t;
+
+ switch (type)
+ {
+ case 'f':
+ case 'F':
+ case 's':
+ case 'S':
+ prec = 2;
+ break;
+
+ case 'd':
+ case 'D':
+ case 'r':
+ case 'R':
+ prec = 4;
+ break;
+
+ /* FIXME: Some targets allow other format chars for bigger sizes here. */
+
+ default:
+ * sizeP = 0;
+ return _("Bad call to md_atof()");
+ }
+
+ t = atof_ieee (input_line_pointer, type, words);
+ if (t)
+ input_line_pointer = t;
+ * sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+ for (i = 0; i < prec; i++)
+ {
+ md_number_to_chars (litP, (valueT) words[i],
+ sizeof (LITTLENUM_TYPE));
+ litP += sizeof (LITTLENUM_TYPE);
+ }
+
+ return 0;
+}
+
+/* If this function returns non-zero, it prevents the relocation
+ against symbol(s) in the FIXP from being replaced with relocations
+ against section symbols, and guarantees that a relocation will be
+ emitted even when the value can be resolved locally. */
+
+int
+metag_force_relocation (fixS * fix)
+{
+ switch (fix->fx_r_type)
+ {
+ case BFD_RELOC_METAG_RELBRANCH_PLT:
+ case BFD_RELOC_METAG_TLS_LE:
+ case BFD_RELOC_METAG_TLS_IE:
+ case BFD_RELOC_METAG_TLS_LDO:
+ case BFD_RELOC_METAG_TLS_LDM:
+ case BFD_RELOC_METAG_TLS_GD:
+ return 1;
+ default:
+ ;
+ }
+
+ return generic_force_reloc (fix);
+}
+
+bfd_boolean
+metag_fix_adjustable (fixS * fixP)
+{
+ if (fixP->fx_addsy == NULL)
+ return 1;
+
+ /* Prevent all adjustments to global symbols. */
+ if (S_IS_EXTERNAL (fixP->fx_addsy))
+ return 0;
+ if (S_IS_WEAK (fixP->fx_addsy))
+ return 0;
+
+ if (fixP->fx_r_type == BFD_RELOC_METAG_HI16_GOTOFF ||
+ fixP->fx_r_type == BFD_RELOC_METAG_LO16_GOTOFF ||
+ fixP->fx_r_type == BFD_RELOC_METAG_GETSET_GOTOFF ||
+ fixP->fx_r_type == BFD_RELOC_METAG_GETSET_GOT ||
+ fixP->fx_r_type == BFD_RELOC_METAG_HI16_GOTPC ||
+ fixP->fx_r_type == BFD_RELOC_METAG_LO16_GOTPC ||
+ fixP->fx_r_type == BFD_RELOC_METAG_HI16_PLT ||
+ fixP->fx_r_type == BFD_RELOC_METAG_LO16_PLT ||
+ fixP->fx_r_type == BFD_RELOC_METAG_RELBRANCH_PLT)
+ return 0;
+
+ /* We need the symbol name for the VTABLE entries. */
+ if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+ return 0;
+
+ return 1;
+}
+
+/* Return an initial guess of the length by which a fragment must grow to
+ hold a branch to reach its destination.
+ Also updates fr_type/fr_subtype as necessary.
+
+ Called just before doing relaxation.
+ Any symbol that is now undefined will not become defined.
+ The guess for fr_var is ACTUALLY the growth beyond fr_fix.
+ Whatever we do to grow fr_fix or fr_var contributes to our returned value.
+ Although it may not be explicit in the frag, pretend fr_var starts with a
+ 0 value. */
+
+int
+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
+ segT segment ATTRIBUTE_UNUSED)
+{
+ /* No assembler relaxation is defined (or necessary) for this port. */
+ abort ();
+}
+
+/* *fragP has been relaxed to its final size, and now needs to have
+ the bytes inside it modified to conform to the new size.
+
+ Called after relaxation is finished.
+ fragP->fr_type == rs_machine_dependent.
+ fragP->fr_subtype is the subtype of what the address relaxed to. */
+
+void
+md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
+ fragS * fragP ATTRIBUTE_UNUSED)
+{
+ /* No assembler relaxation is defined (or necessary) for this port. */
+ abort ();
+}
+
+/* This is called from HANDLE_ALIGN in tc-metag.h. */
+
+void
+metag_handle_align (fragS * fragP)
+{
+ static char const noop[4] = { 0xfe, 0xff, 0xff, 0xa0 };
+ int bytes, fix;
+ char *p;
+
+ if (fragP->fr_type != rs_align_code)
+ return;
+
+ bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
+ p = fragP->fr_literal + fragP->fr_fix;
+ fix = 0;
+
+ if (bytes & 3)
+ {
+ fix = bytes & 3;
+ memset (p, 0, fix);
+ p += fix;
+ bytes -= fix;
+ }
+
+ while (bytes >= 4)
+ {
+ memcpy (p, noop, 4);
+ p += 4;
+ bytes -= 4;
+ fix += 4;
+ }
+
+ fragP->fr_fix += fix;
+ fragP->fr_var = 4;
+}
+
+static char *
+metag_end_of_match (char * cont, char * what)
+{
+ int len = strlen (what);
+
+ if (strncasecmp (cont, what, strlen (what)) == 0
+ && ! is_part_of_name (cont[len]))
+ return cont + len;
+
+ return NULL;
+}
+
+int
+metag_parse_name (char const * name, expressionS * exprP, enum expr_mode mode,
+ char * nextcharP)
+{
+ char *next = input_line_pointer;
+ char *next_end;
+ int reloc_type;
+ operatorT op_type;
+ segT segment;
+
+ exprP->X_op_symbol = NULL;
+ exprP->X_md = BFD_RELOC_UNUSED;
+
+ if (strcmp (name, GOT_NAME) == 0)
+ {
+ if (! GOT_symbol)
+ GOT_symbol = symbol_find_or_make (name);
+
+ exprP->X_add_symbol = GOT_symbol;
+ no_suffix:
+ /* If we have an absolute symbol or a
+ reg, then we know its value now. */
+ segment = S_GET_SEGMENT (exprP->X_add_symbol);
+ if (mode != expr_defer && segment == absolute_section)
+ {
+ exprP->X_op = O_constant;
+ exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
+ exprP->X_add_symbol = NULL;
+ }
+ else if (mode != expr_defer && segment == reg_section)
+ {
+ exprP->X_op = O_register;
+ exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
+ exprP->X_add_symbol = NULL;
+ }
+ else
+ {
+ exprP->X_op = O_symbol;
+ exprP->X_add_number = 0;
+ }
+
+ return 1;
+ }
+
+ exprP->X_add_symbol = symbol_find_or_make (name);
+
+ if (*nextcharP != '@')
+ goto no_suffix;
+ else if ((next_end = metag_end_of_match (next + 1, "GOTOFF")))
+ {
+ reloc_type = BFD_RELOC_METAG_GOTOFF;
+ op_type = O_PIC_reloc;
+ }
+ else if ((next_end = metag_end_of_match (next + 1, "GOT")))
+ {
+ reloc_type = BFD_RELOC_METAG_GETSET_GOT;
+ op_type = O_PIC_reloc;
+ }
+ else if ((next_end = metag_end_of_match (next + 1, "PLT")))
+ {
+ reloc_type = BFD_RELOC_METAG_PLT;
+ op_type = O_PIC_reloc;
+ }
+ else if ((next_end = metag_end_of_match (next + 1, "TLSGD")))
+ {
+ reloc_type = BFD_RELOC_METAG_TLS_GD;
+ op_type = O_PIC_reloc;
+ }
+ else if ((next_end = metag_end_of_match (next + 1, "TLSLDM")))
+ {
+ reloc_type = BFD_RELOC_METAG_TLS_LDM;
+ op_type = O_PIC_reloc;
+ }
+ else if ((next_end = metag_end_of_match (next + 1, "TLSLDO")))
+ {
+ reloc_type = BFD_RELOC_METAG_TLS_LDO;
+ op_type = O_PIC_reloc;
+ }
+ else if ((next_end = metag_end_of_match (next + 1, "TLSIE")))
+ {
+ reloc_type = BFD_RELOC_METAG_TLS_IE;
+ op_type = O_PIC_reloc;
+ }
+ else if ((next_end = metag_end_of_match (next + 1, "TLSIENONPIC")))
+ {
+ reloc_type = BFD_RELOC_METAG_TLS_IENONPIC;
+ op_type = O_PIC_reloc; /* FIXME: is this correct? */
+ }
+ else if ((next_end = metag_end_of_match (next + 1, "TLSLE")))
+ {
+ reloc_type = BFD_RELOC_METAG_TLS_LE;
+ op_type = O_PIC_reloc;
+ }
+ else
+ goto no_suffix;
+
+ *input_line_pointer = *nextcharP;
+ input_line_pointer = next_end;
+ *nextcharP = *input_line_pointer;
+ *input_line_pointer = '\0';
+
+ exprP->X_op = op_type;
+ exprP->X_add_number = 0;
+ exprP->X_md = reloc_type;
+
+ return 1;
+}
+
+/* If while processing a fixup, a reloc really needs to be created
+ then it is done here. */
+
+arelent *
+tc_gen_reloc (seg, fixp)
+ asection *seg ATTRIBUTE_UNUSED;
+ fixS *fixp;
+{
+ arelent *reloc;
+
+ reloc = (arelent *) xmalloc (sizeof (arelent));
+ reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+ reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+
+ reloc->addend = fixp->fx_offset;
+ reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+
+ if (reloc->howto == (reloc_howto_type *) NULL)
+ {
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ /* xgettext:c-format. */
+ _("reloc %d not supported by object file format"),
+ (int) fixp->fx_r_type);
+
+ xfree (reloc);
+
+ return NULL;
+ }
+
+ return reloc;
+}
+
+static unsigned int
+md_chars_to_number (char *val, int n)
+{
+ int retval;
+ unsigned char * where = (unsigned char *) val;
+
+ for (retval = 0; n--;)
+ {
+ retval <<= 8;
+ retval |= where[n];
+ }
+ return retval;
+}
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+ char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
+ int value = (int)*valP;
+
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_METAG_TLS_GD:
+ case BFD_RELOC_METAG_TLS_LE_HI16:
+ case BFD_RELOC_METAG_TLS_LE_LO16:
+ case BFD_RELOC_METAG_TLS_IE:
+ case BFD_RELOC_METAG_TLS_IENONPIC_HI16:
+ case BFD_RELOC_METAG_TLS_IENONPIC_LO16:
+ case BFD_RELOC_METAG_TLS_LDM:
+ case BFD_RELOC_METAG_TLS_LDO_HI16:
+ case BFD_RELOC_METAG_TLS_LDO_LO16:
+ S_SET_THREAD_LOCAL (fixP->fx_addsy);
+ /* Fall through */
+
+ case BFD_RELOC_METAG_HIADDR16:
+ case BFD_RELOC_METAG_LOADDR16:
+ case BFD_RELOC_VTABLE_INHERIT:
+ case BFD_RELOC_VTABLE_ENTRY:
+ fixP->fx_done = FALSE;
+ break;
+
+ case BFD_RELOC_METAG_REL8:
+ if (!within_unsigned_range (value, IMM8_BITS))
+ {
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ "rel8 out of range %d", value);
+ }
+ else
+ {
+ unsigned int newval;
+ newval = md_chars_to_number (buf, 4);
+ newval = (newval & 0xffffc03f) | ((value & IMM8_MASK) << 6);
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+ case BFD_RELOC_METAG_REL16:
+ if (!within_unsigned_range (value, IMM16_BITS))
+ {
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ "rel16 out of range %d", value);
+ }
+ else
+ {
+ unsigned int newval;
+ newval = md_chars_to_number (buf, 4);
+ newval = (newval & 0xfff80007) | ((value & IMM16_MASK) << 3);
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+
+ case BFD_RELOC_8:
+ md_number_to_chars (buf, value, 1);
+ break;
+ case BFD_RELOC_16:
+ md_number_to_chars (buf, value, 2);
+ break;
+ case BFD_RELOC_32:
+ md_number_to_chars (buf, value, 4);
+ break;
+ case BFD_RELOC_64:
+ md_number_to_chars (buf, value, 8);
+
+ case BFD_RELOC_METAG_RELBRANCH:
+ if (!value)
+ break;
+
+ value = value / 4;
+
+ if (!within_signed_range (value, IMM19_BITS))
+ {
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ "relbranch out of range %d", value);
+ }
+ else
+ {
+ unsigned int newval;
+ newval = md_chars_to_number (buf, 4);
+ newval = (newval & 0xff00001f) | ((value & IMM19_MASK) << 5);
+ md_number_to_chars (buf, newval, 4);
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (fixP->fx_addsy == NULL)
+ fixP->fx_done = TRUE;
+}
--- /dev/null
+/* tc-metag.h -- Header file for tc-metag.c.
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#define TC_METAG
+
+#define LISTING_HEADER "META GAS "
+
+/* The target BFD architecture. */
+#define TARGET_ARCH bfd_arch_metag
+
+#define TARGET_FORMAT "elf32-metag"
+
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+/* Permit temporary numeric labels. */
+#define LOCAL_LABELS_FB 1
+
+#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
+
+/* We don't need to handle .word strangely. */
+#define WORKING_DOT_WORD
+
+/* Values passed to md_apply_fix don't include the symbol value. */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define tc_fix_adjustable(FIX) metag_fix_adjustable (FIX)
+extern bfd_boolean metag_fix_adjustable (struct fix *);
+
+#define TC_FORCE_RELOCATION(fix) metag_force_relocation (fix)
+extern int metag_force_relocation (struct fix *);
+
+#define TC_HANDLES_FX_DONE
+
+/* Call md_pcrel_from_section(), not md_pcrel_from(). */
+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+#define HANDLE_ALIGN(fragp) metag_handle_align (fragp)
+extern void metag_handle_align (struct frag *);
+
+#define DWARF2_LINE_MIN_INSN_LENGTH 1
+
+#define md_parse_name(name, exprP, mode, nextcharP) \
+ metag_parse_name ((name), (exprP), (mode), (nextcharP))
+extern int metag_parse_name (char const *, expressionS *, enum expr_mode, char *);
+
+/* This is used to construct expressions out of @GOTOFF, @PLT and @GOT
+ symbols. The relocation type is stored in X_md. */
+#define O_PIC_reloc O_md1
+
+#define TC_CASE_SENSITIVE
+
+extern const char metag_symbol_chars[];
+#define tc_symbol_chars metag_symbol_chars
mep-*-elf) fmt=elf ;;
+ metag-*-elf) fmt=elf ;;
+ metag-*-linux*) fmt=elf em=linux ;;
+
mcore-*-elf) fmt=elf ;;
mcore-*-pe) fmt=coff em=pe bfd_gas=yes ;;
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
+ c-metag.texi \
c-microblaze.texi \
c-mips.texi \
c-mmix.texi \
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
+ c-metag.texi \
c-microblaze.texi \
c-mips.texi \
c-mmix.texi \
@set M68HC11
@set M680X0
@set MCORE
+@set METAG
@set MICROBLAZE
@set MIPS
@set MMIX
[@b{-jsri2bsr}] [@b{-sifilter}] [@b{-relax}]
[@b{-mcpu=[210|340]}]
@end ifset
+@ifset METAG
+
+@emph{Target Meta options:}
+ [@b{-mcpu=@var{cpu}}] [@b{-mfpu=@var{cpu}}] [@b{-mdsp=@var{cpu}}]
+@end ifset
@ifset MICROBLAZE
@emph{Target MICROBLAZE options:}
@c MicroBlaze has no machine-dependent assembler options.
@end table
@end ifset
+@c man end
+@ifset METAG
+
+@ifclear man
+@xref{Meta Options}, for the options available when @value{AS} is configured
+for a Meta processor.
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for a
+Meta processor.
+@c man end
+@c man begin INCLUDE
+@include c-metag.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
+@c man begin OPTIONS
@ifset MMIX
See the info pages for documentation of the MMIX-specific options.
@end ifset
@ifset M68HC11
* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
@end ifset
+@ifset METAG
+* Meta-Dependent :: Meta Dependent Features
+@end ifset
@ifset MICROBLAZE
* MicroBlaze-Dependent:: MICROBLAZE Dependent Features
@end ifset
@include c-m68hc11.texi
@end ifset
+@ifset METAG
+@include c-metag.texi
+@end ifset
+
@ifset MICROBLAZE
@include c-microblaze.texi
@end ifset
--- /dev/null
+@c Copyright 2013 Free Software Foundation, Inc.
+@c Contributed by Imagination Technologies Ltd.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node Meta-Dependent
+@chapter Meta Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter Meta Dependent Features
+@end ifclear
+
+@cindex Meta support
+@menu
+* Meta Options:: Options
+* Meta Syntax:: Meta Assembler Syntax
+@end menu
+
+@node Meta Options
+@section Options
+
+@cindex options for Meta
+@cindex Meta options
+@cindex architectures, Meta
+@cindex Meta architectures
+
+The Imagination Technologies Meta architecture is implemented in a
+number of versions, with each new version adding new features such as
+instructions and registers. For precise details of what instructions
+each core supports, please see the chip's technical reference manual.
+
+The following table lists all available Meta options.
+
+@table @code
+@item -mcpu=metac11
+Generate code for Meta 1.1.
+
+@item -mcpu=metac12
+Generate code for Meta 1.2.
+
+@item -mcpu=metac21
+Generate code for Meta 2.1.
+
+@item -mfpu=metac21
+Allow code to use FPU hardware of Meta 2.1.
+
+@end table
+
+@node Meta Syntax
+@section Syntax
+
+@menu
+* Meta-Chars:: Special Characters
+* Meta-Regs:: Register Names
+@end menu
+
+@node Meta-Chars
+@subsection Special Characters
+
+@cindex line comment character, Meta
+@cindex Meta line comment character
+@samp{!} is the line comment character.
+
+@cindex line separator, Meta
+@cindex statement separator, Meta
+@cindex Meta line separator
+You can use @samp{;} instead of a newline to separate statements.
+
+@cindex symbol names, @samp{$} in
+@cindex @code{$} in symbol names
+Since @samp{$} has no special meaning, you may use it in symbol names.
+
+@node Meta-Regs
+@subsection Register Names
+
+@cindex Meta registers
+@cindex registers, Meta
+Registers can be specified either using their mnemonic names, such as
+@samp{D0Re0}, or using the unit plus register number separated by a @samp{.},
+such as @samp{D0.0}.
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * gas/metag/labelarithmetic.d: New file.
+ * gas/metag/labelarithmetic.s: New file.
+ * gas/metag/metacore12.d: New file.
+ * gas/metag/metacore12.s: New file.
+ * gas/metag/metacore21-invalid.l: New file.
+ * gas/metag/metacore21-invalid.s: New file.
+ * gas/metag/metacore21.d: New file.
+ * gas/metag/metacore21.s: New file.
+ * gas/metag/metacore21ext.d: New file.
+ * gas/metag/metacore21ext.s: New file.
+ * gas/metag/metadsp21-invalid.l: New file.
+ * gas/metag/metadsp21-invalid.s: New file.
+ * gas/metag/metadsp21.d: New file.
+ * gas/metag/metadsp21.s: New file.
+ * gas/metag/metadsp21ext.d: New file.
+ * gas/metag/metadsp21ext.s: New file.
+ * gas/metag/metafpu21.d: New file.
+ * gas/metag/metafpu21.s: New file.
+ * gas/metag/metafpu21ext.d: New file.
+ * gas/metag/metafpu21ext.s: New file.
+ * gas/metag/metag.exp: New file.
+ * gas/metag/tls.d: New file.
+ * gas/metag/tls.s: New file.
+
2013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/diagnostic.s: Add test.
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * dis-asm.h (print_insn_metag): New declaration.
+
2012-12-18 Aldy Hernandez <aldyh@redhat.com>
PR other/54324
extern int print_insn_m88k (bfd_vma, disassemble_info *);
extern int print_insn_mcore (bfd_vma, disassemble_info *);
extern int print_insn_mep (bfd_vma, disassemble_info *);
+extern int print_insn_metag (bfd_vma, disassemble_info *);
extern int print_insn_microblaze (bfd_vma, disassemble_info *);
extern int print_insn_mmix (bfd_vma, disassemble_info *);
extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * common.h: Fix case of "Meta".
+ * metag.h: New file.
+
2013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
* common.h (NT_ARM_TLS, NT_ARM_HW_BREAK, NT_ARM_HW_WATCH): New macro
#define EM_MANIK 171 /* M2000 Reconfigurable RISC Microprocessor */
#define EM_CRAYNV2 172 /* Cray Inc. NV2 vector architecture */
#define EM_RX 173 /* Renesas RX family */
-#define EM_METAG 174 /* Imagination Technologies META processor architecture */
+#define EM_METAG 174 /* Imagination Technologies Meta processor architecture */
#define EM_MCST_ELBRUS 175 /* MCST Elbrus general purpose hardware architecture */
#define EM_ECOG16 176 /* Cyan Technology eCOG16 family */
#define EM_CR16 177 /* National Semiconductor CompactRISC 16-bit processor */
--- /dev/null
+/* Meta ELF support for BFD.
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#ifndef _ELF_METAG_H
+#define _ELF_METAG_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types. */
+
+START_RELOC_NUMBERS (elf_metag_reloc_type)
+ RELOC_NUMBER (R_METAG_HIADDR16, 0)
+ RELOC_NUMBER (R_METAG_LOADDR16, 1)
+ RELOC_NUMBER (R_METAG_ADDR32, 2)
+ RELOC_NUMBER (R_METAG_NONE, 3)
+ RELOC_NUMBER (R_METAG_RELBRANCH, 4)
+ RELOC_NUMBER (R_METAG_GETSETOFF, 5)
+
+ /* Backward compatability */
+ RELOC_NUMBER (R_METAG_REG32OP1, 6)
+ RELOC_NUMBER (R_METAG_REG32OP2, 7)
+ RELOC_NUMBER (R_METAG_REG32OP3, 8)
+ RELOC_NUMBER (R_METAG_REG16OP1, 9)
+ RELOC_NUMBER (R_METAG_REG16OP2, 10)
+ RELOC_NUMBER (R_METAG_REG16OP3, 11)
+ RELOC_NUMBER (R_METAG_REG32OP4, 12)
+
+ RELOC_NUMBER (R_METAG_HIOG, 13)
+ RELOC_NUMBER (R_METAG_LOOG, 14)
+
+ RELOC_NUMBER (R_METAG_REL8, 15)
+ RELOC_NUMBER (R_METAG_REL16, 16)
+
+ /* GNU */
+ RELOC_NUMBER (R_METAG_GNU_VTINHERIT,30)
+ RELOC_NUMBER (R_METAG_GNU_VTENTRY, 31)
+
+ /* PIC relocations */
+ RELOC_NUMBER (R_METAG_HI16_GOTOFF, 32)
+ RELOC_NUMBER (R_METAG_LO16_GOTOFF, 33)
+ RELOC_NUMBER (R_METAG_GETSET_GOTOFF,34)
+ RELOC_NUMBER (R_METAG_GETSET_GOT, 35)
+ RELOC_NUMBER (R_METAG_HI16_GOTPC, 36)
+ RELOC_NUMBER (R_METAG_LO16_GOTPC, 37)
+ RELOC_NUMBER (R_METAG_HI16_PLT, 38)
+ RELOC_NUMBER (R_METAG_LO16_PLT, 39)
+ RELOC_NUMBER (R_METAG_RELBRANCH_PLT,40)
+ RELOC_NUMBER (R_METAG_GOTOFF, 41)
+ RELOC_NUMBER (R_METAG_PLT, 42)
+ RELOC_NUMBER (R_METAG_COPY, 43)
+ RELOC_NUMBER (R_METAG_JMP_SLOT, 44)
+ RELOC_NUMBER (R_METAG_RELATIVE, 45)
+ RELOC_NUMBER (R_METAG_GLOB_DAT, 46)
+
+ /* TLS relocations */
+ RELOC_NUMBER (R_METAG_TLS_GD, 47)
+ RELOC_NUMBER (R_METAG_TLS_LDM, 48)
+ RELOC_NUMBER (R_METAG_TLS_LDO_HI16, 49)
+ RELOC_NUMBER (R_METAG_TLS_LDO_LO16, 50)
+ RELOC_NUMBER (R_METAG_TLS_LDO, 51)
+ RELOC_NUMBER (R_METAG_TLS_IE, 52)
+ RELOC_NUMBER (R_METAG_TLS_IENONPIC, 53)
+ RELOC_NUMBER (R_METAG_TLS_IENONPIC_HI16,54)
+ RELOC_NUMBER (R_METAG_TLS_IENONPIC_LO16,55)
+ RELOC_NUMBER (R_METAG_TLS_TPOFF, 56)
+ RELOC_NUMBER (R_METAG_TLS_DTPMOD, 57)
+ RELOC_NUMBER (R_METAG_TLS_DTPOFF, 58)
+ RELOC_NUMBER (R_METAG_TLS_LE, 59)
+ RELOC_NUMBER (R_METAG_TLS_LE_HI16, 60)
+ RELOC_NUMBER (R_METAG_TLS_LE_LO16, 61)
+
+END_RELOC_NUMBERS (R_METAG_MAX)
+
+#endif /* _ELF_METAG_H */
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * metag.h: New file.
+
2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
* cr16.h (make_instruction): Rename to cr16_make_instruction.
--- /dev/null
+/* Imagination Technologies Meta opcode table.
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd.
+
+ This file is part of GDB and GAS.
+
+ GDB and GAS are free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 3, or (at
+ your option) any later version.
+
+ GDB and GAS are distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GDB or GAS; see the file COPYING3. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+enum metag_unit
+{
+ UNIT_CT,
+ UNIT_D0,
+ UNIT_D1,
+ UNIT_A0,
+ UNIT_A1,
+ UNIT_PC,
+ UNIT_RD,
+ UNIT_TR,
+ UNIT_TT,
+ UNIT_FX,
+ UNIT_DT, /* DSP Template Table */
+ UNIT_ACC_D0,
+ UNIT_ACC_D1,
+ UNIT_RAM_D0,
+ UNIT_RAM_D1,
+};
+
+typedef struct
+{
+ const char * name;
+ enum metag_unit unit;
+ unsigned int no;
+} metag_reg;
+
+static const metag_reg metag_regtab[] =
+ {
+ { "TXENABLE", UNIT_CT, 0 },
+ { "CT.0", UNIT_CT, 0 },
+ { "TXMODE", UNIT_CT, 1 },
+ { "CT.1", UNIT_CT, 1 },
+ { "TXSTATUS", UNIT_CT, 2 },
+ { "CT.2", UNIT_CT, 2 },
+ { "TXRPT", UNIT_CT, 3 },
+ { "CT.3", UNIT_CT, 3 },
+ { "TXTIMER", UNIT_CT, 4 },
+ { "CT.4", UNIT_CT, 4 },
+ { "TXL1START", UNIT_CT, 5 },
+ { "CT.5", UNIT_CT, 5 },
+ { "TXL1END", UNIT_CT, 6 },
+ { "CT.6", UNIT_CT, 6 },
+ { "TXL1COUNT", UNIT_CT, 7 },
+ { "CT.7", UNIT_CT, 7 },
+ { "TXL2START", UNIT_CT, 8 },
+ { "CT.8", UNIT_CT, 8 },
+ { "TXL2END", UNIT_CT, 9 },
+ { "CT.9", UNIT_CT, 9 },
+ { "TXL2COUNT", UNIT_CT, 10 },
+ { "CT.10", UNIT_CT, 10 },
+ { "TXBPOBITS", UNIT_CT, 11 },
+ { "CT.11", UNIT_CT, 11 },
+ { "TXMRSIZE", UNIT_CT, 12 },
+ { "CT.12", UNIT_CT, 12 },
+ { "TXTIMERI", UNIT_CT, 13 },
+ { "CT.13", UNIT_CT, 13 },
+ { "TXDRCTRL", UNIT_CT, 14 },
+ { "CT.14", UNIT_CT, 14 },
+ { "TXDRSIZE", UNIT_CT, 15 },
+ { "CT.15", UNIT_CT, 15 },
+ { "TXCATCH0", UNIT_CT, 16 },
+ { "CT.16", UNIT_CT, 16 },
+ { "TXCATCH1", UNIT_CT, 17 },
+ { "CT.17", UNIT_CT, 17 },
+ { "TXCATCH2", UNIT_CT, 18 },
+ { "CT.18", UNIT_CT, 18 },
+ { "TXCATCH3", UNIT_CT, 19 },
+ { "CT.19", UNIT_CT, 19 },
+ { "TXDEFR", UNIT_CT, 20 },
+ { "CT.20", UNIT_CT, 20 },
+ { "TXCPRS", UNIT_CT, 21 },
+ { "CT.21", UNIT_CT, 21 },
+ { "TXCLKCTRL", UNIT_CT, 22 },
+ { "CT.22", UNIT_CT, 22 },
+ { "TXINTERN0", UNIT_CT, 23 },
+ { "TXSTATE", UNIT_CT, 23 },
+ { "CT.23", UNIT_CT, 23 },
+ { "TXAMAREG0", UNIT_CT, 24 },
+ { "CT.24", UNIT_CT, 24 },
+ { "TXAMAREG1", UNIT_CT, 25 },
+ { "CT.25", UNIT_CT, 25 },
+ { "TXAMAREG2", UNIT_CT, 26 },
+ { "CT.26", UNIT_CT, 26 },
+ { "TXAMAREG3", UNIT_CT, 27 },
+ { "CT.27", UNIT_CT, 27 },
+ { "TXDIVTIME", UNIT_CT, 28 },
+ { "CT.28", UNIT_CT, 28 },
+ { "TXPRIVEXT", UNIT_CT, 29 },
+ { "CT.29", UNIT_CT, 29 },
+ { "TXTACTCYC", UNIT_CT, 30 },
+ { "TXACTCYC", UNIT_CT, 30 },
+ { "CT.30", UNIT_CT, 30 },
+ { "TXIDLECYC", UNIT_CT, 31 },
+ { "CT.31", UNIT_CT, 31 },
+
+ { "D0Re0", UNIT_D0, 0 },
+ { "D0.0", UNIT_D0, 0 },
+ { "D0Ar6", UNIT_D0, 1 },
+ { "D0.1", UNIT_D0, 1 },
+ { "D0Ar4", UNIT_D0, 2 },
+ { "D0.2", UNIT_D0, 2 },
+ { "D0Ar2", UNIT_D0, 3 },
+ { "D0.3", UNIT_D0, 3 },
+ { "D0FrT", UNIT_D0, 4 },
+ { "D0.4", UNIT_D0, 4 },
+ { "D0.5", UNIT_D0, 5 },
+ { "D0.6", UNIT_D0, 6 },
+ { "D0.7", UNIT_D0, 7 },
+ { "D0.8", UNIT_D0, 8 },
+ { "D0.9", UNIT_D0, 9 },
+ { "D0.10", UNIT_D0, 10 },
+ { "D0.11", UNIT_D0, 11 },
+ { "D0.12", UNIT_D0, 12 },
+ { "D0.13", UNIT_D0, 13 },
+ { "D0.14", UNIT_D0, 14 },
+ { "D0.15", UNIT_D0, 15 },
+ { "D0.16", UNIT_D0, 16 },
+ { "D0.17", UNIT_D0, 17 },
+ { "D0.18", UNIT_D0, 18 },
+ { "D0.19", UNIT_D0, 19 },
+ { "D0.20", UNIT_D0, 20 },
+ { "D0.21", UNIT_D0, 21 },
+ { "D0.22", UNIT_D0, 22 },
+ { "D0.23", UNIT_D0, 23 },
+ { "D0.24", UNIT_D0, 24 },
+ { "D0.25", UNIT_D0, 25 },
+ { "D0.26", UNIT_D0, 26 },
+ { "D0.27", UNIT_D0, 27 },
+ { "D0.28", UNIT_D0, 28 },
+ { "D0.29", UNIT_D0, 29 },
+ { "D0.30", UNIT_D0, 30 },
+ { "D0.31", UNIT_D0, 31 },
+
+ { "D1Re0", UNIT_D1, 0 },
+ { "D1.0", UNIT_D1, 0 },
+ { "D1Ar5", UNIT_D1, 1 },
+ { "D1.1", UNIT_D1, 1 },
+ { "D1Ar3", UNIT_D1, 2 },
+ { "D1.2", UNIT_D1, 2 },
+ { "D1Ar1", UNIT_D1, 3 },
+ { "D1.3", UNIT_D1, 3 },
+ { "D1RtP", UNIT_D1, 4 },
+ { "D1.4", UNIT_D1, 4 },
+ { "D1.5", UNIT_D1, 5 },
+ { "D1.6", UNIT_D1, 6 },
+ { "D1.7", UNIT_D1, 7 },
+ { "D1.8", UNIT_D1, 8 },
+ { "D1.9", UNIT_D1, 9 },
+ { "D1.10", UNIT_D1, 10 },
+ { "D1.11", UNIT_D1, 11 },
+ { "D1.12", UNIT_D1, 12 },
+ { "D1.13", UNIT_D1, 13 },
+ { "D1.14", UNIT_D1, 14 },
+ { "D1.15", UNIT_D1, 15 },
+ { "D1.16", UNIT_D1, 16 },
+ { "D1.17", UNIT_D1, 17 },
+ { "D1.18", UNIT_D1, 18 },
+ { "D1.19", UNIT_D1, 19 },
+ { "D1.20", UNIT_D1, 20 },
+ { "D1.21", UNIT_D1, 21 },
+ { "D1.22", UNIT_D1, 22 },
+ { "D1.23", UNIT_D1, 23 },
+ { "D1.24", UNIT_D1, 24 },
+ { "D1.25", UNIT_D1, 25 },
+ { "D1.26", UNIT_D1, 26 },
+ { "D1.27", UNIT_D1, 27 },
+ { "D1.28", UNIT_D1, 28 },
+ { "D1.29", UNIT_D1, 29 },
+ { "D1.30", UNIT_D1, 30 },
+ { "D1.31", UNIT_D1, 31 },
+
+ { "A0StP", UNIT_A0, 0 },
+ { "A0.0", UNIT_A0, 0 },
+ { "A0FrP", UNIT_A0, 1 },
+ { "A0.1", UNIT_A0, 1 },
+ { "A0.2", UNIT_A0, 2 },
+ { "A0.3", UNIT_A0, 3 },
+ { "A0.4", UNIT_A0, 4 },
+ { "A0.5", UNIT_A0, 5 },
+ { "A0.6", UNIT_A0, 6 },
+ { "A0.7", UNIT_A0, 7 },
+ { "A0.8", UNIT_A0, 8 },
+ { "A0.9", UNIT_A0, 9 },
+ { "A0.10", UNIT_A0, 10 },
+ { "A0.11", UNIT_A0, 11 },
+ { "A0.12", UNIT_A0, 12 },
+ { "A0.13", UNIT_A0, 13 },
+ { "A0.14", UNIT_A0, 14 },
+ { "A0.15", UNIT_A0, 15 },
+ { "CPC0", UNIT_A0, 16 },
+
+ { "A1GbP", UNIT_A1, 0 },
+ { "A1.0", UNIT_A1, 0 },
+ { "A1LbP", UNIT_A1, 1 },
+ { "A1.1", UNIT_A1, 1 },
+ { "A1.2", UNIT_A1, 2 },
+ { "A1.3", UNIT_A1, 3 },
+ { "A1.4", UNIT_A1, 4 },
+ { "A1.5", UNIT_A1, 5 },
+ { "A1.6", UNIT_A1, 6 },
+ { "A1.7", UNIT_A1, 7 },
+ { "A1.8", UNIT_A1, 8 },
+ { "A1.9", UNIT_A1, 9 },
+ { "A1.10", UNIT_A1, 10 },
+ { "A1.11", UNIT_A1, 11 },
+ { "A1.12", UNIT_A1, 12 },
+ { "A1.13", UNIT_A1, 13 },
+ { "A1.14", UNIT_A1, 14 },
+ { "A1.15", UNIT_A1, 15 },
+ { "CPC1", UNIT_A1, 16 },
+
+ { "PC", UNIT_PC, 0 },
+ { "PCX", UNIT_PC, 1 },
+
+ { "RD", UNIT_RD, 0 },
+ { "RA", UNIT_RD, 16 },
+ { "RD", UNIT_RD, 16 },
+ { "RAPF", UNIT_RD, 17 },
+ { "RAM8X32", UNIT_RD, 22 },
+ { "RAM8X", UNIT_RD, 23 },
+ { "RABZ", UNIT_RD, 24 },
+ { "RAWZ", UNIT_RD, 25 },
+ { "RADZ", UNIT_RD, 26 },
+ { "RABX", UNIT_RD, 28 },
+ { "RAWX", UNIT_RD, 29 },
+ { "RADX", UNIT_RD, 30 },
+ { "RAMX", UNIT_RD, 31 },
+ { "RAM16X", UNIT_RD, 31 },
+
+ { "TXSTAT", UNIT_TR, 0 },
+ { "TR.0", UNIT_TR, 0 },
+ { "TXMASK", UNIT_TR, 1 },
+ { "TR.1", UNIT_TR, 1 },
+ { "TXSTATI", UNIT_TR, 2 },
+ { "TR.2", UNIT_TR, 2 },
+ { "TXMASKI", UNIT_TR, 3 },
+ { "TR.3", UNIT_TR, 3 },
+ { "TXPOLL", UNIT_TR, 4 },
+ { "TR.4", UNIT_TR, 4 },
+ { "TXGPIOI", UNIT_TR, 5 },
+ { "TR.5", UNIT_TR, 5 },
+ { "TXPOLLI", UNIT_TR, 6 },
+ { "TR.6", UNIT_TR, 6 },
+ { "TXGPIOO", UNIT_TR, 7 },
+ { "TR.7", UNIT_TR, 7 },
+
+ { "TTEXEC", UNIT_TT, 0 },
+ { "TT.0", UNIT_TT, 0 },
+ { "TTCTRL", UNIT_TT, 1 },
+ { "TT.1", UNIT_TT, 1 },
+ { "TTMARK", UNIT_TT, 2 },
+ { "TT.2", UNIT_TT, 2 },
+ { "TTREC", UNIT_TT, 3 },
+ { "TT.3", UNIT_TT, 3 },
+ { "GTEXEC", UNIT_TT, 4 },
+ { "TT.4", UNIT_TT, 4 },
+
+ { "FX.0", UNIT_FX, 0 },
+ { "FX.1", UNIT_FX, 1 },
+ { "FX.2", UNIT_FX, 2 },
+ { "FX.3", UNIT_FX, 3 },
+ { "FX.4", UNIT_FX, 4 },
+ { "FX.5", UNIT_FX, 5 },
+ { "FX.6", UNIT_FX, 6 },
+ { "FX.7", UNIT_FX, 7 },
+ { "FX.8", UNIT_FX, 8 },
+ { "FX.9", UNIT_FX, 9 },
+ { "FX.10", UNIT_FX, 10 },
+ { "FX.11", UNIT_FX, 11 },
+ { "FX.12", UNIT_FX, 12 },
+ { "FX.13", UNIT_FX, 13 },
+ { "FX.14", UNIT_FX, 14 },
+ { "FX.15", UNIT_FX, 15 },
+ };
+
+static const metag_reg metag_dsp_regtab[] =
+ {
+ { "D0AR.0", UNIT_RAM_D0, 0 },
+ { "D0AR.1", UNIT_RAM_D0, 1 },
+ { "D0AW.0", UNIT_RAM_D0, 2 },
+ { "D0AW.1", UNIT_RAM_D0, 3 },
+ { "D0BR.0", UNIT_RAM_D0, 4 },
+ { "D0BR.1", UNIT_RAM_D0, 5 },
+ { "D0BW.0", UNIT_RAM_D0, 6 },
+ { "D0BW.1", UNIT_RAM_D0, 7 },
+ { "D0ARI.0", UNIT_RAM_D0, 8 },
+ { "D0ARI.1", UNIT_RAM_D0, 9 },
+ { "D0AWI.0", UNIT_RAM_D0, 10 },
+ { "D0AWI.1", UNIT_RAM_D0, 11 },
+ { "D0BRI.0", UNIT_RAM_D0, 12 },
+ { "D0BRI.1", UNIT_RAM_D0, 13 },
+ { "D0BWI.0", UNIT_RAM_D0, 14 },
+ { "D0BWI.1", UNIT_RAM_D0, 15 },
+
+ { "AC0.0", UNIT_ACC_D0, 16 },
+ { "AC0.1", UNIT_ACC_D0, 17 },
+ { "AC0.2", UNIT_ACC_D0, 18 },
+ { "AC0.3", UNIT_ACC_D0, 19 },
+
+ { "D1AR.0", UNIT_RAM_D1, 0 },
+ { "D1AR.1", UNIT_RAM_D1, 1 },
+ { "D1AW.0", UNIT_RAM_D1, 2 },
+ { "D1AW.1", UNIT_RAM_D1, 3 },
+ { "D1BR.0", UNIT_RAM_D1, 4 },
+ { "D1BR.1", UNIT_RAM_D1, 5 },
+ { "D1BW.0", UNIT_RAM_D1, 6 },
+ { "D1BW.1", UNIT_RAM_D1, 7 },
+ { "D1ARI.0", UNIT_RAM_D1, 8 },
+ { "D1ARI.1", UNIT_RAM_D1, 9 },
+ { "D1AWI.0", UNIT_RAM_D1, 10 },
+ { "D1AWI.1", UNIT_RAM_D1, 11 },
+ { "D1BRI.0", UNIT_RAM_D1, 12 },
+ { "D1BRI.1", UNIT_RAM_D1, 13 },
+ { "D1BWI.0", UNIT_RAM_D1, 14 },
+ { "D1BWI.1", UNIT_RAM_D1, 15 },
+
+ { "AC1.0", UNIT_ACC_D1, 16 },
+ { "AC1.1", UNIT_ACC_D1, 17 },
+ { "AC1.2", UNIT_ACC_D1, 18 },
+ { "AC1.3", UNIT_ACC_D1, 19 },
+
+ { "T0", UNIT_DT, 0 },
+ { "T1", UNIT_DT, 1 },
+ { "T2", UNIT_DT, 2 },
+ { "T3", UNIT_DT, 3 },
+ { "T4", UNIT_DT, 4 },
+ { "T5", UNIT_DT, 5 },
+ { "T6", UNIT_DT, 6 },
+ { "T7", UNIT_DT, 7 },
+ { "T8", UNIT_DT, 8 },
+ { "T9", UNIT_DT, 9 },
+ { "TA", UNIT_DT, 10 },
+ { "TB", UNIT_DT, 11 },
+ { "TC", UNIT_DT, 12 },
+ { "TD", UNIT_DT, 13 },
+ { "TE", UNIT_DT, 14 },
+ { "TF", UNIT_DT, 15 },
+ };
+
+/* This table differs from 'metag_dsp_regtab' in that the number
+ fields in this table are suitable for insertion into DSPRAM
+ template definition instruction encodings.
+
+ The table is indexed by "load". The main benefit of this is that we
+ can implicitly check that the correct DSPRAM register has been used
+ when parsing, e.g. the read pointer only appears in the load table
+ and the write pointer only exists in the store table.
+
+ The ordering of the table entries might look a bit weird but it is
+ based on matching the longest register string. */
+static const metag_reg metag_dsp_tmpl_regtab[2][56] =
+ {
+ {
+ { "D0AW.0+D0AWI.0++", UNIT_RAM_D0, 18 },
+ { "D0AW.0+D0AWI.0", UNIT_RAM_D0, 18 },
+ { "D0AW.0+D0AWI.1++", UNIT_RAM_D0, 19 },
+ { "D0AW.0+D0AWI.1", UNIT_RAM_D0, 19 },
+ { "D0AW.0++", UNIT_RAM_D0, 17 },
+ { "D0AW.0", UNIT_RAM_D0, 16 },
+ { "D0AWI.0", UNIT_RAM_D0, 18 },
+ { "D0AWI.1", UNIT_RAM_D0, 19 },
+ { "D0AW.1+D0AWI.0++", UNIT_RAM_D0, 22 },
+ { "D0AW.1+D0AWI.0", UNIT_RAM_D0, 22 },
+ { "D0AW.1+D0AWI.1++", UNIT_RAM_D0, 23 },
+ { "D0AW.1+D0AWI.1", UNIT_RAM_D0, 23 },
+ { "D0AW.1++", UNIT_RAM_D0, 21 },
+ { "D0AW.1", UNIT_RAM_D0, 20 },
+ { "D0BW.0+D0BWI.0++", UNIT_RAM_D0, 26 },
+ { "D0BW.0+D0BWI.0", UNIT_RAM_D0, 26 },
+ { "D0BW.0+D0BWI.1++", UNIT_RAM_D0, 27 },
+ { "D0BW.0+D0BWI.1", UNIT_RAM_D0, 27 },
+ { "D0BW.0++", UNIT_RAM_D0, 25 },
+ { "D0BW.0", UNIT_RAM_D0, 24 },
+ { "D0BWI.0", UNIT_RAM_D0, 18 },
+ { "D0BWI.1", UNIT_RAM_D0, 19 },
+ { "D0BW.1+D0BWI.0++", UNIT_RAM_D0, 30 },
+ { "D0BW.1+D0BWI.0", UNIT_RAM_D0, 30 },
+ { "D0BW.1+D0BWI.1++", UNIT_RAM_D0, 31 },
+ { "D0BW.1+D0BWI.1", UNIT_RAM_D0, 31 },
+ { "D0BW.1++", UNIT_RAM_D0, 29 },
+ { "D0BW.1", UNIT_RAM_D0, 28 },
+
+ { "D1AW.0+D1AWI.0++", UNIT_RAM_D1, 18 },
+ { "D1AW.0+D1AWI.0", UNIT_RAM_D1, 18 },
+ { "D1AW.0+D1AWI.1++", UNIT_RAM_D1, 19 },
+ { "D1AW.0+D1AWI.1", UNIT_RAM_D1, 19 },
+ { "D1AW.0++", UNIT_RAM_D1, 17 },
+ { "D1AW.0", UNIT_RAM_D1, 16 },
+ { "D1AWI.0", UNIT_RAM_D1, 18 },
+ { "D1AWI.1", UNIT_RAM_D1, 19 },
+ { "D1AW.1+D1AWI.0++", UNIT_RAM_D1, 22 },
+ { "D1AW.1+D1AWI.0", UNIT_RAM_D1, 22 },
+ { "D1AW.1+D1AWI.1++", UNIT_RAM_D1, 23 },
+ { "D1AW.1+D1AWI.1", UNIT_RAM_D1, 23 },
+ { "D1AW.1++", UNIT_RAM_D1, 21 },
+ { "D1AW.1", UNIT_RAM_D1, 20 },
+ { "D1BW.0+D1BWI.0++", UNIT_RAM_D1, 26 },
+ { "D1BW.0+D1BWI.0", UNIT_RAM_D1, 26 },
+ { "D1BW.0+D1BWI.1++", UNIT_RAM_D1, 27 },
+ { "D1BW.0+D1BWI.1", UNIT_RAM_D1, 27 },
+ { "D1BW.0++", UNIT_RAM_D1, 25 },
+ { "D1BW.0", UNIT_RAM_D1, 24 },
+ { "D1BWI.0", UNIT_RAM_D1, 18 },
+ { "D1BWI.1", UNIT_RAM_D1, 19 },
+ { "D1BW.1+D1BWI.0++", UNIT_RAM_D1, 30 },
+ { "D1BW.1+D1BWI.0", UNIT_RAM_D1, 30 },
+ { "D1BW.1+D1BWI.1++", UNIT_RAM_D1, 31 },
+ { "D1BW.1+D1BWI.1", UNIT_RAM_D1, 31 },
+ { "D1BW.1++", UNIT_RAM_D1, 29 },
+ { "D1BW.1", UNIT_RAM_D1, 28 },
+ },
+
+ {
+ { "D0AR.0+D0ARI.0++", UNIT_RAM_D0, 18 },
+ { "D0AR.0+D0ARI.0", UNIT_RAM_D0, 18 },
+ { "D0AR.0+D0ARI.1++", UNIT_RAM_D0, 19 },
+ { "D0AR.0+D0ARI.1", UNIT_RAM_D0, 19 },
+ { "D0AR.0++", UNIT_RAM_D0, 17 },
+ { "D0AR.0", UNIT_RAM_D0, 16 },
+ { "D0ARI.0", UNIT_RAM_D0, 18 },
+ { "D0ARI.1", UNIT_RAM_D0, 19 },
+ { "D0AR.1+D0ARI.0++", UNIT_RAM_D0, 22 },
+ { "D0AR.1+D0ARI.0", UNIT_RAM_D0, 22 },
+ { "D0AR.1+D0ARI.1++", UNIT_RAM_D0, 23 },
+ { "D0AR.1+D0ARI.1", UNIT_RAM_D0, 23 },
+ { "D0AR.1++", UNIT_RAM_D0, 21 },
+ { "D0AR.1", UNIT_RAM_D0, 20 },
+ { "D0BR.0+D0BRI.0++", UNIT_RAM_D0, 26 },
+ { "D0BR.0+D0BRI.0", UNIT_RAM_D0, 26 },
+ { "D0BR.0+D0BRI.1++", UNIT_RAM_D0, 27 },
+ { "D0BR.0+D0BRI.1", UNIT_RAM_D0, 27 },
+ { "D0BR.0++", UNIT_RAM_D0, 25 },
+ { "D0BR.0", UNIT_RAM_D0, 24 },
+ { "D0BRI.0", UNIT_RAM_D0, 18 },
+ { "D0BRI.1", UNIT_RAM_D0, 19 },
+ { "D0BR.1+D0BRI.0++", UNIT_RAM_D0, 30 },
+ { "D0BR.1+D0BRI.0", UNIT_RAM_D0, 30 },
+ { "D0BR.1+D0BRI.1++", UNIT_RAM_D0, 31 },
+ { "D0BR.1+D0BRI.1", UNIT_RAM_D0, 31 },
+ { "D0BR.1++", UNIT_RAM_D0, 29 },
+ { "D0BR.1", UNIT_RAM_D0, 28 },
+
+ { "D1AR.0+D1ARI.0++", UNIT_RAM_D1, 18 },
+ { "D1AR.0+D1ARI.0", UNIT_RAM_D1, 18 },
+ { "D1AR.0+D1ARI.1++", UNIT_RAM_D1, 19 },
+ { "D1AR.0+D1ARI.1", UNIT_RAM_D1, 19 },
+ { "D1AR.0++", UNIT_RAM_D1, 17 },
+ { "D1AR.0", UNIT_RAM_D1, 16 },
+ { "D1ARI.0", UNIT_RAM_D1, 18 },
+ { "D1ARI.1", UNIT_RAM_D1, 19 },
+ { "D1AR.1+D1ARI.0++", UNIT_RAM_D1, 22 },
+ { "D1AR.1+D1ARI.0", UNIT_RAM_D1, 22 },
+ { "D1AR.1+D1ARI.1++", UNIT_RAM_D1, 23 },
+ { "D1AR.1+D1ARI.1", UNIT_RAM_D1, 23 },
+ { "D1AR.1++", UNIT_RAM_D1, 21 },
+ { "D1AR.1", UNIT_RAM_D1, 20 },
+ { "D1BR.0+D1BRI.0++", UNIT_RAM_D1, 26 },
+ { "D1BR.0+D1BRI.0", UNIT_RAM_D1, 26 },
+ { "D1BR.0+D1BRI.1++", UNIT_RAM_D1, 27 },
+ { "D1BR.0+D1BRI.1", UNIT_RAM_D1, 27 },
+ { "D1BR.0++", UNIT_RAM_D1, 25 },
+ { "D1BR.0", UNIT_RAM_D1, 24 },
+ { "D1BR.1+D1BRI.0++", UNIT_RAM_D1, 30 },
+ { "D1BR.1+D1BRI.0", UNIT_RAM_D1, 30 },
+ { "D1BR.1+D1BRI.1++", UNIT_RAM_D1, 31 },
+ { "D1BR.1+D1BRI.1", UNIT_RAM_D1, 31 },
+ { "D1BR.1++", UNIT_RAM_D1, 29 },
+ { "D1BR.1", UNIT_RAM_D1, 28 },
+ { "D1BRI.0", UNIT_RAM_D1, 18 },
+ { "D1BRI.1", UNIT_RAM_D1, 19 },
+ },
+ };
+
+typedef struct
+{
+ const char * name;
+ unsigned int part;
+} metag_acf;
+
+static const metag_acf metag_acftab[] =
+ {
+ { "ACF.0", 0},
+ { "ACF.1", 1},
+ { "ACF.2", 2},
+ { "ACF.3", 3},
+ };
+
+enum insn_encoding
+{
+ ENC_NONE,
+ ENC_MOV_U2U,
+ ENC_MOV_PORT,
+ ENC_MMOV,
+ ENC_MDRD,
+ ENC_MOVL_TTREC,
+ ENC_GET_SET,
+ ENC_GET_SET_EXT,
+ ENC_MGET_MSET,
+ ENC_COND_SET,
+ ENC_XFR,
+ ENC_MOV_CT,
+ ENC_SWAP,
+ ENC_JUMP,
+ ENC_CALLR,
+ ENC_ALU,
+ ENC_SHIFT,
+ ENC_MIN_MAX,
+ ENC_BITOP,
+ ENC_CMP,
+ ENC_BRANCH,
+ ENC_KICK,
+ ENC_SWITCH,
+ ENC_CACHER,
+ ENC_CACHEW,
+ ENC_ICACHE,
+ ENC_LNKGET,
+ ENC_FMOV,
+ ENC_FMMOV,
+ ENC_FMOV_DATA,
+ ENC_FMOV_I,
+ ENC_FPACK,
+ ENC_FSWAP,
+ ENC_FCMP,
+ ENC_FMINMAX,
+ ENC_FCONV,
+ ENC_FCONVX,
+ ENC_FBARITH,
+ ENC_FEARITH,
+ ENC_FREC,
+ ENC_FSIMD,
+ ENC_FGET_SET_ACF,
+ ENC_DGET_SET,
+ ENC_DTEMPLATE,
+ ENC_DALU,
+ ENC_MAX,
+};
+
+enum insn_type
+{
+ INSN_GP,
+ INSN_FPU,
+ INSN_DSP,
+ INSN_DSP_FPU,
+};
+
+typedef struct
+{
+ const char *name;
+
+ unsigned int core_flags;
+#define CoreMeta11 0x1 /* The earliest Meta core we support */
+#define CoreMeta12 0x2
+#define CoreMeta21 0x4
+
+#define FpuMeta21 0x21
+
+#define DspMeta21 0x100
+
+ unsigned int meta_opcode;
+ unsigned int meta_mask;
+
+ enum insn_type insn_type;
+
+ enum insn_encoding encoding;
+
+#define DSP_ARGS_1 0x0000001 /* De.r,Dx.r,De.r (3 register operands) */
+#define DSP_ARGS_ACC2 0x0000002 /* Accumulator source operand 2 */
+#define DSP_ARGS_QR 0x0000004 /* QUICKRoT */
+#define DSP_ARGS_XACC 0x0000008 /* Cross-unit accumulator op */
+#define DSP_ARGS_DACC 0x0000010 /* Target accumulator as destination */
+#define DSP_ARGS_SRD 0x0000020 /* Source the RD port */
+#define DSP_ARGS_2 0x0000040 /* De.r,Dx.r (2 register operands) */
+#define DSP_ARGS_DSP_SRC1 0x0000080 /* Source a DSP register */
+#define DSP_ARGS_DSP_SRC2 0x0000100 /* Source a DSP register */
+#define DSP_ARGS_IMM 0x0000200 /* Immediate value for src 2 */
+#define DSP_ARGS_SPLIT8 0x0000400 /* Data unit split 8 operations */
+#define DSP_ARGS_12 0x0000800 /* De.r,Dx.r */
+#define DSP_ARGS_13 0x0001000 /* Dx.r,Rx.r */
+#define DSP_ARGS_14 0x0002000 /* DSPe.r,Dx.r */
+#define DSP_ARGS_15 0x0004000 /* DSPx.r,#I16 */
+#define DSP_ARGS_16 0x0008000 /* De.r,DSPx.r */
+#define DSP_ARGS_17 0x0010000 /* De.r|ACe.r,Dx.r,Rx.r|RD */
+#define DSP_ARGS_18 0x0020000 /* De.r,Dx.r|ACx.r */
+#define DSP_ARGS_20 0x0080000 /* De.r,Dx.r|ACx.r,De.r */
+#define DSP_ARGS_21 0x0100000 /* De.r,Dx.r|ACx.r,#I5 */
+#define DSP_ARGS_22 0x0200000 /* De.r,Dx.r|ACx.r,De.r|#I5 */
+#define DSP_ARGS_23 0x0400000 /* Ux.r,Dx.r|ACx.r,De.r|#I5 */
+#define GP_ARGS_QR 0x0000001 /* QUICKRoT */
+ unsigned int arg_type;
+} insn_template;
+
+enum major_opcode
+{
+ OPC_ADD,
+ OPC_SUB,
+ OPC_AND,
+ OPC_OR,
+ OPC_XOR,
+ OPC_SHIFT,
+ OPC_MUL,
+ OPC_CMP,
+ OPC_ADDR,
+ OPC_9,
+ OPC_MISC,
+ OPC_SET,
+ OPC_GET,
+ OPC_XFR,
+ OPC_CPR,
+ OPC_FPU,
+};
+
+#define GET_EXT_MINOR 0x7
+#define MOV_EXT_MINOR 0x6
+#define MOVL_MINOR 0x2
+
+#define MAJOR_OPCODE(opcode) (((opcode) >> 28) & 0xf)
+#define MINOR_OPCODE(opcode) (((opcode) >> 24) & 0xf)
+
+enum cond_code
+{
+ COND_A,
+ COND_EQ,
+ COND_NE,
+ COND_CS,
+ COND_CC,
+ COND_MI,
+ COND_PL,
+ COND_VS,
+ COND_VC,
+ COND_HI,
+ COND_LS,
+ COND_GE,
+ COND_LT,
+ COND_GT,
+ COND_LE,
+ COND_NV,
+};
+
+enum scond_code
+{
+ SCOND_A,
+ SCOND_LEQ,
+ SCOND_LNE,
+ SCOND_LLO,
+ SCOND_LHS,
+ SCOND_HEQ,
+ SCOND_HNE,
+ SCOND_HLO,
+ SCOND_HHS,
+ SCOND_LGR,
+ SCOND_LLE,
+ SCOND_HGR,
+ SCOND_HLE,
+ SCOND_EEQ,
+ SCOND_ELO,
+ SCOND_NV,
+};
+
+typedef struct
+{
+ const char *name;
+ enum scond_code code;
+} split_condition;
+
+static const split_condition metag_scondtab[] =
+ {
+ { "LEQ", SCOND_LEQ },
+ { "LEZ", SCOND_LEQ },
+ { "LNE", SCOND_LNE },
+ { "LNZ", SCOND_LNE },
+ { "LLO", SCOND_LLO },
+ { "LCS", SCOND_LLO },
+ { "LHS", SCOND_LHS },
+ { "LCC", SCOND_LHS },
+ { "HEQ", SCOND_HEQ },
+ { "HEZ", SCOND_HEQ },
+ { "HNE", SCOND_HNE },
+ { "HNZ", SCOND_HNE },
+ { "HLO", SCOND_HLO },
+ { "HCS", SCOND_HLO },
+ { "HHS", SCOND_HHS },
+ { "HCC", SCOND_HHS },
+ { "LGR", SCOND_LGR },
+ { "LHI", SCOND_LGR },
+ { "LLE", SCOND_LLE },
+ { "LLS", SCOND_LLE },
+ { "HGR", SCOND_HGR },
+ { "HHI", SCOND_HGR },
+ { "HLE", SCOND_HLE },
+ { "HLS", SCOND_HLE },
+ { "EEQ", SCOND_EEQ },
+ { "EEZ", SCOND_EEQ },
+ { "ELO", SCOND_ELO },
+ { "ECS", SCOND_ELO },
+ };
+
+static const split_condition metag_dsp_scondtab[] =
+ {
+ { "LEQ", SCOND_LEQ },
+ { "LEZ", SCOND_LEQ },
+ { "LNE", SCOND_LNE },
+ { "LNZ", SCOND_LNE },
+ { "LCS", SCOND_LLO },
+ { "LLO", SCOND_LLO },
+ { "LCC", SCOND_LHS },
+ { "LHS", SCOND_LHS },
+ { "HEQ", SCOND_HEQ },
+ { "HEZ", SCOND_HEQ },
+ { "HNE", SCOND_HNE },
+ { "HNZ", SCOND_HNE },
+ { "HCS", SCOND_HLO },
+ { "HLO", SCOND_HLO },
+ { "HCC", SCOND_HHS },
+ { "HHS", SCOND_HHS },
+ { "LHI", SCOND_LGR },
+ { "LGR", SCOND_LGR },
+ { "LLS", SCOND_LLE },
+ { "LLE", SCOND_LLE },
+ { "HHI", SCOND_HGR },
+ { "HGR", SCOND_HGR },
+ { "HLS", SCOND_HLE },
+ { "HLE", SCOND_HLE },
+ { "EEQ", SCOND_EEQ },
+ { "EEZ", SCOND_EEQ },
+ { "ECS", SCOND_ELO },
+ { "ELO", SCOND_ELO },
+ };
+
+static const split_condition metag_fpu_scondtab[] =
+ {
+ { "LEQ", SCOND_LEQ },
+ { "LEZ", SCOND_LEQ },
+ { "LNE", SCOND_LNE },
+ { "LNZ", SCOND_LNE },
+ { "LLO", SCOND_LLO },
+ { "LCS", SCOND_LLO },
+ { "LHS", SCOND_LHS },
+ { "LCC", SCOND_LHS },
+ { "HEQ", SCOND_HEQ },
+ { "HEZ", SCOND_HEQ },
+ { "HNE", SCOND_HNE },
+ { "HNZ", SCOND_HNE },
+ { "HLO", SCOND_HLO },
+ { "HCS", SCOND_HLO },
+ { "HHS", SCOND_HHS },
+ { "HCC", SCOND_HHS },
+ { "LGR", SCOND_LGR },
+ { "LHI", SCOND_LGR },
+ { "LLE", SCOND_LLE },
+ { "LLS", SCOND_LLE },
+ { "HGR", SCOND_HGR },
+ { "HHI", SCOND_HGR },
+ { "HLE", SCOND_HLE },
+ { "HLS", SCOND_HLE },
+ { "EEQ", SCOND_EEQ },
+ { "EEZ", SCOND_EEQ },
+ { "ELO", SCOND_ELO },
+ { "ECS", SCOND_ELO },
+ };
+
+enum fcond_code
+{
+ FCOND_A,
+ FCOND_FEQ,
+ FCOND_UNE,
+ FCOND_FLT,
+ FCOND_UGE,
+
+ FCOND_UVS = 7,
+ FCOND_FVC,
+ FCOND_UGT,
+ FCOND_FLE,
+ FCOND_FGE,
+ FCOND_ULT,
+ FCOND_FGT,
+ FCOND_ULE,
+ FCOND_NV,
+};
+
+#define COND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode, \
+ meta_mask, insn_type, encoding, args) \
+ { mnemonic suffix, flags, meta_opcode, meta_mask, \
+ insn_type, encoding, args }, \
+ { mnemonic "A" suffix, flags, meta_opcode, meta_mask, \
+ insn_type, encoding, args }, \
+ { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "FEQ" suffix, flags, meta_opcode | \
+ (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FZ" suffix, flags, meta_opcode | \
+ (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UNE" suffix, flags, meta_opcode | \
+ (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UNZ" suffix, flags, meta_opcode | \
+ (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FLT" suffix, flags, meta_opcode | \
+ (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FLO" suffix, flags, meta_opcode | \
+ (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UGE" suffix, flags, meta_opcode | \
+ (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UHS" suffix, flags, meta_opcode | \
+ (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UVS" suffix, flags, meta_opcode | \
+ (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FVC" suffix, flags, meta_opcode | \
+ (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UGT" suffix, flags, meta_opcode | \
+ (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UHI" suffix, flags, meta_opcode | \
+ (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FLE" suffix, flags, meta_opcode | \
+ (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FGE" suffix, flags, meta_opcode | \
+ (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FHS" suffix, flags, meta_opcode | \
+ (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "ULT" suffix, flags, meta_opcode | \
+ (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "ULO" suffix, flags, meta_opcode | \
+ (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FGT" suffix, flags, meta_opcode | \
+ (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FHI" suffix, flags, meta_opcode | \
+ (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "ULE" suffix, flags, meta_opcode | \
+ (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "NV" suffix, flags, meta_opcode | \
+ (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args }
+
+#define FCOND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode, \
+ meta_mask, insn_type, encoding, args) \
+ { mnemonic suffix, flags, meta_opcode, meta_mask, \
+ insn_type, encoding, args }, \
+ { mnemonic "A" suffix, flags, meta_opcode, meta_mask, \
+ insn_type, encoding, args }, \
+ { mnemonic "FEQ" suffix, flags, meta_opcode | \
+ (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FZ" suffix, flags, meta_opcode | \
+ (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UNE" suffix, flags, meta_opcode | \
+ (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UNZ" suffix, flags, meta_opcode | \
+ (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FLO" suffix, flags, meta_opcode | \
+ (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FLT" suffix, flags, meta_opcode | \
+ (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UHS" suffix, flags, meta_opcode | \
+ (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UGE" suffix, flags, meta_opcode | \
+ (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UVS" suffix, flags, meta_opcode | \
+ (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FVC" suffix, flags, meta_opcode | \
+ (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UHI" suffix, flags, meta_opcode | \
+ (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "UGT" suffix, flags, meta_opcode | \
+ (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FLE" suffix, flags, meta_opcode | \
+ (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FGE" suffix, flags, meta_opcode | \
+ (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FHS" suffix, flags, meta_opcode | \
+ (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "ULT" suffix, flags, meta_opcode | \
+ (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "ULO" suffix, flags, meta_opcode | \
+ (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FGT" suffix, flags, meta_opcode | \
+ (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "FHI" suffix, flags, meta_opcode | \
+ (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "ULE" suffix, flags, meta_opcode | \
+ (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "NV" suffix, flags, meta_opcode | \
+ (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+ { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \
+ meta_mask, insn_type, encoding, args }, \
+ { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \
+ meta_mask, insn_type, encoding, args }
+
+#define TEMPLATE_INSN(flags, meta_opcode, meta_mask, insn_type) \
+ { "T0", flags, meta_opcode | 0x0, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T1", flags, meta_opcode | 0x1, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T2", flags, meta_opcode | 0x2, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T3", flags, meta_opcode | 0x3, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T4", flags, meta_opcode | 0x4, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T5", flags, meta_opcode | 0x5, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T6", flags, meta_opcode | 0x6, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T7", flags, meta_opcode | 0x7, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T8", flags, meta_opcode | 0x8, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "T9", flags, meta_opcode | 0x9, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "TA", flags, meta_opcode | 0xa, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "TB", flags, meta_opcode | 0xb, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "TC", flags, meta_opcode | 0xc, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "TD", flags, meta_opcode | 0xd, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "TE", flags, meta_opcode | 0xe, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+ { "TF", flags, meta_opcode | 0xf, meta_mask, insn_type, ENC_DTEMPLATE, 0 }
+
+
+/* Unimplemented GP instructions:
+ CPR - coprocessor read
+ CPW - coprocessor write
+ MORT - morton order operation
+ VPACK, VADD, VSUB - vector instructions
+
+ The order of the entries in this table is extremely important. DO
+ NOT modify it unless you know what you're doing. If you do modify
+ it, be sure to run the entire testsuite to make sure you haven't
+ caused a regression. */
+
+static const insn_template metag_optab[] =
+ {
+ /* Port-to-unit MOV */
+ COND_INSN ("MOVB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa1800000, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
+ COND_INSN ("MOVW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa1800001, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
+ COND_INSN ("MOVD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa1800200, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
+ COND_INSN ("MOVL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa2800000, 0xfff8019f, INSN_GP, ENC_MOV_PORT, 0),
+
+ /* Read pipeline prime/drain */
+ { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xca000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 },
+ { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xcb000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 },
+ { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xcc000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 },
+ { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xcd000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 },
+
+ /* Read pipeline flush */
+ { "MDRD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xcc000002, 0xffffc07f, INSN_GP, ENC_MDRD, 0 },
+
+ /* Unit-to-TTREC MOVL */
+ COND_INSN ("MOVL", "", 1, CoreMeta12|CoreMeta21,
+ 0xa2002001, 0xff003e7f, INSN_GP, ENC_MOVL_TTREC, 0),
+
+ /* MOV to RA (extended) */
+ { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa6000000, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa6000002, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa6000004, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa6000006, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
+
+ /* Extended GET */
+ { "GETB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa7000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "GETW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa7000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "GETD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa7000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "GETL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa7000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+
+ /* Extended SET */
+ { "SETB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa5000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "SETW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa5000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "SETD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa5000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+ { "SETL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa5000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+
+ /* MOV to RA */
+ { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc000000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
+ { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc100000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
+ { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc400000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
+ { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc500000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
+
+ /* Standard GET */
+ { "GETB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+ { "GETW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+ { "GETD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+ /* GET is a synonym for GETD. */
+ { "GET", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+ { "GETL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+
+ /* Standard SET */
+ { "SETB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xb0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+ { "SETW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xb1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+ { "SETD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+ /* SET is a synonym for SETD. */
+ { "SET", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+ { "SETL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xb5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+
+ /* Multiple GET */
+ { "MGETD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
+ { "MGETL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xc9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
+
+ /* Multiple SET */
+ { "MSETD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xb8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
+ { "MSETL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xb9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
+
+ /* Conditional SET */
+ COND_INSN ("SETB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa4000000, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+ COND_INSN ("SETW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa4000001, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+ COND_INSN ("SETD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa4000200, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+ COND_INSN ("SETL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa4000201, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+ { "XFRD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xd0000000, 0xf2000000, INSN_GP, ENC_XFR, 0 },
+ { "XFRL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xd2000000, 0xf2000000, INSN_GP, ENC_XFR, 0 },
+
+ /* Fast control register setup */
+ { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa9000000, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
+ { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa9000001, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
+ { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa9000004, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
+ { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa9000005, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
+
+ /* Internal transfer operations */
+ { "JUMP", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xac000000, 0xff000004, INSN_GP, ENC_JUMP, 0 },
+ { "CALL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xac000004, 0xff000004, INSN_GP, ENC_JUMP, 0 },
+ { "CALLR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xab000000, 0xff000000, INSN_GP, ENC_CALLR, 0 },
+
+ /* Address unit ALU operations */
+ { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x80000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x82000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x82000005, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x80000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x82000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x82000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x86000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x84000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x86000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x88000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x8a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x8a000005, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x88000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x8a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x8a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x8e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x8c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x8e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+
+ /* Data unit ALU operations */
+ { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x00000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x08000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x02000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x0a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x02000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "MOVST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x0a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "ADD", DspMeta21,
+ 0x00000100, 0xfe000104, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC|DSP_ARGS_IMM },
+ { "ADD", DspMeta21,
+ 0x02000003, 0xfe000003, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_IMM },
+ COND_INSN ("ADD", "", 1, DspMeta21,
+ 0x040001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
+ { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x00000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "ADDS", DspMeta21,
+ 0x08000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 },
+ { "ADDS", DspMeta21,
+ 0x0a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x08000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x02000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x0a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x02000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ADDST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x0a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x06000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ COND_INSN ("ADDS", "", 1, DspMeta21,
+ 0x0c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
+ { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x0e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x04000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x0c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x06000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x0e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x10000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x18000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x12000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x1a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x12000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "NEGST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x1a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "SUB", DspMeta21,
+ 0x10000100, 0xfe000104, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC },
+ { "SUB", DspMeta21,
+ 0x12000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x10000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x18000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+ { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x12000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x1a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x12000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "SUBS", DspMeta21,
+ 0x18000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 },
+ { "SUBS", DspMeta21,
+ 0x1a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "SUBST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x1a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x16000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x1e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ COND_INSN ("SUBS", "", 1, DspMeta21,
+ 0x1c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
+ COND_INSN ("SUB", "", 1, DspMeta21,
+ 0x140001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
+ COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x14000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x1c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x16000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x1e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x20000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x28000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x20000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x28000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x22000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ANDMB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x22000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ANDSMB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ANDT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x22000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "ANDMT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x22000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "ANDST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "ANDSMT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "AND", DspMeta21,
+ 0x20000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x26000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x26000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "ANDQ", DspMeta21,
+ 0x20000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+ COND_INSN ("ANDQ", "", 1, DspMeta21,
+ 0x240001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_QR),
+ COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x24000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ { "ANDSQ", DspMeta21,
+ 0x28000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+ COND_INSN ("ANDSQ", "", 1, DspMeta21,
+ 0x2c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_QR),
+ COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x26000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("ANDQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x26000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+ COND_INSN ("ANDSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x2e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+ { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x30000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x38000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x30000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x38000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x32000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ORMB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x32000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ORSMB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "ORT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x32000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "ORMT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x32000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "ORST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "ORSMT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x36000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x36000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "ORQ", DspMeta21,
+ 0x30000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+ COND_INSN ("ORQ", "", 1, DspMeta21,
+ 0x340001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_QR),
+ COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x34000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ { "ORSQ", DspMeta21,
+ 0x38000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+ COND_INSN ("ORSQ", "", 1, DspMeta21,
+ 0x3c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_QR),
+ COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x36000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("ORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x36000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+ COND_INSN ("ORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x3e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+ { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x40000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x48000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x40000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x48000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x42000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "XORMB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x42000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "XORSMB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "XORT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x42000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "XORMT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x42000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "XORST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "XORSMT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x46000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x46000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+ { "XORQ", DspMeta21,
+ 0x40000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+ COND_INSN ("XORQ", "", 1, DspMeta21,
+ 0x440001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_QR),
+ COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x44000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ { "XORSQ", DspMeta21,
+ 0x48000140, 0xfe000140, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+ COND_INSN ("XORSQ", "", 1, DspMeta21,
+ 0x4c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_QR),
+ COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x46000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("XORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x46000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+ COND_INSN ("XORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x4e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+ { "LSL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x50000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+ { "LSL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x54000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+ COND_INSN ("LSL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x54000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+ { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x58000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+ { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x5c000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+ COND_INSN ("LSLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x5c000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+ { "LSR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x50000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+ { "LSR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x54000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+ COND_INSN ("LSR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x54000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+ { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x58000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+ { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x5c000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+ COND_INSN ("LSRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x5c000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+ { "ASL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x50000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+ { "ASL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x540000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+ COND_INSN ("ASL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x54000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+ { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x58000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+ { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x5c0000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+ COND_INSN ("ASLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x5c000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+ { "ASR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x500000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+ { "ASR", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x540000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+ COND_INSN ("ASR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x540000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+ { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x580000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+ { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x5c0000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+ COND_INSN ("ASRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x5c0000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+ { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x60000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ /* MUL is a synonym from MULD. */
+ { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+ { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x62000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+ { "MULWT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x62000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "MULDT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "MULT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+ { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x64000020, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
+ { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
+ { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
+ { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x66000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+ COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x64000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x66000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+ { "MIN", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x70000020, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
+ { "MAX", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x70000024, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
+ { "FFB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x70000004, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
+ { "NORM", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x70000008, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
+ { "ABS", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x70000028, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
+ { "XSDB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xaa000000, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "XSDSB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xaa000008, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "XSDW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xaa000002, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "XSDSW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xaa00000a, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "RTDW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xaa000006, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "RTDSW", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xaa00000e, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "NMIN", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x7000002c, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
+
+ /* Condition setting operations */
+ { "CMP", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x70000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 },
+ { "TST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x78000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 },
+ { "CMP", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x72000000, 0xfe000005, INSN_GP, ENC_CMP, 0 },
+ { "CMPMB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x72000004, 0xfe000005, INSN_GP, ENC_CMP, 0 },
+ { "TST", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x7a000000, 0xfe000005, INSN_GP, ENC_CMP, 0 },
+ { "TSTMB", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x7a000004, 0xfe000005, INSN_GP, ENC_CMP, 0 },
+ { "CMPT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x72000001, 0xfe000007, INSN_GP, ENC_CMP, 0 },
+ { "CMPMT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x72000005, 0xfe000007, INSN_GP, ENC_CMP, 0 },
+ { "TSTT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x7a000001, 0xfe000007, INSN_GP, ENC_CMP, 0 },
+ { "TSTMT", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x7a000005, 0xfe000007, INSN_GP, ENC_CMP, 0 },
+ COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x74000000, 0xfef801fe, INSN_GP, ENC_CMP, 0),
+ COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x7c000000, 0xfef801fe, INSN_GP, ENC_CMP, 0),
+ COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x76000000, 0xfef8003e, INSN_GP, ENC_CMP, 0),
+ COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0x7e000000, 0xfef8003e, INSN_GP, ENC_CMP, 0),
+
+ /* No-op (BNV) */
+ { "NOP", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa0fffffe, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+
+ /* Branch */
+ COND_INSN ("B", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa0000000, 0xff00001f, INSN_GP, ENC_BRANCH, 0),
+ COND_INSN ("B", "R", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa0000001, 0xff00001f, INSN_GP, ENC_BRANCH, 0),
+
+ /* System operations */
+ { "LOCK0", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa8000000, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+ { "LOCK1", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa8000001, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+ { "LOCK2", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa8000003, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+ { "RTI", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa3ffffff, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+ { "RTH", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa37fffff, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+ COND_INSN ("KICK", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa3000001, 0xff003e1f, INSN_GP, ENC_KICK, 0),
+ { "SWITCH", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xaf000000, 0xff000000, INSN_GP, ENC_SWITCH, 0 },
+ { "DCACHE", CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xad000000, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
+ { "ICACHEEXIT", CoreMeta12|CoreMeta21,
+ 0xae000000, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+ { "ICACHEEXITR", CoreMeta12|CoreMeta21,
+ 0xae000001, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+ { "ICACHE", CoreMeta12|CoreMeta21,
+ 0xae000000, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 },
+ { "ICACHER", CoreMeta12|CoreMeta21,
+ 0xae000001, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 },
+
+ /* Meta 2 instructions */
+ { "CACHERD", CoreMeta21,
+ 0xad000081, 0xff000087, INSN_GP, ENC_CACHER, 0 },
+ { "CACHERL", CoreMeta21,
+ 0xad000083, 0xff000087, INSN_GP, ENC_CACHER, 0 },
+ { "CACHEWD", CoreMeta21,
+ 0xad000001, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
+ { "CACHEWL", CoreMeta21,
+ 0xad000003, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
+ COND_INSN ("DEFR", "", 1, CoreMeta21,
+ 0xa3002001, 0xff003e1f, INSN_GP, ENC_KICK, 0),
+ { "BEXD", CoreMeta21,
+ 0xaa000004, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "BEXSD", CoreMeta21,
+ 0xaa00000c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "BEXL", CoreMeta21,
+ 0xaa000014, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "BEXSL", CoreMeta21,
+ 0xaa00001c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+ { "LNKGETB", CoreMeta21,
+ 0xad000080, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
+ { "LNKGETW", CoreMeta21,
+ 0xad000082, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
+ { "LNKGETD", CoreMeta21,
+ 0xad000084, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
+ { "LNKGETL", CoreMeta21,
+ 0xad000086, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
+ COND_INSN ("LNKSETB", "", 1, CoreMeta21,
+ 0xa4000080, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+ COND_INSN ("LNKSETW", "", 1, CoreMeta21,
+ 0xa4000081, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+ COND_INSN ("LNKSETD", "", 1, CoreMeta21,
+ 0xa4000280, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+ COND_INSN ("LNKSETL", "", 1, CoreMeta21,
+ 0xa4000281, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+
+ /* Meta 2 FPU instructions */
+
+ /* Port-to-unit MOV */
+ COND_INSN ("MOVL", "", 1, FpuMeta21,
+ 0xa1800201, 0xfff83e1f, INSN_FPU, ENC_MOV_PORT, 0),
+
+ /* Read pipeline drain */
+ { "MMOVD", FpuMeta21,
+ 0xce000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
+ { "MMOVL", FpuMeta21,
+ 0xcf000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
+
+ /* FP data movement instructions */
+ FCOND_INSN ("ABS", "", 1, FpuMeta21,
+ 0xf0000080, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
+ { "MMOVD", FpuMeta21,
+ 0xbe000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
+ { "MMOVL", FpuMeta21,
+ 0xbf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
+ { "MMOVD", FpuMeta21,
+ 0xce000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
+ { "MMOVL", FpuMeta21,
+ 0xcf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
+ { "MOVD", FpuMeta21,
+ 0x08000144, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
+ { "MOVD", FpuMeta21,
+ 0x080001c4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
+ { "MOVL", FpuMeta21,
+ 0x08000154, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
+ { "MOVL", FpuMeta21,
+ 0x080001d4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
+ FCOND_INSN ("MOV", "", 1, FpuMeta21,
+ 0xf0000000, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
+ { "MOV", FpuMeta21,
+ 0xf0000001, 0xff800001, INSN_FPU, ENC_FMOV_I, 0 },
+ FCOND_INSN ("NEG", "", 1, FpuMeta21,
+ 0xf0000100, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
+ { "PACK", FpuMeta21,
+ 0xf0000180, 0xff8c21ff, INSN_FPU, ENC_FPACK, 0 },
+ { "SWAP", FpuMeta21,
+ 0xf00001c0, 0xff8c7fff, INSN_FPU, ENC_FSWAP, 0 },
+
+ /* FP comparison instructions */
+ FCOND_INSN ("CMP", "", 1, FpuMeta21,
+ 0xf3000000, 0xfff4201f, INSN_FPU, ENC_FCMP, 0),
+ FCOND_INSN ("MAX", "", 1, FpuMeta21,
+ 0xf3000081, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
+ FCOND_INSN ("MIN", "", 1, FpuMeta21,
+ 0xf3000001, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
+
+ /* FP data conversion instructions */
+ FCOND_INSN ("DTOF", "", 1, FpuMeta21,
+ 0xf2000121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("FTOD", "", 1, FpuMeta21,
+ 0xf2000101, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("DTOH", "", 1, FpuMeta21,
+ 0xf2000320, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("FTOH", "", 1, FpuMeta21,
+ 0xf2000300, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("DTOI", "", 1, FpuMeta21,
+ 0xf2002120, 0xff842fff, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("FTOI", "", 1, FpuMeta21,
+ 0xf2002100, 0xff842fbf, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("DTOL", "", 1, FpuMeta21,
+ 0xf2002320, 0xff8c6fff, INSN_FPU, ENC_FCONV, 0),
+
+ FCOND_INSN ("DTOX", "", 1, FpuMeta21,
+ 0xf2000020, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
+ FCOND_INSN ("FTOX", "", 1, FpuMeta21,
+ 0xf2000000, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
+ FCOND_INSN ("DTOXL", "", 1, FpuMeta21,
+ 0xf20000a0, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
+
+ FCOND_INSN ("HTOD", "", 1, FpuMeta21,
+ 0xf2000321, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("HTOF", "", 1, FpuMeta21,
+ 0xf2000301, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("ITOD", "", 1, FpuMeta21,
+ 0xf2002121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("ITOF", "", 1, FpuMeta21,
+ 0xf2002101, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
+ FCOND_INSN ("LTOD", "", 1, FpuMeta21,
+ 0xf2002321, 0xff8c7fff, INSN_FPU, ENC_FCONV, 0),
+
+ FCOND_INSN ("XTOD", "", 1, FpuMeta21,
+ 0xf2000021, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
+ FCOND_INSN ("XTOF", "", 1, FpuMeta21,
+ 0xf2000001, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
+ FCOND_INSN ("XLTOD", "", 1, FpuMeta21,
+ 0xf20000a1, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
+
+ /* FP basic arithmetic instructions */
+ FCOND_INSN ("ADD", "", 1, FpuMeta21,
+ 0xf1000001, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
+ FCOND_INSN ("MUL", "", 1, FpuMeta21,
+ 0xf1000100, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
+ FCOND_INSN ("SUB", "", 1, FpuMeta21,
+ 0xf1000101, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
+
+ /* FP extended arithmetic instructions */
+ { "MAC", FpuMeta21,
+ 0xf6000000, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
+ { "MACS", FpuMeta21,
+ 0xf6000100, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
+
+ { "MAR", FpuMeta21,
+ 0xf6000004, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
+ { "MARS", FpuMeta21,
+ 0xf6000104, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
+
+ { "MAW", FpuMeta21,
+ 0xf6000008, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
+ { "MAWS", FpuMeta21,
+ 0xf6000108, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
+ { "MAW1", FpuMeta21,
+ 0xf6000009, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
+ { "MAWS1", FpuMeta21,
+ 0xf6000109, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
+
+ FCOND_INSN ("MXA", "", 1, FpuMeta21,
+ 0xf5000000, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
+ FCOND_INSN ("MXAS", "", 1, FpuMeta21,
+ 0xf5000100, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
+ FCOND_INSN ("MXA1", "", 1, FpuMeta21,
+ 0xf5000001, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
+ FCOND_INSN ("MXAS1", "", 1, FpuMeta21,
+ 0xf5000101, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
+
+ { "MUZ", FpuMeta21,
+ 0xf6000010, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
+ { "MUZS", FpuMeta21,
+ 0xf6000110, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
+ { "MUZ1", FpuMeta21,
+ 0xf6000011, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
+ { "MUZS1", FpuMeta21,
+ 0xf6000111, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
+
+ { "RCP", FpuMeta21,
+ 0xf7000000, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
+ { "RSQ", FpuMeta21,
+ 0xf7000100, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
+
+ /* FP SIMD arithmetic instructions */
+ { "ADDRE", FpuMeta21,
+ 0xf4000000, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
+ { "MULRE", FpuMeta21,
+ 0xf4000001, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
+ { "SUBRE", FpuMeta21,
+ 0xf4000100, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
+
+ /* FP memory instructions */
+ { "MGETD", FpuMeta21,
+ 0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+ { "MGET", FpuMeta21,
+ 0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+ { "MGETL", FpuMeta21,
+ 0xcf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+
+ { "MSETD", FpuMeta21,
+ 0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+ { "MSET", FpuMeta21,
+ 0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+ { "MSETL", FpuMeta21,
+ 0xbf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+
+ /* FP accumulator memory instructions */
+ { "GETL", FpuMeta21,
+ 0xcf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
+ { "SETL", FpuMeta21,
+ 0xbf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
+
+ /* DSP FPU data movement */
+ { "MOV", DspMeta21|FpuMeta21,
+ 0x08000146, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU,
+ DSP_ARGS_2|DSP_ARGS_DSP_SRC1 },
+ { "MOV", DspMeta21|FpuMeta21,
+ 0x080001c6, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU,
+ DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+
+ /* Unit-to-unit MOV */
+ COND_INSN ("MOV", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa3000000, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0),
+ COND_INSN ("TTMOV", "", 1, CoreMeta12|CoreMeta21,
+ 0xa3000201, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0),
+ COND_INSN ("SWAP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+ 0xa3000200, 0xff00021f, INSN_GP, ENC_SWAP, 0),
+
+ /* DSP memory instructions */
+ { "GETD", DspMeta21,
+ 0x94000100, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
+ { "SETD", DspMeta21,
+ 0x94000000, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
+ { "GETL", DspMeta21,
+ 0x94000104, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
+ { "SETL", DspMeta21,
+ 0x94000004, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
+
+ /* DSP read pipeline prime/drain */
+ { "MMOVD", DspMeta21,
+ 0xca000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 },
+ { "MMOVL", DspMeta21,
+ 0xcb000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 },
+ { "MMOVD", DspMeta21,
+ 0xcc000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 },
+ { "MMOVL", DspMeta21,
+ 0xcd000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 },
+
+ /* DSP Template instantiation */
+ TEMPLATE_INSN (DspMeta21, 0x90000000, 0xff00000f, INSN_DSP),
+ TEMPLATE_INSN (DspMeta21, 0x93000000, 0xff0001ff, INSN_DSP),
+ TEMPLATE_INSN (DspMeta21, 0x95000000, 0xff00000f, INSN_DSP),
+
+ { "AND", DspMeta21,
+ 0x22000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "ANDS", DspMeta21,
+ 0x28000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "ANDS", DspMeta21,
+ 0x2a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "MAX", DspMeta21,
+ 0x70000124, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "MIN", DspMeta21,
+ 0x70000120, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "NMIN", DspMeta21,
+ 0x7000012c, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "OR", DspMeta21,
+ 0x30000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "OR", DspMeta21,
+ 0x32000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "ORS", DspMeta21,
+ 0x38000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "ORS", DspMeta21,
+ 0x3a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "XOR", DspMeta21,
+ 0x40000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "XOR", DspMeta21,
+ 0x42000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "XORS", DspMeta21,
+ 0x48000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+ { "XORS", DspMeta21,
+ 0x4a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "ADDB8", DspMeta21,
+ 0x20000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "ADDT8", DspMeta21,
+ 0x2000010c, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "ADDSB8", DspMeta21,
+ 0x28000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "ADDST8", DspMeta21,
+ 0x2800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "MULB8", DspMeta21,
+ 0x40000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "MULT8", DspMeta21,
+ 0x4000010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "MULSB8", DspMeta21,
+ 0x48000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "MULST8", DspMeta21,
+ 0x4800010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "SUBB8", DspMeta21,
+ 0x30000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "SUBT8", DspMeta21,
+ 0x3000010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "SUBSB8", DspMeta21,
+ 0x38000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "SUBST8", DspMeta21,
+ 0x3800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+ { "MUL", DspMeta21,
+ 0x60000100, 0xfe000100, INSN_DSP, ENC_DALU,
+ DSP_ARGS_1|DSP_ARGS_DACC },
+ { "MUL", DspMeta21,
+ 0x62000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+ { "ABS", DspMeta21,
+ 0x70000128, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "FFB", DspMeta21,
+ 0x70000104, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "NORM", DspMeta21,
+ 0x70000108, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "CMP", DspMeta21,
+ 0x70000000, 0xfe0000ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
+ { "CMP", DspMeta21,
+ 0x72000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
+ { "TST", DspMeta21,
+ 0x78000100, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
+ { "TST", DspMeta21,
+ 0x7a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
+ { "MOV", DspMeta21,
+ 0x00000104, 0xfe078146, INSN_DSP, ENC_DALU,
+ DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_DSP_SRC2|DSP_ARGS_IMM },
+ { "MOVS", DspMeta21,
+ 0x08000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+ { "MOV", DspMeta21,
+ 0x91000000, 0xff000000, INSN_DSP, ENC_DALU,
+ DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_IMM },
+ { "MOV", DspMeta21,
+ 0x92000000, 0xff000000, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+ { "NEG", DspMeta21,
+ 0x10000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+ { "NEGS", DspMeta21,
+ 0x18000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+ { "XSDB", DspMeta21,
+ 0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "XSD", DspMeta21,
+ 0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "XSDW", DspMeta21,
+ 0xaa000102, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "XSDSB", DspMeta21,
+ 0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "XSDS", DspMeta21,
+ 0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "XSDSW", DspMeta21,
+ 0xaa00010a, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "LSL", DspMeta21,
+ 0x50000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+ { "LSR", DspMeta21,
+ 0x50000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+ { "ASL", DspMeta21,
+ 0x50000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+ { "ASR", DspMeta21,
+ 0x500001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+ { "LSL", DspMeta21,
+ 0x54000120, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
+ { "LSR", DspMeta21,
+ 0x54000160, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
+ { "ASL", DspMeta21,
+ 0x540001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
+ { "ASR", DspMeta21,
+ 0x540001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
+ COND_INSN ("LSL", "", 1, DspMeta21,
+ 0x54000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+ COND_INSN ("LSR", "", 1, DspMeta21,
+ 0x54000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+ COND_INSN ("ASL", "", 1, DspMeta21,
+ 0x54000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+ COND_INSN ("ASR", "", 1, DspMeta21,
+ 0x540001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+ { "LSLS", DspMeta21,
+ 0x58000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+ { "LSRS", DspMeta21,
+ 0x58000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+ { "ASLS", DspMeta21,
+ 0x58000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+ { "ASRS", DspMeta21,
+ 0x580001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+ COND_INSN ("LSLS", "", 1, DspMeta21,
+ 0x5c000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+ COND_INSN ("LSRS", "", 1, DspMeta21,
+ 0x5c000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+ COND_INSN ("ASLS", "", 1, DspMeta21,
+ 0x5c000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+ COND_INSN ("ASRS", "", 1, DspMeta21,
+ 0x5c0001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+ { "LSLS", DspMeta21,
+ 0x5c000120, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
+ { "LSRS", DspMeta21,
+ 0x5c000160, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
+ { "ASLS", DspMeta21,
+ 0x5c0001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
+ { "ASRS", DspMeta21,
+ 0x5c0001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
+ { "RTDW", DspMeta21,
+ 0xaa000106, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ { "RTDSW", DspMeta21,
+ 0xaa00010e, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+ };
+
+#define UNIT_MASK 0xf
+#define SHORT_UNIT_MASK 0x3
+#define EXT_BASE_REG_MASK 0x1
+#define REG_MASK 0x1f
+#define CC_MASK 0xf
+#define RMASK_MASK 0x7f
+#define GET_SET_IMM_MASK 0x3f
+#define GET_SET_IMM_BITS 6
+#define GET_SET_EXT_IMM_MASK 0xfff
+#define GET_SET_EXT_IMM_BITS 12
+#define DGET_SET_IMM_MASK 0x3
+#define DGET_SET_IMM_BITS 2
+#define MGET_MSET_MAX_REGS 8
+#define MMOV_MAX_REGS 8
+#define IMM16_MASK 0xffff
+#define IMM16_BITS 16
+#define IMM19_MASK 0x7ffff
+#define IMM19_BITS 19
+#define IMM8_MASK 0xff
+#define IMM8_BITS 8
+#define IMM24_MASK 0xffffff
+#define IMM24_BITS 24
+#define IMM5_MASK 0x1f
+#define IMM5_BITS 5
+#define IMM6_MASK 0x3f
+#define IMM6_BITS 6
+#define IMM15_MASK 0x7fff
+#define IMM15_BITS 15
+#define IMM4_MASK 0x1f
+#define IMM4_BITS 4
+#define CALLR_REG_MASK 0x7
+#define CPC_REG_MASK 0xf
+#define O2R_REG_MASK 0x7
+#define ACF_PART_MASK 0x3
+#define DSP_REG_MASK 0xf
+#define DSP_PART_MASK 0x17
+#define TEMPLATE_NUM_REGS 4
+#define TEMPLATE_REGS_MASK 0xf
+
+#define IS_TEMPLATE_DEF(insn) (insn->dsp_daoppame_flags & DSP_DAOPPAME_TEMP)
+
+unsigned int metag_get_set_size_bytes (unsigned int opcode);
+unsigned int metag_get_set_ext_size_bytes (unsigned int opcode);
+unsigned int metag_cond_set_size_bytes (unsigned int opcode);
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * Makefile.am: Add Meta.
+ * Makefile.in: Regenerate.
+ * configure.tgt: Add Meta.
+ * emulparams/elf32metag.sh: New file.
+ * emultempl/metagelf.em: New file.
+
2013-01-09 Alan Modra <amodra@gmail.com>
* emulparams/elf_x86_64.sh (LARGE_BSS_AFTER_BSS): Define.
eelf32mb_linux.c \
eelf32mcore.c \
eelf32mep.c \
+ eelf32metag.c \
eelf32microblazeel.c \
eelf32microblaze.c \
eelf32mipswindiss.c \
eelf32mep.c: $(srcdir)/emulparams/elf32mep.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/mep.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32mep "$(tdir_mep)"
+eelf32metag.c: $(srcdir)/emulparams/elf32metag.sh \
+ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/metagelf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32metag "$(tdir_metag)"
eelf32microblazeel.c: $(srcdir)/emulparams/elf32microblazeel.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32microblazeel "$(tdir_microblazeel)"
eelf32mb_linux.c \
eelf32mcore.c \
eelf32mep.c \
+ eelf32metag.c \
eelf32microblazeel.c \
eelf32microblaze.c \
eelf32mipswindiss.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mb_linux.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mcore.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mep.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32metag.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32microblaze.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32microblazeel.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Po@am__quote@
eelf32mep.c: $(srcdir)/emulparams/elf32mep.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/mep.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32mep "$(tdir_mep)"
+eelf32metag.c: $(srcdir)/emulparams/elf32metag.sh \
+ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/metagelf.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32metag "$(tdir_metag)"
eelf32microblazeel.c: $(srcdir)/emulparams/elf32microblazeel.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32microblazeel "$(tdir_microblazeel)"
-*- text -*-
+* Add support for the Imagination Technologies Meta processor.
+
Changes in 2.23:
* Enable compressed debug section feature for x86/x86_64 pe-coff.
mcore-*-elf) targ_emul=elf32mcore
;;
mep-*-elf) targ_emul=elf32mep ;;
+metag-*-*) targ_emul=elf32metag ;;
microblazeel*-linux*) targ_emul="elf32mbel_linux"
targ_extra_emuls="elf32mb_linux"
;;
--- /dev/null
+MACHINE=
+SCRIPT_NAME=elf
+TEMPLATE_NAME=elf32
+GENERATE_SHLIB_SCRIPT=yes
+GENERATE_PIE_SCRIPT=yes
+OUTPUT_FORMAT="elf32-metag"
+TEXT_START_ADDR=0x10005000
+ARCH=metag
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+ENTRY=__start
+NOP=0xa0fffffe
+EXTRA_EM_FILE=metagelf
+USER_LABEL_PREFIX=_
+OTHER_SECTIONS="
+ .core_text 0x80000000 :
+ {
+ *(.core_text)
+ }
+ .core_data 0x82000000 :
+ {
+ *(.core_data)
+ *(.core_rodata)
+ }
+ .internal_memory 0xe0200000 :
+ {
+ *(.internal_text)
+ *(.internal_data)
+ *(.internal_rodata)
+ }
+"
--- /dev/null
+# This shell script emits a C file. -*- C -*-
+# Copyright 2013 Free Software Foundation, Inc.
+#
+# This file is part of GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# This file is sourced from elf32.em, and defines extra metagelf
+# specific routines. Taken from hppaelf.em.
+#
+fragment <<EOF
+
+#include "ldctor.h"
+#include "elf32-metag.h"
+
+
+/* Fake input file for stubs. */
+static lang_input_statement_type *stub_file;
+
+/* Whether we need to call metag_layout_sections_again. */
+static int need_laying_out = 0;
+
+/* Maximum size of a group of input sections that can be handled by
+ one stub section. A value of +/-1 indicates the bfd back-end
+ should use a suitable default size. */
+static bfd_signed_vma group_size = 1;
+
+/* This is called before the input files are opened. We create a new
+ fake input file to hold the stub sections. */
+
+static void
+metagelf_create_output_section_statements (void)
+{
+ extern const bfd_target bfd_elf32_metag_vec;
+
+ if (link_info.output_bfd->xvec != &bfd_elf32_metag_vec)
+ return;
+
+ stub_file = lang_add_input_file ("linker stubs",
+ lang_input_file_is_fake_enum,
+ NULL);
+ stub_file->the_bfd = bfd_create ("linker stubs", link_info.output_bfd);
+ if (stub_file->the_bfd == NULL
+ || ! bfd_set_arch_mach (stub_file->the_bfd,
+ bfd_get_arch (link_info.output_bfd),
+ bfd_get_mach (link_info.output_bfd)))
+ {
+ einfo ("%X%P: can not create BFD %E\n");
+ return;
+ }
+
+ stub_file->the_bfd->flags |= BFD_LINKER_CREATED;
+ ldlang_add_file (stub_file);
+}
+
+
+struct hook_stub_info
+{
+ lang_statement_list_type add;
+ asection *input_section;
+};
+
+/* Traverse the linker tree to find the spot where the stub goes. */
+
+static bfd_boolean
+hook_in_stub (struct hook_stub_info *info, lang_statement_union_type **lp)
+{
+ lang_statement_union_type *l;
+ bfd_boolean ret;
+
+ for (; (l = *lp) != NULL; lp = &l->header.next)
+ {
+ switch (l->header.type)
+ {
+ case lang_constructors_statement_enum:
+ ret = hook_in_stub (info, &constructor_list.head);
+ if (ret)
+ return ret;
+ break;
+
+ case lang_output_section_statement_enum:
+ ret = hook_in_stub (info,
+ &l->output_section_statement.children.head);
+ if (ret)
+ return ret;
+ break;
+
+ case lang_wild_statement_enum:
+ ret = hook_in_stub (info, &l->wild_statement.children.head);
+ if (ret)
+ return ret;
+ break;
+
+ case lang_group_statement_enum:
+ ret = hook_in_stub (info, &l->group_statement.children.head);
+ if (ret)
+ return ret;
+ break;
+
+ case lang_input_section_enum:
+ if (l->input_section.section == info->input_section)
+ {
+ /* We've found our section. Insert the stub immediately
+ before its associated input section. */
+ *lp = info->add.head;
+ *(info->add.tail) = l;
+ return TRUE;
+ }
+ break;
+
+ case lang_data_statement_enum:
+ case lang_reloc_statement_enum:
+ case lang_object_symbols_statement_enum:
+ case lang_output_statement_enum:
+ case lang_target_statement_enum:
+ case lang_input_statement_enum:
+ case lang_assignment_statement_enum:
+ case lang_padding_statement_enum:
+ case lang_address_statement_enum:
+ case lang_fill_statement_enum:
+ break;
+
+ default:
+ FAIL ();
+ break;
+ }
+ }
+ return FALSE;
+}
+
+
+/* Call-back for elf_metag_size_stubs. */
+
+/* Create a new stub section, and arrange for it to be linked
+ immediately before INPUT_SECTION. */
+
+static asection *
+metagelf_add_stub_section (const char *stub_sec_name, asection *input_section)
+{
+ asection *stub_sec;
+ flagword flags;
+ asection *output_section;
+ const char *secname;
+ lang_output_section_statement_type *os;
+ struct hook_stub_info info;
+
+ flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
+ | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP);
+ stub_sec = bfd_make_section_anyway_with_flags (stub_file->the_bfd,
+ stub_sec_name, flags);
+ if (stub_sec == NULL)
+ goto err_ret;
+
+ output_section = input_section->output_section;
+ secname = bfd_get_section_name (output_section->owner, output_section);
+ os = lang_output_section_find (secname);
+
+ info.input_section = input_section;
+ lang_list_init (&info.add);
+ lang_add_section (&info.add, stub_sec, NULL, os);
+
+ if (info.add.head == NULL)
+ goto err_ret;
+
+ if (hook_in_stub (&info, &os->children.head))
+ return stub_sec;
+
+ err_ret:
+ einfo ("%X%P: can not make stub section: %E\n");
+ return NULL;
+}
+
+
+/* Another call-back for elf_metag_size_stubs. */
+
+static void
+metagelf_layout_sections_again (void)
+{
+ /* If we have changed sizes of the stub sections, then we need
+ to recalculate all the section offsets. This may mean we need to
+ add even more stubs. */
+ gld${EMULATION_NAME}_map_segments (TRUE);
+ need_laying_out = -1;
+}
+
+
+static void
+build_section_lists (lang_statement_union_type *statement)
+{
+ if (statement->header.type == lang_input_section_enum)
+ {
+ asection *i = statement->input_section.section;
+
+ if (!((lang_input_statement_type *) i->owner->usrdata)->flags.just_syms
+ && (i->flags & SEC_EXCLUDE) == 0
+ && i->output_section != NULL
+ && i->output_section->owner == link_info.output_bfd)
+ {
+ elf_metag_next_input_section (&link_info, i);
+ }
+ }
+}
+
+
+/* For Meta we use this opportunity to build linker stubs. */
+
+static void
+gld${EMULATION_NAME}_after_allocation (void)
+{
+ /* bfd_elf_discard_info just plays with data and debugging sections,
+ ie. doesn't affect code size, so we can delay resizing the
+ sections. It's likely we'll resize everything in the process of
+ adding stubs. */
+ if (bfd_elf_discard_info (link_info.output_bfd, &link_info))
+ need_laying_out = 1;
+
+ /* If generating a relocatable output file, then we don't
+ have to examine the relocs. */
+ if (stub_file != NULL && !link_info.relocatable)
+ {
+ int ret = elf_metag_setup_section_lists (link_info.output_bfd,
+ &link_info);
+
+ if (ret != 0)
+ {
+ if (ret < 0)
+ {
+ einfo ("%X%P: can not size stub section: %E\n");
+ return;
+ }
+
+ lang_for_each_statement (build_section_lists);
+
+ /* Call into the BFD backend to do the real work. */
+ if (! elf_metag_size_stubs (link_info.output_bfd,
+ stub_file->the_bfd,
+ &link_info,
+ group_size,
+ &metagelf_add_stub_section,
+ &metagelf_layout_sections_again))
+ {
+ einfo ("%X%P: can not size stub section: %E\n");
+ return;
+ }
+ }
+ }
+
+ if (need_laying_out != -1)
+ gld${EMULATION_NAME}_map_segments (need_laying_out);
+
+ if (! link_info.relocatable)
+ {
+ /* Now build the linker stubs. */
+ if (stub_file != NULL && stub_file->the_bfd->sections != NULL)
+ {
+ if (! elf_metag_build_stubs (&link_info))
+ einfo ("%X%P: can not build stubs: %E\n");
+ }
+ }
+}
+
+
+/* Avoid processing the fake stub_file in vercheck, stat_needed and
+ check_needed routines. */
+
+static void (*real_func) (lang_input_statement_type *);
+
+static void metag_for_each_input_file_wrapper (lang_input_statement_type *l)
+{
+ if (l != stub_file)
+ (*real_func) (l);
+}
+
+static void
+metag_lang_for_each_input_file (void (*func) (lang_input_statement_type *))
+{
+ real_func = func;
+ lang_for_each_input_file (&metag_for_each_input_file_wrapper);
+}
+
+#define lang_for_each_input_file metag_lang_for_each_input_file
+
+EOF
+
+# Define some shell vars to insert bits of code into the standard elf
+# parse_args and list_options functions.
+#
+PARSE_AND_LIST_PROLOGUE='
+#define OPTION_STUBGROUP_SIZE 301
+'
+
+PARSE_AND_LIST_LONGOPTS='
+ { "stub-group-size", required_argument, NULL, OPTION_STUBGROUP_SIZE },
+'
+
+PARSE_AND_LIST_OPTIONS='
+ fprintf (file, _("\
+ --stub-group-size=N Maximum size of a group of input sections that\n\
+ can be handled by one stub section. A negative\n\
+ value locates all stubs before their branches\n\
+ (with a group size of -N), while a positive\n\
+ value allows two groups of input sections, one\n\
+ before, and one after each stub section.\n\
+ Values of +/-1 indicate the linker should\n\
+ choose suitable defaults.\n"
+ ));
+'
+
+PARSE_AND_LIST_ARGS_CASES='
+ case OPTION_STUBGROUP_SIZE:
+ {
+ const char *end;
+ group_size = bfd_scan_vma (optarg, &end, 0);
+ if (*end)
+ einfo (_("%P%F: invalid number `%s'\''\n"), optarg);
+ }
+ break;
+'
+
+# Put these extra metagelf routines in ld_${EMULATION_NAME}_emulation
+#
+LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
+LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=metagelf_create_output_section_statements
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * ld-elf/merge.d: Mark Meta as xfail.
+ * ld-gc/start.d: Skip this test on Meta.
+ * ld-gc/personality.d: Skip this test on Meta.
+ * ld-metag/external.s: New file.
+ * ld-metag/metag.exp: New file.
+ * ld-metag/pcrel.d: New file.
+ * ld-metag/pcrel.s: New file.
+ * ld-metag/shared.d: New file.
+ * ld-metag/shared.r: New file.
+ * ld-metag/shared.s: New file.
+ * ld-metag/stub.d: New file.
+ * ld-metag/stub.s: New file.
+ * ld-metag/stub_pic_app.d: New file.
+ * ld-metag/stub_pic_app.r: New file.
+ * ld-metag/stub_pic_app.s: New file.
+ * ld-metag/stub_pic_shared.d: New file.
+ * ld-metag/stub_pic_shared.s: New file.
+ * ld-metag/stub_shared.d: New file.
+ * ld-metag/stub_shared.r: New file.
+ * ld-metag/stub_shared.s: New file.
+
2013-01-08 Thomas Schwinge <thomas@codesourcery.com>
* ld-i386/export-class.exp: Restore (and reword) comment about
#xfail: "i370-*-*" "i860-*-*" "i960-*-*" "ip2k-*-*" "iq2000-*-*" "lm32-*-*"
#xfail: "mcore-*-*" "mn102*-*-*" "mips*-*-*" "ms1-*-*" "msp430-*-*" "mep-*-*"
#xfail: "or32-*-*" "pj-*-*" "sparc*-*-*" "tic6x-*-*" "vax-*-*" "xstormy16-*-*"
-#xfail: "xtensa*-*-*"
+#xfail: "xtensa*-*-*" "metag-*-*"
.*: file format .*elf.*
#name: --gc-sections with __gxx_personality
#ld: --gc-sections -e main -L tmpdir -lpersonality
#nm: -n
-#xfail: bfin-*-* cris*-*-* frv-*-* mn10300-*-* vax-*-* xtensa-*-*
+#xfail: bfin-*-* cris*-*-* frv-*-* mn10300-*-* vax-*-* xtensa-*-* metag-*-*
# above targets don't support cfi
#failif
#ld: --gc-sections -e _start
#nm: -n
#target: *-*-linux* *-*-gnu*
-#notarget: *-*-*aout *-*-*oldld frv-*-linux*
+#notarget: *-*-*aout *-*-*oldld frv-*-linux* metag-*-linux*
#...
[0-9a-f]+ D +__start__foo
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * Makefile.am: Add Meta.
+ * configure.in: Add Meta.
+ * disassemble.c: Add Meta support.
+ * metag-dis.c: New file.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
mep-dis.c \
mep-ibld.c \
mep-opc.c \
+ metag-dis.c \
microblaze-dis.c \
micromips-opc.c \
mips-dis.c \
mep-dis.c \
mep-ibld.c \
mep-opc.c \
+ metag-dis.c \
microblaze-dis.c \
micromips-opc.c \
mips-dis.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-ibld.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-opc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/metag-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/microblaze-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/micromips-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mips-dis.Plo@am__quote@
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
+ bfd_metag_arch) ta="$ta metag-dis.lo" ;;
bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;;
bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo micromips-opc.lo" ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
+ bfd_metag_arch) ta="$ta metag-dis.lo" ;;
bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;;
bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo micromips-opc.lo" ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
#define ARCH_m88k
#define ARCH_mcore
#define ARCH_mep
+#define ARCH_metag
#define ARCH_microblaze
#define ARCH_mips
#define ARCH_mmix
disassemble = print_insn_mep;
break;
#endif
+#ifdef ARCH_metag
+ case bfd_arch_metag:
+ disassemble = print_insn_metag;
+ break;
+#endif
#ifdef ARCH_mips
case bfd_arch_mips:
if (bfd_big_endian (abfd))
info->skip_zeroes_at_end = 0;
break;
#endif
+#ifdef ARCH_metag
+ case bfd_arch_metag:
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
#ifdef ARCH_m32c
case bfd_arch_m32c:
/* This processor in fact is little endian. The value set here
--- /dev/null
+/* Disassemble Imagination Technologies Meta instructions.
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "dis-asm.h"
+#include "opintl.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "opcode/metag.h"
+
+/* Column widths for printing. */
+#define PREFIX_WIDTH "10"
+#define INSN_NAME_WIDTH "10"
+
+#define OPERAND_WIDTH 92
+#define ADDR_WIDTH 20
+#define REG_WIDTH 50
+#define DSP_PREFIX_WIDTH 17
+
+/* Value to print if we fail to parse a register name. */
+const char unknown_reg[] = "?";
+
+/* Return the size of a GET or SET instruction. */
+unsigned int
+metag_get_set_size_bytes (unsigned int opcode)
+{
+ switch (((opcode) >> 24) & 0x5)
+ {
+ case 0x5:
+ return 8;
+ case 0x4:
+ return 4;
+ case 0x1:
+ return 2;
+ case 0x0:
+ return 1;
+ }
+ return 1;
+}
+
+/* Return the size of an extended GET or SET instruction. */
+unsigned int
+metag_get_set_ext_size_bytes (unsigned int opcode)
+{
+ switch (((opcode) >> 1) & 0x3)
+ {
+ case 0x3:
+ return 8;
+ case 0x2:
+ return 4;
+ case 0x1:
+ return 2;
+ case 0x0:
+ return 1;
+ }
+ return 1;
+}
+
+/* Return the size of a conditional SET instruction. */
+unsigned int
+metag_cond_set_size_bytes (unsigned int opcode)
+{
+ switch (opcode & 0x201)
+ {
+ case 0x201:
+ return 8;
+ case 0x200:
+ return 4;
+ case 0x001:
+ return 2;
+ case 0x000:
+ return 1;
+ }
+ return 1;
+}
+
+/* Return a value sign-extended. */
+static int
+sign_extend (int n, unsigned int bits)
+{
+ int mask = 1 << (bits - 1);
+ return -(n & mask) | n;
+}
+
+/* Return the short interpretation of UNIT. */
+static unsigned int
+short_unit (unsigned int unit)
+{
+ if (unit == UNIT_CT)
+ return UNIT_A1;
+ else
+ return unit;
+}
+
+/* Return the register corresponding to UNIT and NUMBER or NULL. */
+static const metag_reg *
+lookup_reg (unsigned int unit, unsigned int number)
+{
+ size_t i;
+
+ for (i = 0; i < sizeof(metag_regtab)/sizeof(metag_regtab[0]); i++)
+ {
+ const metag_reg *reg = &metag_regtab[i];
+
+ if (reg->unit == unit && reg->no == number)
+ return reg;
+ }
+ return NULL;
+}
+
+
+/* Return the register name corresponding to UNIT and NUMBER or NULL. */
+static const char *
+lookup_reg_name (unsigned int unit, unsigned int number)
+{
+ const metag_reg *reg;
+
+ reg = lookup_reg (unit, number);
+
+ if (reg)
+ return reg->name;
+ else
+ return unknown_reg;
+}
+
+/* Return the unit that is the pair of UNIT. */
+static unsigned int
+get_pair_unit (unsigned int unit)
+{
+ switch (unit)
+ {
+ case UNIT_D0:
+ return UNIT_D1;
+ case UNIT_D1:
+ return UNIT_D0;
+ case UNIT_A0:
+ return UNIT_A1;
+ case UNIT_A1:
+ return UNIT_A0;
+ default:
+ return unit;
+ }
+}
+
+/* Return the name of the pair register for UNIT and NUMBER or NULL. */
+static const char *
+lookup_pair_reg_name (unsigned int unit, unsigned int number)
+{
+ if (unit == UNIT_FX)
+ return lookup_reg_name (unit, number + 1);
+ else
+ return lookup_reg_name (get_pair_unit (unit), number);
+}
+
+/* Return the name of the accumulator register for PART. */
+static const char *
+lookup_acf_name (unsigned int part)
+{
+ size_t i;
+
+ for (i = 0; i < sizeof(metag_acftab)/sizeof(metag_acftab[0]); i++)
+ {
+ const metag_acf *acf = &metag_acftab[i];
+
+ if (acf->part == part)
+ return acf->name;
+ }
+ return "ACF.?";
+}
+
+/* Return the register name for the O2R register for UNIT and NUMBER. */
+static const char *
+lookup_o2r (enum metag_unit unit, unsigned int number)
+{
+ unsigned int o2r_unit;
+ enum metag_unit actual_unit = UNIT_A0;
+ const metag_reg *reg;
+
+ o2r_unit = (number & ~O2R_REG_MASK) >> 3;
+ number = number & O2R_REG_MASK;
+
+ if (unit == UNIT_A0)
+ {
+ switch (o2r_unit)
+ {
+ case 0:
+ actual_unit = UNIT_A1;
+ break;
+ case 1:
+ actual_unit = UNIT_D0;
+ break;
+ case 2:
+ actual_unit = UNIT_RD;
+ break;
+ case 3:
+ actual_unit = UNIT_D1;
+ break;
+ }
+ }
+ else if (unit == UNIT_A1)
+ {
+ switch (o2r_unit)
+ {
+ case 0:
+ actual_unit = UNIT_D1;
+ break;
+ case 1:
+ actual_unit = UNIT_D0;
+ break;
+ case 2:
+ actual_unit = UNIT_RD;
+ break;
+ case 3:
+ actual_unit = UNIT_A0;
+ break;
+ }
+ }
+ else if (unit == UNIT_D0)
+ {
+ switch (o2r_unit)
+ {
+ case 0:
+ actual_unit = UNIT_A1;
+ break;
+ case 1:
+ actual_unit = UNIT_D1;
+ break;
+ case 2:
+ actual_unit = UNIT_RD;
+ break;
+ case 3:
+ actual_unit = UNIT_A0;
+ break;
+ }
+ }
+ else if (unit == UNIT_D1)
+ {
+ switch (o2r_unit)
+ {
+ case 0:
+ actual_unit = UNIT_A1;
+ break;
+ case 1:
+ actual_unit = UNIT_D0;
+ break;
+ case 2:
+ actual_unit = UNIT_RD;
+ break;
+ case 3:
+ actual_unit = UNIT_A0;
+ break;
+ }
+ }
+
+ reg = lookup_reg (actual_unit, number);
+
+ if (reg)
+ return reg->name;
+ else
+ return unknown_reg;
+}
+
+/* Return the string for split condition code CODE. */
+static const char *
+lookup_scc_flags (unsigned int code)
+{
+ size_t i;
+
+ for (i = 0; i < sizeof (metag_dsp_scondtab) / sizeof (metag_dsp_scondtab[0]); i++)
+ {
+ if (metag_dsp_scondtab[i].code == code)
+ {
+ return metag_dsp_scondtab[i].name;
+ }
+ }
+ return NULL;
+}
+
+/* Return the string for FPU split condition code CODE. */
+static const char *
+lookup_fpu_scc_flags (unsigned int code)
+{
+ size_t i;
+
+ for (i = 0; i < sizeof (metag_fpu_scondtab) / sizeof (metag_fpu_scondtab[0]); i++)
+ {
+ if (metag_fpu_scondtab[i].code == code)
+ {
+ return metag_fpu_scondtab[i].name;
+ }
+ }
+ return NULL;
+}
+
+/* Print an instruction with PREFIX, NAME and OPERANDS. */
+static void
+print_insn (disassemble_info *outf, const char *prefix, const char *name,
+ const char *operands)
+{
+ outf->fprintf_func (outf->stream, "%-" PREFIX_WIDTH "s%-" INSN_NAME_WIDTH "s%s", prefix, name, operands);
+}
+
+/* Print an instruction with no operands. */
+static void
+print_none (unsigned int insn_word ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ outf->fprintf_func (outf->stream, "%-" PREFIX_WIDTH "s%s", "",
+ template->name);
+}
+
+/* Print a unit to unit MOV instruction. */
+static void
+print_mov_u2u (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ unsigned int dest_unit, dest_no, src_unit, src_no;
+ unsigned int is_kick = (insn_word & 0x1) && !((insn_word >> 9) & 0x1);
+ unsigned int major = MAJOR_OPCODE (insn_word);
+ unsigned int minor = MINOR_OPCODE (insn_word);
+ char buf[OPERAND_WIDTH];
+ const char *dest_reg;
+ const char *src_reg;
+
+ dest_unit = (insn_word >> 5) & UNIT_MASK;
+ dest_no = (insn_word >> 14) & REG_MASK;
+
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+
+ if (is_kick)
+ src_unit = UNIT_TR;
+ else
+ src_unit = (insn_word >> 10) & UNIT_MASK;
+
+ /* This is really an RTI/RTH. No, really. */
+ if (major == OPC_MISC &&
+ minor == 0x3 &&
+ src_unit == 0xf)
+ {
+ if (insn_word & 0x800000)
+ outf->fprintf_func (outf->stream, "%-" PREFIX_WIDTH "s%s", "",
+ "RTI");
+ else
+ outf->fprintf_func (outf->stream, "%-" PREFIX_WIDTH "s%s", "",
+ "RTH");
+
+ return;
+ }
+
+ src_no = (insn_word >> 19) & REG_MASK;
+
+ src_reg = lookup_reg_name (src_unit, src_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ if (dest_unit == UNIT_FX || src_unit == UNIT_FX)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a MOV to port instruction. */
+static void
+print_mov_port (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ unsigned int dest_unit, dest1_no, dest2_no, src_unit, src_no;
+ unsigned int is_movl = MINOR_OPCODE (insn_word) == MOVL_MINOR;
+ char buf[OPERAND_WIDTH];
+ const char *dest_reg;
+ const char *pair_reg;
+ const char *src_reg;
+
+ if (is_movl)
+ dest_unit = short_unit ((insn_word >> 5) & SHORT_UNIT_MASK);
+ else
+ dest_unit = (insn_word >> 5) & UNIT_MASK;
+
+ dest1_no = (insn_word >> 14) & REG_MASK;
+ dest2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (dest_unit, dest1_no);
+ pair_reg = lookup_pair_reg_name (dest_unit, dest2_no);
+
+ src_unit = UNIT_RD;
+ src_no = 0;
+
+ src_reg = lookup_reg_name (src_unit, src_no);
+
+ if (is_movl)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, pair_reg, src_reg);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ if (dest_unit == UNIT_FX)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Return the number of bits set in rmask. */
+static unsigned int hweight (unsigned int rmask)
+{
+ unsigned int count;
+
+ for (count = 0; rmask; count++)
+ {
+ rmask &= rmask - 1;
+ }
+
+ return count;
+}
+
+/* Print a MOVL to TTREC instruction. */
+static void
+print_movl_ttrec (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ unsigned int dest_unit, dest_no, src1_no, src2_no, src_unit;
+ char buf[OPERAND_WIDTH];
+ const char *dest_reg;
+ const char *src_reg;
+ const char *pair_reg;
+
+ dest_unit = UNIT_TT;
+ dest_no = 3;
+
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+
+ src1_no = (insn_word >> 19) & REG_MASK;
+ src2_no = (insn_word >> 14) & REG_MASK;
+
+ src_unit = short_unit ((insn_word >> 7) & SHORT_UNIT_MASK);
+
+ src_reg = lookup_reg_name (src_unit, src1_no);
+ pair_reg = lookup_pair_reg_name (src_unit, src2_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, src_reg, pair_reg);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Format a GET or SET address mode string from INSN_WORD into BUF. */
+static void
+get_set_addr_str (char *buf, unsigned int buf_size, unsigned int size,
+ unsigned int insn_word)
+{
+ const char *base_reg;
+ unsigned int base_unit, base_no;
+ unsigned int imm = (insn_word >> 25) & 1;
+ unsigned int ua = (insn_word >> 7) & 1;
+ unsigned int pp = insn_word & 1;
+
+ base_unit = short_unit ((insn_word >> 5) & SHORT_UNIT_MASK);
+ base_no = (insn_word >> 14) & REG_MASK;
+
+ base_reg = lookup_reg_name (base_unit, base_no);
+
+ if (imm)
+ {
+ int offset = (insn_word >> 8) & GET_SET_IMM_MASK;
+
+ offset = sign_extend (offset, GET_SET_IMM_BITS);
+
+ if (offset == 0)
+ {
+ snprintf (buf, buf_size, "[%s]", base_reg);
+ return;
+ }
+
+ if (offset == 1 && ua)
+ {
+ if (pp)
+ snprintf (buf, buf_size, "[%s++]", base_reg);
+ else
+ snprintf (buf, buf_size, "[++%s]", base_reg);
+
+ return;
+ }
+ else if (offset == -1 && ua)
+ {
+ if (pp)
+ snprintf (buf, buf_size, "[%s--]", base_reg);
+ else
+ snprintf (buf, buf_size, "[--%s]", base_reg);
+
+ return;
+ }
+
+ offset = offset * size;
+
+ if (ua)
+ {
+ if (pp)
+ snprintf (buf, buf_size, "[%s+#%d++]", base_reg, offset);
+ else
+ snprintf (buf, buf_size, "[%s++#%d]", base_reg, offset);
+ }
+ else
+ snprintf (buf, buf_size, "[%s+#%d]", base_reg, offset);
+ }
+ else
+ {
+ const char *offset_reg;
+ unsigned int offset_no;
+
+ offset_no = (insn_word >> 9) & REG_MASK;
+
+ offset_reg = lookup_reg_name (base_unit, offset_no);
+
+ if (ua)
+ {
+ if (pp)
+ snprintf (buf, buf_size, "[%s+%s++]", base_reg, offset_reg);
+ else
+ snprintf (buf, buf_size, "[%s++%s]", base_reg, offset_reg);
+ }
+ else
+ snprintf (buf, buf_size, "[%s+%s]", base_reg, offset_reg);
+ }
+}
+
+/* Format an extended GET or SET address mode string from INSN_WORD into BUF. */
+static void
+get_set_ext_addr_str (char *buf, unsigned int buf_size, unsigned int size,
+ unsigned int insn_word)
+{
+ const char *base_reg;
+ unsigned int base_unit, base_no;
+ int offset;
+
+ base_unit = short_unit ((insn_word >> 5) & SHORT_UNIT_MASK);
+ base_no = insn_word & EXT_BASE_REG_MASK;
+
+ base_reg = lookup_reg_name (base_unit, base_no);
+
+ offset = (insn_word >> 7) & GET_SET_EXT_IMM_MASK;
+
+ offset = sign_extend (offset, GET_SET_EXT_IMM_BITS);
+
+ offset = offset * size;
+
+ if (offset == 0)
+ {
+ snprintf (buf, buf_size, "[%s]", base_reg);
+ }
+ else
+ {
+ snprintf (buf, buf_size, "[%s+#%d]", base_reg, offset);
+ }
+}
+
+/* Format an MGET or MSET address mode string from INSN_WORD into BUF. */
+static void
+mget_mset_addr_str (char *buf, unsigned int buf_size,
+ unsigned int insn_word)
+{
+ const char *base_reg;
+ unsigned int base_unit, base_no;
+
+ base_unit = short_unit ((insn_word >> 5) & SHORT_UNIT_MASK);
+ base_no = (insn_word >> 14) & REG_MASK;
+
+ base_reg = lookup_reg_name (base_unit, base_no);
+
+ snprintf (buf, buf_size, "[%s++]", base_reg);
+}
+
+/* Format a conditional SET address mode string from INSN_WORD into BUF. */
+static void
+cond_set_addr_str (char *buf, unsigned int buf_size,
+ unsigned int insn_word)
+{
+ const char *base_reg;
+ unsigned int base_unit, base_no;
+
+ base_unit = short_unit ((insn_word >> 5) & SHORT_UNIT_MASK);
+ base_no = (insn_word >> 14) & REG_MASK;
+
+ base_reg = lookup_reg_name (base_unit, base_no);
+
+ snprintf (buf, buf_size, "[%s]", base_reg);
+}
+
+/* Format a cache instruction address mode string from INSN_WORD into BUF. */
+static void
+cache_addr_str (char *buf, unsigned int buf_size, unsigned int insn_word,
+ int width)
+{
+ const char *base_reg;
+ unsigned int base_unit, base_no;
+ int offset;
+
+ base_unit = short_unit ((insn_word >> 5) & SHORT_UNIT_MASK);
+ base_no = (insn_word >> 14) & REG_MASK;
+
+ base_reg = lookup_reg_name (base_unit, base_no);
+
+ offset = (insn_word >> 8) & GET_SET_IMM_MASK;
+
+ offset = sign_extend (offset, GET_SET_IMM_BITS);
+
+ offset = offset * width;
+
+ if (offset == 0)
+ {
+ snprintf (buf, buf_size, "[%s]", base_reg);
+ }
+ else
+ {
+ snprintf (buf, buf_size, "[%s+#%d]", base_reg, offset);
+ }
+}
+
+/* Format a list of registers starting at REG_UNIT and REG_NO and conforming
+ to RMASK into BUF. */
+static void
+lookup_reg_list (char *reg_buf, size_t buf_len, unsigned int reg_unit,
+ unsigned int reg_no, unsigned int rmask,
+ bfd_boolean is_fpu_64bit)
+{
+ const char *regs[MGET_MSET_MAX_REGS];
+ size_t used_regs = 1, i, remaining;
+
+ regs[0] = lookup_reg_name (reg_unit, reg_no);
+
+ for (i = 1; i < MGET_MSET_MAX_REGS; i++)
+ {
+ if (rmask & 1)
+ {
+ if (is_fpu_64bit)
+ regs[used_regs] = lookup_reg_name (reg_unit, reg_no + (i * 2));
+ else
+ regs[used_regs] = lookup_reg_name (reg_unit, reg_no + i);
+ used_regs++;
+ }
+ rmask = rmask >> 1;
+ }
+
+ remaining = buf_len;
+
+ for (i = 0; i < used_regs; i++)
+ {
+ size_t len;
+ if (i == 0)
+ len = snprintf(reg_buf, remaining, "%s", regs[i]);
+ else
+ len = snprintf(reg_buf, remaining, ",%s", regs[i]);
+
+ reg_buf += len;
+ remaining -= len;
+ }
+}
+
+/* Print a GET instruction. */
+static void
+print_get (char *buf, char *addr_buf, unsigned int size,
+ const char *dest_reg, const char *pair_reg, unsigned int reg_unit,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ if (size == 8)
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, pair_reg,
+ addr_buf);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, addr_buf);
+ }
+
+ if (reg_unit == UNIT_FX)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a SET instruction. */
+static void
+print_set (char *buf, char *addr_buf, unsigned int size,
+ const char *src_reg, const char *pair_reg, unsigned int reg_unit,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ if (size == 8)
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", addr_buf, src_reg, pair_reg);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", addr_buf, src_reg);
+ }
+
+ if (reg_unit == UNIT_FX)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a GET or SET instruction. */
+static void
+print_get_set (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ unsigned int reg_unit, reg_no;
+ unsigned int size = metag_get_set_size_bytes (insn_word);
+ const char *reg_name;
+ const char *pair_reg;
+
+ reg_unit = (insn_word >> 1) & UNIT_MASK;
+ reg_no = (insn_word >> 19) & REG_MASK;
+
+ /* SETs should always print RD. */
+ if (!is_get && reg_unit == UNIT_RD)
+ reg_no = 0;
+
+ reg_name = lookup_reg_name (reg_unit, reg_no);
+
+ pair_reg = lookup_pair_reg_name (reg_unit, reg_no);
+
+ get_set_addr_str (addr_buf, ADDR_WIDTH, size, insn_word);
+
+ if (is_get)
+ {
+ /* RD regs are 64 bits wide so don't use the pair syntax. */
+ if (reg_unit == UNIT_RD)
+ print_get (buf, addr_buf, 4, reg_name, pair_reg, reg_unit,
+ template, outf);
+ else
+ print_get (buf, addr_buf, size, reg_name, pair_reg, reg_unit,
+ template, outf);
+ }
+ else
+ {
+ /* RD regs are 64 bits wide so don't use the pair syntax. */
+ if (reg_unit == UNIT_RD)
+ print_set (buf, addr_buf, 4, reg_name, pair_reg, reg_unit,
+ template, outf);
+ else
+ print_set (buf, addr_buf, size, reg_name, pair_reg, reg_unit,
+ template, outf);
+ }
+}
+
+/* Print an extended GET or SET instruction. */
+static void
+print_get_set_ext (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ bfd_boolean is_get = MINOR_OPCODE (template->meta_opcode) == GET_EXT_MINOR;
+ bfd_boolean is_mov = MINOR_OPCODE (template->meta_opcode) == MOV_EXT_MINOR;
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ unsigned int reg_unit, reg_no;
+ unsigned int size = metag_get_set_ext_size_bytes (insn_word);
+ const char *reg_name;
+ const char *pair_reg;
+
+ if (is_mov)
+ reg_unit = UNIT_RD;
+ else
+ reg_unit = short_unit ((insn_word >> 3) & SHORT_UNIT_MASK);
+
+ reg_no = (insn_word >> 19) & REG_MASK;
+
+ reg_name = lookup_reg_name (reg_unit, reg_no);
+
+ pair_reg = lookup_pair_reg_name (reg_unit, reg_no);
+
+ get_set_ext_addr_str (addr_buf, ADDR_WIDTH, size, insn_word);
+
+ if (is_get)
+ print_get (buf, addr_buf, size, reg_name, pair_reg, reg_unit,
+ template, outf);
+ else if (is_mov)
+ print_get (buf, addr_buf, 4, reg_name, pair_reg, reg_unit,
+ template, outf);
+ else
+ print_set (buf, addr_buf, size, reg_name, pair_reg, reg_unit,
+ template, outf);
+}
+
+/* Print an MGET or MSET instruction. */
+static void
+print_mget_mset (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bfd_boolean is_fpu = (MINOR_OPCODE (template->meta_opcode) & 0x6) == 0x6;
+ bfd_boolean is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) == 0x1;
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ char reg_buf[REG_WIDTH];
+ unsigned int reg_unit, reg_no, rmask;
+
+ if (is_fpu)
+ reg_unit = UNIT_FX;
+ else
+ reg_unit = short_unit ((insn_word >> 3) & SHORT_UNIT_MASK);
+
+ reg_no = (insn_word >> 19) & REG_MASK;
+ rmask = (insn_word >> 7) & RMASK_MASK;
+
+ lookup_reg_list (reg_buf, REG_WIDTH, reg_unit, reg_no, rmask,
+ is_fpu && is_64bit);
+
+ mget_mset_addr_str (addr_buf, ADDR_WIDTH, insn_word);
+
+ if (is_get)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", reg_buf, addr_buf);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", addr_buf, reg_buf);
+
+ if (is_fpu)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a conditional SET instruction. */
+static void
+print_cond_set (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ unsigned int src_unit, src_no;
+ unsigned int size = metag_cond_set_size_bytes (insn_word);
+ const char *src_reg;
+ const char *pair_reg;
+
+ src_unit = (insn_word >> 10) & UNIT_MASK;
+ src_no = (insn_word >> 19) & REG_MASK;
+
+ if (src_unit == UNIT_RD)
+ src_no = 0;
+
+ src_reg = lookup_reg_name (src_unit, src_no);
+
+ pair_reg = lookup_pair_reg_name (src_unit, src_no);
+
+ cond_set_addr_str (addr_buf, ADDR_WIDTH, insn_word);
+
+ if (src_unit == UNIT_RD)
+ print_set (buf, addr_buf, 4, src_reg, pair_reg, src_unit,
+ template, outf);
+ else
+ print_set (buf, addr_buf, size, src_reg, pair_reg, src_unit,
+ template, outf);
+}
+
+/* Print a MMOV instruction. */
+static void
+print_mmov (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ unsigned int is_fpu = template->insn_type == INSN_FPU;
+ unsigned int is_prime = ((MINOR_OPCODE (template->meta_opcode) & 0x2) &&
+ !is_fpu);
+ unsigned int is_64bit = MINOR_OPCODE (template->meta_opcode) & 0x1;
+ unsigned int is_dsp = template->meta_opcode & 0x1;
+ unsigned int dest_unit, dest_no, rmask;
+ char buf[OPERAND_WIDTH];
+ char reg_buf[REG_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+
+ if (is_fpu)
+ dest_no = (insn_word >> 14) & REG_MASK;
+ else
+ dest_no = (insn_word >> 19) & REG_MASK;
+
+ rmask = (insn_word >> 7) & RMASK_MASK;
+
+ if (is_prime)
+ {
+ const char *dest_reg;
+ const char *base_reg;
+ unsigned int base_unit, base_no;
+ int i, count = hweight (rmask);
+
+ dest_reg = lookup_reg_name (UNIT_RD, dest_no);
+
+ strcpy (reg_buf, dest_reg);
+
+ for (i = 0; i < count; i++)
+ {
+ strcat (reg_buf, ",");
+ strcat (reg_buf, dest_reg);
+ }
+
+ base_unit = short_unit ((insn_word >> 5) & SHORT_UNIT_MASK);
+ base_no = (insn_word >> 14) & REG_MASK;
+
+ base_reg = lookup_reg_name (base_unit, base_no);
+
+ snprintf (addr_buf, ADDR_WIDTH, "[%s++]", base_reg);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", reg_buf, addr_buf);
+ }
+ else
+ {
+ if (is_fpu)
+ dest_unit = UNIT_FX;
+ else
+ dest_unit = short_unit ((insn_word >> 3) & SHORT_UNIT_MASK);
+
+ lookup_reg_list (reg_buf, REG_WIDTH, dest_unit, dest_no, rmask,
+ is_fpu && is_64bit);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,RD", reg_buf);
+ }
+
+ if (is_dsp)
+ {
+ char prefix_buf[10] = {0};
+ if (is_prime)
+ {
+ if (dest_no == 22 || dest_no == 23)
+ strcpy (prefix_buf, "DB");
+ else if (dest_no == 24)
+ strcpy (prefix_buf, "DBH");
+ else if (dest_no == 25)
+ strcpy (prefix_buf, "DWH");
+ else if (dest_no == 31)
+ strcpy (prefix_buf, "DW");
+ }
+ else
+ strcpy (prefix_buf, "DW");
+ print_insn (outf, prefix_buf, template->name, buf);
+ }
+ else if (is_fpu)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print an MDRD instruction. */
+static void
+print_mdrd (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ unsigned int rmask, count;
+ char buf[OPERAND_WIDTH];
+
+ rmask = (insn_word >> 7) & RMASK_MASK;
+
+ count = hweight (rmask);
+
+ snprintf (buf, OPERAND_WIDTH, "#%#x", count + 1);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print an XFR instruction. */
+static void
+print_xfr (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char dest_buf[ADDR_WIDTH];
+ char src_buf[ADDR_WIDTH];
+ unsigned int dest_unit, src_unit;
+ unsigned int dest_no, src_no;
+ unsigned int us, ud, pp;
+ const char *dest_base_reg;
+ const char *dest_offset_reg;
+ const char *src_base_reg;
+ const char *src_offset_reg;
+
+ src_unit = short_unit ((insn_word >> 2) & SHORT_UNIT_MASK);
+ src_no = (insn_word >> 19) & REG_MASK;
+
+ src_base_reg = lookup_reg_name (src_unit, src_no);
+
+ src_no = (insn_word >> 14) & REG_MASK;
+
+ src_offset_reg = lookup_reg_name (src_unit, src_no);
+
+ dest_unit = short_unit (insn_word & SHORT_UNIT_MASK);
+ dest_no = (insn_word >> 9) & REG_MASK;
+
+ dest_base_reg = lookup_reg_name (dest_unit, dest_no);
+
+ dest_no = (insn_word >> 4) & REG_MASK;
+
+ dest_offset_reg = lookup_reg_name (dest_unit, dest_no);
+
+ us = (insn_word >> 27) & 0x1;
+ ud = (insn_word >> 26) & 0x1;
+ pp = (insn_word >> 24) & 0x1;
+
+ if (us)
+ if (pp)
+ snprintf (src_buf, ADDR_WIDTH, "[%s+%s++]", src_base_reg,
+ src_offset_reg);
+ else
+ snprintf (src_buf, ADDR_WIDTH, "[%s++%s]", src_base_reg,
+ src_offset_reg);
+ else
+ snprintf (src_buf, ADDR_WIDTH, "[%s+%s]", src_base_reg,
+ src_offset_reg);
+
+ if (ud)
+ if (pp)
+ snprintf (dest_buf, ADDR_WIDTH, "[%s+%s++]", dest_base_reg,
+ dest_offset_reg);
+ else
+ snprintf (dest_buf, ADDR_WIDTH, "[%s++%s]", dest_base_reg,
+ dest_offset_reg);
+ else
+ snprintf (dest_buf, ADDR_WIDTH, "[%s+%s]", dest_base_reg,
+ dest_offset_reg);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_buf, src_buf);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a MOV to control unit instruction. */
+static void
+print_mov_ct (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int reg_no;
+ unsigned int se = (insn_word >> 1) & 0x1;
+ unsigned int is_trace = (insn_word >> 2) & 0x1;
+ int value;
+ const char *dest_reg;
+
+ reg_no = (insn_word >> 19) & REG_MASK;
+
+ if (is_trace)
+ dest_reg = lookup_reg_name (UNIT_TT, reg_no);
+ else
+ dest_reg = lookup_reg_name (UNIT_CT, reg_no);
+
+ value = (insn_word >> 3) & IMM16_MASK;
+
+ if (se)
+ {
+ value = sign_extend (value, IMM16_BITS);
+ snprintf (buf, OPERAND_WIDTH, "%s,#%d", dest_reg, value);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,#%#x", dest_reg, value);
+ }
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a SWAP instruction. */
+static void
+print_swap (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int dest_no, src_no;
+ unsigned int dest_unit, src_unit;
+ const char *dest_reg;
+ const char *src_reg;
+
+ src_unit = (insn_word >> 10) & UNIT_MASK;
+ src_no = (insn_word >> 19) & REG_MASK;
+
+ src_reg = lookup_reg_name (src_unit, src_no);
+
+ dest_unit = (insn_word >> 5) & UNIT_MASK;
+ dest_no = (insn_word >> 14) & REG_MASK;
+
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ if (dest_unit == UNIT_FX || src_unit == UNIT_FX)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a SWAP instruction. */
+static void
+print_jump (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int reg_no, reg_unit;
+ const char *reg_name;
+ int value;
+
+ reg_unit = short_unit (insn_word & SHORT_UNIT_MASK);
+ reg_no = (insn_word >> 19) & REG_MASK;
+
+ reg_name = lookup_reg_name (reg_unit, reg_no);
+
+ value = (insn_word >> 3) & IMM16_MASK;
+
+ snprintf (buf, OPERAND_WIDTH, "%s,#%#x", reg_name, value);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a CALLR instruction. */
+static void
+print_callr (unsigned int insn_word, bfd_vma pc, const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int reg_no, reg_unit;
+ const char *reg_name;
+ int value;
+
+ reg_unit = short_unit ((insn_word >> 3) & SHORT_UNIT_MASK);
+ reg_no = insn_word & CALLR_REG_MASK;
+
+ reg_name = lookup_reg_name (reg_unit, reg_no);
+
+ value = (insn_word >> 5) & IMM19_MASK;
+
+ value = sign_extend (value, IMM19_BITS);
+
+ value = value * 4;
+
+ value += pc;
+
+ snprintf (buf, OPERAND_WIDTH, "%s,", reg_name);
+
+ print_insn (outf, "", template->name, buf);
+
+ outf->print_address_func (value, outf);
+}
+
+/* Print a GP ALU instruction. */
+static void
+print_alu (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int is_addr_op = MAJOR_OPCODE (template->meta_opcode) == OPC_ADDR;
+ unsigned int is_mul = MAJOR_OPCODE (template->meta_opcode) == OPC_MUL;
+ unsigned int dest_no, src1_no, src2_no;
+ unsigned int imm = (insn_word >> 25) & 0x1;
+ unsigned int cond = (insn_word >> 26) & 0x1;
+ unsigned int o1z = 0;
+ unsigned int o2r = insn_word & 0x1;
+ unsigned int unit_bit = (insn_word >> 24) & 0x1;
+ unsigned int ca = (insn_word >> 5) & 0x1;
+ unsigned int se = (insn_word >> 1) & 0x1;
+ bfd_boolean is_quickrot = template->arg_type & GP_ARGS_QR;
+ enum metag_unit base_unit;
+ enum metag_unit dest_unit;
+ const char *dest_reg;
+ const char *src1_reg;
+ const char *src2_reg;
+ int value;
+
+ if ((MAJOR_OPCODE (template->meta_opcode) == OPC_ADDR ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_ADD ||
+ MAJOR_OPCODE (template->meta_opcode) == OPC_SUB) &&
+ ((insn_word >> 2) & 0x1))
+ o1z = 1;
+
+ if (is_addr_op)
+ {
+ if (unit_bit)
+ base_unit = UNIT_A1;
+ else
+ base_unit = UNIT_A0;
+ }
+ else
+ {
+ if (unit_bit)
+ base_unit = UNIT_D1;
+ else
+ base_unit = UNIT_D0;
+ }
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src1_no = (insn_word >> 14) & REG_MASK;
+ src2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_unit = base_unit;
+
+ if (imm)
+ {
+ if (cond)
+ {
+ if (ca)
+ {
+ dest_unit = (insn_word >> 1) & UNIT_MASK;
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+ }
+ else
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+
+ src1_reg = lookup_reg_name (base_unit, src1_no);
+
+ value = (insn_word >> 6) & IMM8_MASK;
+
+ if (is_quickrot)
+ {
+ unsigned int qr_unit = unit_bit ? UNIT_A1 : UNIT_A0;
+ unsigned int qr_no = 2;
+ const char *qr_reg = lookup_reg_name (qr_unit, qr_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,#%#x,%s", dest_reg,
+ src1_reg, value, qr_reg);
+ }
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,#%#x", dest_reg,
+ src1_reg, value);
+ }
+ else
+ {
+ if (is_addr_op && (dest_no & ~CPC_REG_MASK))
+ {
+ dest_reg = lookup_reg_name (dest_unit, dest_no & CPC_REG_MASK);
+ src1_reg = lookup_reg_name (base_unit, 0x10);
+ }
+ else
+ {
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+ src1_reg = lookup_reg_name (base_unit, dest_no);
+ }
+
+ value = (insn_word >> 3) & IMM16_MASK;
+
+ if (se)
+ {
+ value = sign_extend (value, IMM16_BITS);
+ if (o1z)
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,#%d", dest_reg, value);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,#%d", dest_reg,
+ src1_reg, value);
+ }
+ }
+ else
+ {
+ if (o1z)
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,#%#x", dest_reg, value);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,#%#x", dest_reg,
+ src1_reg, value);
+ }
+ }
+ }
+ }
+ else
+ {
+ src1_reg = lookup_reg_name (base_unit, src1_no);
+
+ if (o2r)
+ src2_reg = lookup_o2r (base_unit, src2_no);
+ else
+ src2_reg = lookup_reg_name (base_unit, src2_no);
+
+ if (cond)
+ {
+ dest_unit = (insn_word >> 5) & UNIT_MASK;
+
+ if (is_mul)
+ {
+ if (ca)
+ dest_unit = (insn_word >> 1) & UNIT_MASK;
+ else
+ dest_unit = base_unit;
+ }
+
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg,
+ src1_reg, src2_reg);
+ }
+ else
+ {
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+
+ if (is_quickrot)
+ {
+ unsigned int qr_unit = unit_bit ? UNIT_A1 : UNIT_A0;
+ unsigned int qr_no = 2 + ((insn_word >> 7) & 0x1);
+ const char *qr_reg = lookup_reg_name (qr_unit, qr_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s,%s", dest_reg,
+ src1_reg, src2_reg, qr_reg);
+ }
+ else if (o1z)
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src2_reg);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg,
+ src1_reg, src2_reg);
+ }
+ }
+ }
+
+ if (dest_unit == UNIT_FX)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a B instruction. */
+static void
+print_branch (unsigned int insn_word, bfd_vma pc,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ int value;
+
+ value = (insn_word >> 5) & IMM19_MASK;
+
+ value = sign_extend (value, IMM19_BITS);
+
+ value = value * 4;
+
+ value += pc;
+
+ print_insn (outf, "", template->name, "");
+
+ outf->print_address_func (value, outf);
+}
+
+/* Print a SWITCH instruction. */
+static void
+print_switch (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int value;
+
+ value = insn_word & IMM24_MASK;
+
+ snprintf (buf, OPERAND_WIDTH, "#%#x", value);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a shift instruction. */
+static void
+print_shift (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int dest_no, src1_no, src2_no;
+ unsigned int imm = (insn_word >> 25) & 0x1;
+ unsigned int cond = (insn_word >> 26) & 0x1;
+ unsigned int unit_bit = (insn_word >> 24) & 0x1;
+ unsigned int ca = (insn_word >> 5) & 0x1;
+ enum metag_unit base_unit;
+ unsigned int dest_unit;
+ const char *dest_reg;
+ const char *src1_reg;
+ const char *src2_reg;
+ int value;
+
+ if (unit_bit)
+ base_unit = UNIT_D1;
+ else
+ base_unit = UNIT_D0;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src1_no = (insn_word >> 14) & REG_MASK;
+ src2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_unit = base_unit;
+
+ if (imm)
+ {
+ if (cond && ca)
+ dest_unit = (insn_word >> 1) & UNIT_MASK;
+
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+
+ src1_reg = lookup_reg_name (base_unit, src1_no);
+
+ value = (insn_word >> 9) & IMM5_MASK;
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,#%#x", dest_reg,
+ src1_reg, value);
+ }
+ else
+ {
+ if (cond && ca)
+ dest_unit = (insn_word >> 1) & UNIT_MASK;
+
+ dest_reg = lookup_reg_name (dest_unit, dest_no);
+
+ src1_reg = lookup_reg_name (base_unit, src1_no);
+ src2_reg = lookup_reg_name (base_unit, src2_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg,
+ src1_reg, src2_reg);
+ }
+
+ if (dest_unit == UNIT_FX)
+ print_insn (outf, "F", template->name, buf);
+ else
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a MIN or MAX instruction. */
+static void
+print_min_max (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ unsigned int base_unit, dest_no, src1_no, src2_no;
+ char buf[OPERAND_WIDTH];
+ const char *dest_reg;
+ const char *src1_reg;
+ const char *src2_reg;
+
+ if ((insn_word >> 24) & UNIT_MASK)
+ base_unit = UNIT_D1;
+ else
+ base_unit = UNIT_D0;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src1_no = (insn_word >> 14) & REG_MASK;
+ src2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (base_unit, dest_no);
+
+ src1_reg = lookup_reg_name (base_unit, src1_no);
+ src2_reg = lookup_reg_name (base_unit, src2_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, src1_reg, src2_reg);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a bit operation instruction. */
+static void
+print_bitop (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ unsigned int swap_inst = MAJOR_OPCODE (template->meta_opcode) == OPC_MISC;
+ unsigned int base_unit, src_unit, dest_no, src_no;
+ unsigned int is_bexl = 0;
+ char buf[OPERAND_WIDTH];
+ const char *dest_reg;
+ const char *src_reg;
+
+ if (swap_inst &&
+ ((insn_word >> 1) & 0xb) == 0xa)
+ is_bexl = 1;
+
+ if (swap_inst)
+ {
+ if (insn_word & 0x1)
+ base_unit = UNIT_D1;
+ else
+ base_unit = UNIT_D0;
+ }
+ else
+ {
+ if ((insn_word >> 24) & 0x1)
+ base_unit = UNIT_D1;
+ else
+ base_unit = UNIT_D0;
+ }
+
+ src_unit = base_unit;
+
+ if (is_bexl)
+ base_unit = get_pair_unit (base_unit);
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+
+ dest_reg = lookup_reg_name (base_unit, dest_no);
+
+ src_no = (insn_word >> 14) & REG_MASK;
+
+ src_reg = lookup_reg_name (src_unit, src_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a CMP or TST instruction. */
+static void
+print_cmp (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int dest_no, src_no;
+ unsigned int imm = (insn_word >> 25) & 0x1;
+ unsigned int cond = (insn_word >> 26) & 0x1;
+ unsigned int o2r = insn_word & 0x1;
+ unsigned int unit_bit = (insn_word >> 24) & 0x1;
+ unsigned int se = (insn_word >> 1) & 0x1;
+ enum metag_unit base_unit;
+ const char *dest_reg;
+ const char *src_reg;
+ int value;
+
+ if (unit_bit)
+ base_unit = UNIT_D1;
+ else
+ base_unit = UNIT_D0;
+
+ dest_no = (insn_word >> 14) & REG_MASK;
+ src_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (base_unit, dest_no);
+
+ if (imm)
+ {
+ if (cond)
+ {
+ value = (insn_word >> 6) & IMM8_MASK;
+
+ snprintf (buf, OPERAND_WIDTH, "%s,#%#x", dest_reg, value);
+ }
+ else
+ {
+ dest_no = (insn_word >> 19) & REG_MASK;
+
+ dest_reg = lookup_reg_name (base_unit, dest_no);
+
+ value = (insn_word >> 3) & IMM16_MASK;
+
+ if (se)
+ {
+ value = sign_extend (value, IMM16_BITS);
+ snprintf (buf, OPERAND_WIDTH, "%s,#%d", dest_reg, value);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,#%#x", dest_reg, value);
+ }
+ }
+ }
+ else
+ {
+ if (o2r)
+ src_reg = lookup_o2r (base_unit, src_no);
+ else
+ src_reg = lookup_reg_name (base_unit, src_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+ }
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a CACHER instruction. */
+static void
+print_cacher (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ unsigned int reg_unit, reg_no;
+ unsigned int size = ((insn_word >> 1) & 0x1) ? 8 : 4;
+ const char *reg_name;
+ const char *pair_name;
+
+ reg_unit = short_unit ((insn_word >> 3) & SHORT_UNIT_MASK);
+ reg_no = (insn_word >> 19) & REG_MASK;
+
+ reg_name = lookup_reg_name (reg_unit, reg_no);
+ pair_name = lookup_pair_reg_name (reg_unit, reg_no);
+
+ cache_addr_str (addr_buf, ADDR_WIDTH, insn_word, size);
+
+ if (size == 8)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", reg_name, pair_name, addr_buf);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", reg_name, addr_buf);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a CACHEW instruction. */
+static void
+print_cachew (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ unsigned int reg_unit, reg_no;
+ unsigned int size = ((insn_word >> 1) & 0x1) ? 8 : 4;
+ const char *reg_name;
+ const char *pair_name;
+
+ reg_unit = short_unit ((insn_word >> 3) & SHORT_UNIT_MASK);
+ reg_no = (insn_word >> 19) & REG_MASK;
+
+ reg_name = lookup_reg_name (reg_unit, reg_no);
+ pair_name = lookup_pair_reg_name (reg_unit, reg_no);
+
+ cache_addr_str (addr_buf, ADDR_WIDTH, insn_word, 64);
+
+ if (size == 8)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", addr_buf, reg_name, pair_name);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", addr_buf, reg_name);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print an ICACHE instruction. */
+static void
+print_icache (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ int offset;
+ int pfcount;
+
+ offset = ((insn_word >> 9) & IMM15_MASK);
+ pfcount = ((insn_word >> 1) & IMM4_MASK);
+
+ offset = sign_extend (offset, IMM15_BITS);
+
+ if (pfcount)
+ snprintf (buf, OPERAND_WIDTH, "#%d,#0x%x", offset, pfcount);
+ else
+ snprintf (buf, OPERAND_WIDTH, "#%d,#0", offset);
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print a LNKGET instruction. */
+static void
+print_lnkget (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ unsigned int reg_unit, reg_no;
+ unsigned int size = metag_get_set_ext_size_bytes (insn_word);
+ const char *reg_name;
+ const char *pair_name;
+
+ reg_unit = short_unit ((insn_word >> 3) & SHORT_UNIT_MASK);
+ reg_no = (insn_word >> 19) & REG_MASK;
+
+ reg_name = lookup_reg_name (reg_unit, reg_no);
+ pair_name = lookup_pair_reg_name (reg_unit, reg_no);
+
+ cache_addr_str (addr_buf, ADDR_WIDTH, insn_word, size);
+
+ if (size == 8)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", reg_name, pair_name, addr_buf);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", reg_name, addr_buf);
+
+ print_insn (outf, "", template->name, buf);
+}
+
+/* Print an FPU MOV instruction. */
+static void
+print_fmov (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix_buf[10];
+ unsigned int src_no, dest_no;
+ unsigned int p = (insn_word >> 6) & 0x1;
+ unsigned int d = (insn_word >> 5) & 0x1;
+ unsigned int cc = (insn_word >> 1) & CC_MASK;
+ bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ const char *dest_reg;
+ const char *src_reg;
+ const char *cc_flags;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src_no = (insn_word >> 14) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src_reg = lookup_reg_name (UNIT_FX, src_no);
+
+ cc_flags = lookup_fpu_scc_flags (cc);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ snprintf (prefix_buf, 10, "F%s%s%s", p ? "L" : "",
+ d ? "D" : "", show_cond ? cc_flags : "");
+
+ print_insn (outf, prefix_buf, template->name, buf);
+}
+
+/* Convert an FPU rmask into a compatible form. */
+static unsigned int
+convert_fx_rmask (unsigned int rmask)
+{
+ int num_bits = hweight (rmask), i;
+ unsigned int ret = 0;
+
+ for (i = 0; i < num_bits; i++)
+ {
+ ret <<= 1;
+ ret |= 0x1;
+ }
+
+ return ret;
+}
+
+/* Print an FPU MMOV instruction. */
+static void
+print_fmmov (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char data_buf[REG_WIDTH];
+ char fpu_buf[REG_WIDTH];
+ bfd_boolean to_fpu = MAJOR_OPCODE (insn_word) == OPC_GET;
+ bfd_boolean is_mmovl = MINOR_OPCODE (insn_word) & 0x1;
+ unsigned int rmask = (insn_word >> 7) & RMASK_MASK;
+ unsigned int fpu_no, data_no, data_unit;
+
+ data_no = (insn_word >> 19) & REG_MASK;
+ fpu_no = (insn_word >> 14) & REG_MASK;
+
+ if (insn_word & 0x1)
+ data_unit = UNIT_D1;
+ else
+ data_unit = UNIT_D0;
+
+ lookup_reg_list (data_buf, REG_WIDTH, data_unit, data_no, rmask, FALSE);
+ lookup_reg_list (fpu_buf, REG_WIDTH, UNIT_FX, fpu_no,
+ convert_fx_rmask (rmask), is_mmovl);
+
+ if (to_fpu)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", fpu_buf, data_buf);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", data_buf, fpu_buf);
+
+ print_insn (outf, "F", template->name, buf);
+}
+
+/* Print an FPU data unit MOV instruction. */
+static void
+print_fmov_data (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int src_no, dest_no;
+ unsigned int to_fpu = ((insn_word >> 7) & 0x1);
+ unsigned int unit_bit = (insn_word >> 24) & 0x1;
+ enum metag_unit base_unit;
+ const char *dest_reg;
+ const char *src_reg;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src_no = (insn_word >> 9) & REG_MASK;
+
+ if (unit_bit)
+ base_unit = UNIT_D1;
+ else
+ base_unit = UNIT_D0;
+
+ if (to_fpu)
+ {
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src_reg = lookup_reg_name (base_unit, src_no);
+ }
+ else
+ {
+ dest_reg = lookup_reg_name (base_unit, dest_no);
+ src_reg = lookup_reg_name (UNIT_FX, src_no);
+ }
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ print_insn (outf, "F", template->name, buf);
+}
+
+/* Print an FPU MOV immediate instruction. */
+static void
+print_fmov_i (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int dest_no;
+ unsigned int p = (insn_word >> 2) & 0x1;
+ unsigned int d = (insn_word >> 1) & 0x1;
+ const char *dest_reg;
+ unsigned int value = (insn_word >> 3) & IMM16_MASK;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,#%#x", dest_reg, value);
+
+ if (p)
+ print_insn (outf, "FL", template->name, buf);
+ else if (d)
+ print_insn (outf, "FD", template->name, buf);
+ else
+ print_insn (outf, "F", template->name, buf);
+}
+
+/* Print an FPU PACK instruction. */
+static void
+print_fpack (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int src1_no, src2_no, dest_no;
+ const char *dest_reg;
+ const char *src1_reg;
+ const char *src2_reg;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src1_no = (insn_word >> 14) & REG_MASK;
+ src2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src1_reg = lookup_reg_name (UNIT_FX, src1_no);
+ src2_reg = lookup_reg_name (UNIT_FX, src2_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, src1_reg, src2_reg);
+
+ print_insn (outf, "F", template->name, buf);
+}
+
+/* Print an FPU SWAP instruction. */
+static void
+print_fswap (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int src_no, dest_no;
+ const char *dest_reg;
+ const char *src_reg;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src_no = (insn_word >> 14) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src_reg = lookup_reg_name (UNIT_FX, src_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ print_insn (outf, "FL", template->name, buf);
+}
+
+/* Print an FPU CMP instruction. */
+static void
+print_fcmp (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix_buf[10];
+ unsigned int src_no, dest_no;
+ unsigned int a = (insn_word >> 19) & 0x1;
+ unsigned int z = (insn_word >> 8) & 0x1;
+ unsigned int p = (insn_word >> 6) & 0x1;
+ unsigned int d = (insn_word >> 5) & 0x1;
+ unsigned int q = (insn_word >> 7) & 0x1;
+ unsigned int cc = (insn_word >> 1) & CC_MASK;
+ bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ const char *dest_reg;
+ const char *src_reg;
+ const char *cc_flags;
+
+ dest_no = (insn_word >> 14) & REG_MASK;
+ src_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src_reg = lookup_reg_name (UNIT_FX, src_no);
+
+ cc_flags = lookup_fpu_scc_flags (cc);
+
+ if (z)
+ snprintf (buf, OPERAND_WIDTH, "%s,#0", dest_reg);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ snprintf (prefix_buf, 10, "F%s%s%s%s%s", p ? "L" : "",
+ d ? "D" : "", a ? "A" : "", q ? "Q" : "",
+ show_cond ? cc_flags : "");
+
+ print_insn (outf, prefix_buf, template->name, buf);
+}
+
+/* Print an FPU MIN or MAX instruction. */
+static void
+print_fminmax (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix_buf[10];
+ unsigned int p = (insn_word >> 6) & 0x1;
+ unsigned int d = (insn_word >> 5) & 0x1;
+ unsigned int src1_no, src2_no, dest_no;
+ unsigned int cc = (insn_word >> 1) & CC_MASK;
+ bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ const char *dest_reg;
+ const char *src1_reg;
+ const char *src2_reg;
+ const char *cc_flags;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src1_no = (insn_word >> 14) & REG_MASK;
+ src2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src1_reg = lookup_reg_name (UNIT_FX, src1_no);
+ src2_reg = lookup_reg_name (UNIT_FX, src2_no);
+
+ cc_flags = lookup_fpu_scc_flags (cc);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, src1_reg, src2_reg);
+
+ snprintf (prefix_buf, 10, "F%s%s%s", p ? "L" : "",
+ d ? "D" : "", show_cond ? cc_flags : "");
+
+ print_insn (outf, prefix_buf, template->name, buf);
+}
+
+/* Print an FPU data conversion instruction. */
+static void
+print_fconv (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix_buf[10];
+ unsigned int p = (insn_word >> 6) & 0x1;
+ unsigned int z = (insn_word >> 12) & 0x1;
+ unsigned int src_no, dest_no;
+ unsigned int cc = (insn_word >> 1) & CC_MASK;
+ bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ const char *dest_reg;
+ const char *src_reg;
+ const char *cc_flags;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src_no = (insn_word >> 14) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src_reg = lookup_reg_name (UNIT_FX, src_no);
+
+ cc_flags = lookup_fpu_scc_flags (cc);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ snprintf (prefix_buf, 10, "F%s%s%s", p ? "L" : "",
+ z ? "Z" : "", show_cond ? cc_flags : "");
+
+ print_insn (outf, prefix_buf, template->name, buf);
+}
+
+/* Print an FPU extended data conversion instruction. */
+static void
+print_fconvx (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix_buf[10];
+ unsigned int p = (insn_word >> 6) & 0x1;
+ unsigned int xl = (insn_word >> 7) & 0x1;
+ unsigned int src_no, dest_no, fraction_bits;
+ unsigned int cc = (insn_word >> 1) & CC_MASK;
+ bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ const char *dest_reg;
+ const char *src_reg;
+ const char *cc_flags;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src_no = (insn_word >> 14) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src_reg = lookup_reg_name (UNIT_FX, src_no);
+
+ cc_flags = lookup_fpu_scc_flags (cc);
+
+ if (xl)
+ fraction_bits = (insn_word >> 8) & IMM6_MASK;
+ else
+ fraction_bits = (insn_word >> 9) & IMM5_MASK;
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,#%#x", dest_reg, src_reg,
+ fraction_bits);
+
+ snprintf (prefix_buf, 10, "F%s%s", p ? "L" : "",
+ show_cond ? cc_flags : "");
+
+ print_insn (outf, prefix_buf, template->name, buf);
+}
+
+/* Print an FPU basic arithmetic instruction. */
+static void
+print_fbarith (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix_buf[10];
+ unsigned int n = (insn_word >> 7) & 0x1;
+ unsigned int p = (insn_word >> 6) & 0x1;
+ unsigned int d = (insn_word >> 5) & 0x1;
+ unsigned int src1_no, src2_no, dest_no;
+ unsigned int cc = (insn_word >> 1) & CC_MASK;
+ bfd_boolean show_cond = cc != COND_A && cc != COND_NV;
+ const char *dest_reg;
+ const char *src1_reg;
+ const char *src2_reg;
+ const char *cc_flags;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src1_no = (insn_word >> 14) & REG_MASK;
+ src2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src1_reg = lookup_reg_name (UNIT_FX, src1_no);
+ src2_reg = lookup_reg_name (UNIT_FX, src2_no);
+
+ cc_flags = lookup_fpu_scc_flags (cc);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, src1_reg, src2_reg);
+
+ snprintf (prefix_buf, 10, "F%s%s%s%s", p ? "L" : "",
+ d ? "D" : "", n ? "I" : "", show_cond ? cc_flags : "");
+
+ print_insn (outf, prefix_buf, template->name, buf);
+}
+
+/* Print an FPU extended arithmetic instruction. */
+static void
+print_fearith (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix_buf[10];
+ bfd_boolean is_muz = (MINOR_OPCODE (insn_word) == 0x6 &&
+ ((insn_word >> 4) & 0x1));
+ bfd_boolean is_mac = (MINOR_OPCODE (insn_word) == 0x6 &&
+ (insn_word & 0x1f) == 0);
+ bfd_boolean is_maw = (MINOR_OPCODE (insn_word) == 0x6 &&
+ ((insn_word >> 3) & 0x1));
+ unsigned int o3o = insn_word & 0x1;
+ unsigned int q = is_muz && ((insn_word >> 1) & 0x1);
+ unsigned int n = (insn_word >> 7) & 0x1;
+ unsigned int p = (insn_word >> 6) & 0x1;
+ unsigned int d = (insn_word >> 5) & 0x1;
+ unsigned int cc = (insn_word >> 1) & CC_MASK;
+ bfd_boolean show_cond = (MINOR_OPCODE (insn_word) == 0x5 && cc != COND_A &&
+ cc != COND_NV);
+ unsigned int src1_no, src2_no, dest_no;
+ const char *dest_reg;
+ const char *src1_reg;
+ const char *src2_reg;
+ const char *cc_flags;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src1_no = (insn_word >> 14) & REG_MASK;
+ src2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src1_reg = lookup_reg_name (UNIT_FX, src1_no);
+ src2_reg = lookup_reg_name (UNIT_FX, src2_no);
+
+ cc_flags = lookup_fpu_scc_flags (cc);
+
+ if (is_mac)
+ snprintf (buf, OPERAND_WIDTH, "ACF.0,%s,%s", src1_reg, src2_reg);
+ else if (o3o && is_maw)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", src1_reg, src2_reg);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, src1_reg, src2_reg);
+
+ snprintf (prefix_buf, 10, "F%s%s%s%s%s", p ? "L" : "",
+ d ? "D" : "", n ? "I" : "", q ? "Q" : "",
+ show_cond ? cc_flags : "");
+
+ print_insn (outf, prefix_buf, template->name, buf);
+}
+
+/* Print an FPU RCP or RSQ instruction. */
+static void
+print_frec (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix_buf[10];
+ unsigned int z = (insn_word >> 10) & 0x1;
+ unsigned int q = (insn_word >> 9) & 0x1;
+ unsigned int n = (insn_word >> 7) & 0x1;
+ unsigned int p = (insn_word >> 6) & 0x1;
+ unsigned int d = (insn_word >> 5) & 0x1;
+ unsigned int src_no, dest_no;
+ const char *dest_reg;
+ const char *src_reg;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src_no = (insn_word >> 14) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src_reg = lookup_reg_name (UNIT_FX, src_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", dest_reg, src_reg);
+
+ snprintf (prefix_buf, 10, "F%s%s%s%s%s", p ? "L" : "",
+ d ? "D" : "", n ? "I" : "", q ? "Q" : "", z ? "Z" : "");
+
+ print_insn (outf, prefix_buf, template->name, buf);
+}
+
+static void
+print_fsimd (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ unsigned int n = (insn_word >> 7) & 0x1;
+ unsigned int src1_no, src2_no, dest_no;
+ const char *dest_reg;
+ const char *src1_reg;
+ const char *src2_reg;
+
+ dest_no = (insn_word >> 19) & REG_MASK;
+ src1_no = (insn_word >> 14) & REG_MASK;
+ src2_no = (insn_word >> 9) & REG_MASK;
+
+ dest_reg = lookup_reg_name (UNIT_FX, dest_no);
+ src1_reg = lookup_reg_name (UNIT_FX, src1_no);
+ src2_reg = lookup_reg_name (UNIT_FX, src2_no);
+
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", dest_reg, src1_reg, src2_reg);
+
+ if (n)
+ print_insn (outf, "FLI", template->name, buf);
+ else
+ print_insn (outf, "FL", template->name, buf);
+}
+
+/* Print an FPU accumulator GET or SET instruction. */
+static void
+print_fget_set_acf (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ unsigned int part;
+ const char *reg_name;
+
+ part = (insn_word >> 19) & ACF_PART_MASK;
+
+ reg_name = lookup_acf_name (part);
+
+ mget_mset_addr_str (addr_buf, ADDR_WIDTH, insn_word);
+
+ if (is_get)
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", reg_name, addr_buf);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", addr_buf, reg_name);
+ }
+ print_insn (outf, "F", template->name, buf);
+}
+
+/* Return the name of the DSP register or accumulator for NUM and UNIT. */
+static const char *
+__lookup_dsp_name (unsigned int num, unsigned int unit)
+{
+ size_t i;
+
+ for (i = 0; i < sizeof(metag_dsp_regtab)/sizeof(metag_dsp_regtab[0]); i++)
+ {
+ const metag_reg *reg = &metag_dsp_regtab[i];
+
+ if (reg->no == num)
+ {
+ if ((reg->unit == UNIT_RAM_D0 || reg->unit == UNIT_ACC_D0) &&
+ unit == UNIT_D0)
+ return reg->name;
+
+ if ((reg->unit == UNIT_RAM_D1 || reg->unit == UNIT_ACC_D1) &&
+ unit == UNIT_D1)
+ return reg->name;
+ }
+ }
+ return "?.?";
+}
+
+/* Return the name of the DSP register for NUM and UNIT. */
+static const char *
+lookup_dsp_name (unsigned int num, unsigned int unit)
+{
+ size_t i;
+
+ for (i = 0; i < sizeof(metag_dsp_regtab)/sizeof(metag_dsp_regtab[0]); i++)
+ {
+ const metag_reg *reg = &metag_dsp_regtab[i];
+
+ if (reg->no == num && reg->unit == unit)
+ return reg->name;
+ }
+ return "?.?";
+}
+
+/* Return the name of the DSP RAM register for NUM and UNIT. */
+static const char *
+lookup_dspram_name (unsigned int num, unsigned int unit, bfd_boolean load)
+{
+ size_t i, nentries;
+
+ nentries = sizeof(metag_dsp_tmpl_regtab[load])/sizeof(metag_dsp_tmpl_regtab[load][0]);
+
+ for (i = 0; i < nentries; i++)
+ {
+ const metag_reg *reg = &metag_dsp_tmpl_regtab[load][i];
+
+ if (reg->no == num && reg->unit == unit)
+ return reg->name;
+ }
+ return "?.?";
+}
+
+/* This lookup function looks up the corresponding name for a register
+ number in a DSP instruction. SOURCE indicates whether this
+ register is a source or destination operand. */
+static const char *
+lookup_any_reg_name (unsigned int unit, unsigned int num, bfd_boolean source)
+{
+ /* A register with the top bit set (5th bit) indicates a DSPRAM
+ register. */
+ if (num > 15)
+ {
+ unsigned int dunit = (unit == UNIT_D0) ? UNIT_RAM_D0 : UNIT_RAM_D1;
+ return lookup_dspram_name (num, dunit, source);
+ }
+ else
+ return lookup_reg_name (unit, num);
+}
+
+/* Return the DSP data unit for UNIT. */
+static inline enum metag_unit
+dsp_data_unit_to_sym (unsigned int unit)
+{
+ if (unit == 0)
+ return UNIT_D0;
+ else
+ return UNIT_D1;
+}
+
+/* Print a DSP GET or SET instruction. */
+static void
+print_dget_set (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ bfd_boolean is_get = (template->meta_opcode & 0x100);
+ char buf[OPERAND_WIDTH];
+ char addr_buf[ADDR_WIDTH];
+ char prefix[DSP_PREFIX_WIDTH];
+ unsigned int part;
+ const char *reg_name[2];
+ bfd_boolean is_high = FALSE;
+ bfd_boolean is_dual = (insn_word & 0x4);
+ bfd_boolean is_template = (insn_word & 0x2);
+ const char *base_reg = "?";
+ unsigned int addr_unit, base_no, unit;
+
+ unit = dsp_data_unit_to_sym (insn_word & 0x1);
+
+ /* Is this a load/store to a template table? */
+ if (is_template)
+ {
+ part = (insn_word >> 19) & 0x1f;
+ reg_name[0] = lookup_dsp_name (part, UNIT_DT);
+ }
+ else
+ {
+ part = (insn_word >> 19) & REG_MASK;
+ is_high = ((part & 0x18) == 0x18);
+
+ /* Strip bit high indicator. */
+ if (is_high)
+ part &= 0x17;
+
+ reg_name[0] = __lookup_dsp_name (part, unit);
+
+ }
+
+ /* Is this a dual unit DSP operation? The modulo operator below
+ makes sure that we print the Rd register in the correct order,
+ e.g. because there's only one bit in the instruction for the Data
+ Unit we have to work out what the other data unit number is.
+ (there's only 2). */
+ if (is_dual)
+ {
+ unsigned int _unit = insn_word & 0x1;
+
+ _unit = ((_unit + 1) % 2);
+ reg_name[1] = __lookup_dsp_name(part, dsp_data_unit_to_sym (_unit));
+ }
+ else
+ reg_name[1] = NULL;
+
+ addr_unit = ((insn_word >> 18) & 0x1);
+ if (addr_unit == 0)
+ addr_unit = UNIT_A0;
+ else
+ addr_unit = UNIT_A1;
+
+ base_no = (insn_word >> 14) & DSP_REG_MASK;
+
+ base_reg = lookup_reg_name (addr_unit, base_no);
+
+ /* Check if it's a post-increment/post-decrement. */
+ if (insn_word & 0x2000)
+ {
+ unsigned int imm = (insn_word >> 9) & DGET_SET_IMM_MASK;
+ const char *post_op;
+
+ switch (imm)
+ {
+ case 0x1:
+ post_op = "++";
+ break;
+ case 0x3:
+ post_op = "--";
+ break;
+ default:
+ post_op = "";
+ }
+
+ snprintf (addr_buf, ADDR_WIDTH, "[%s%s]", base_reg, post_op);
+ }
+ else
+ {
+ unsigned int offset_part = (insn_word >> 9) & DSP_REG_MASK;
+ const char *offset_reg = lookup_reg_name (addr_unit, offset_part);
+
+ snprintf (addr_buf, ADDR_WIDTH, "[%s+%s++]", base_reg, offset_reg);
+ }
+
+ if (is_get)
+ {
+ if (is_dual && !is_template)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", reg_name[0],
+ reg_name[1], addr_buf);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", reg_name[0], addr_buf);
+ }
+ else
+ {
+ if (is_dual && !is_template)
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s", addr_buf,
+ reg_name[0], reg_name[1]);
+ else
+ snprintf (buf, OPERAND_WIDTH, "%s,%s", addr_buf, reg_name[0]);
+ }
+
+ snprintf (prefix, DSP_PREFIX_WIDTH, "D%s", is_high ? "H" : "");
+ print_insn (outf, prefix, template->name, buf);
+}
+
+/* Print a DSP template instruction. */
+static void
+print_dtemplate (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ char buf[OPERAND_WIDTH];
+ char prefix[DSP_PREFIX_WIDTH];
+ unsigned int offset[4];
+ bfd_boolean is_half = (MINOR_OPCODE (insn_word) == 0x5);
+ bfd_boolean daop_only = (MINOR_OPCODE (insn_word) == 0x3);
+
+ offset[0] = ((insn_word >> 19) & REG_MASK);
+ offset[1] = ((insn_word >> 14) & REG_MASK);
+ offset[2] = ((insn_word >> 9) & REG_MASK);
+ offset[3] = ((insn_word >> 4) & REG_MASK);
+
+ if (daop_only)
+ snprintf (buf, OPERAND_WIDTH, "#0x%x,#0x%x,#0x%x", offset[0],
+ offset[1], offset[2]);
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "#0x%x,#0x%x,#0x%x,#0x%x", offset[0],
+ offset[1], offset[2], offset[3]);
+ }
+
+ snprintf (prefix, DSP_PREFIX_WIDTH, "D%s", is_half ? "H" : "");
+ print_insn (outf, prefix, template->name, buf);
+}
+
+/* Format template definition from INSN_WORD into BUF. */
+static void
+decode_template_definition(unsigned int insn_word, char *buf, size_t len)
+{
+ bfd_boolean load = ((insn_word >> 13) & 0x1);
+ bfd_boolean dspram = (((insn_word >> 17) & 0x3) == 0x3);
+ const char *template[1];
+ unsigned int tidx = ((insn_word >> 9) & TEMPLATE_REGS_MASK);
+ enum metag_unit au, ram_unit;
+ unsigned int addr_reg_nums[2];
+ const char *addr_reg_names[2];
+ const char *post_op = "";
+ const char *join_op = "";
+ enum metag_unit data_unit = ((insn_word >> 24) & 0x1) ? UNIT_D1 : UNIT_D0;
+
+ template[0] = lookup_dsp_name (tidx, UNIT_DT);
+
+ addr_reg_names[1] = "";
+
+ if (dspram)
+ {
+ ram_unit = (data_unit == UNIT_D0) ? UNIT_RAM_D0 : UNIT_RAM_D1;
+ addr_reg_nums[0] = ((insn_word >> 19) & REG_MASK);
+ addr_reg_names[0] = lookup_dspram_name (addr_reg_nums[0],
+ ram_unit, load);
+ }
+ else
+ {
+ bfd_boolean im = (((insn_word >> 18) & 0x1) != 0);
+
+ au = (((insn_word >> 23) & 0x1) == 0) ? UNIT_A0 : UNIT_A1;
+ addr_reg_nums[0] = ((insn_word >> 19) & DSP_REG_MASK);
+
+ addr_reg_names[0] = lookup_reg_name (au, addr_reg_nums[0]);
+
+ if (im)
+ {
+ unsigned int im_value = ((insn_word >> 14) & 0x3);
+
+ switch (im_value)
+ {
+ case 0x1:
+ post_op = "++";
+ break;
+ case 0x3:
+ post_op = "--";
+ break;
+ }
+ }
+ else
+ {
+ addr_reg_nums[1] = ((insn_word >> 14) & DSP_REG_MASK);
+ addr_reg_names[1] = lookup_reg_name (au, addr_reg_nums[1]);
+ join_op = "+";
+ post_op = "++";
+ }
+ }
+
+ if (load)
+ {
+ len = snprintf (buf, len, " %s,[%s%s%s%s]", template[0], addr_reg_names[0],
+ join_op, addr_reg_names[1], post_op);
+ }
+ else
+ {
+ len = snprintf (buf, len, " [%s%s%s%s],%s", addr_reg_names[0], join_op,
+ addr_reg_names[1], post_op, template[0]);
+ }
+}
+
+/* Print a DSP ALU instruction. */
+static void
+print_dalu (unsigned int insn_word, bfd_vma pc ATTRIBUTE_UNUSED,
+ const insn_template *template,
+ disassemble_info *outf)
+{
+ bfd_boolean is_dual = FALSE;
+ unsigned int data_unit = (((insn_word >> 24) & 0x1) ? UNIT_D1 : UNIT_D0);
+ const char *reg_names[3];
+ unsigned int reg_nums[3];
+ bfd_boolean ac = ((insn_word >> 7) & 0x1);
+ char buf[OPERAND_WIDTH];
+ char prefix[DSP_PREFIX_WIDTH];
+ size_t len;
+ bfd_boolean is_mod = FALSE;
+ bfd_boolean is_overflow = FALSE;
+ unsigned int reg_brackets[3];
+ bfd_boolean is_w_mx = FALSE;
+ bfd_boolean is_b_mx = FALSE;
+ bfd_boolean imm = FALSE;
+ bfd_boolean is_quickrot64 = FALSE;
+ bfd_boolean conditional = FALSE;
+ const char *cc_flags = NULL;
+ bfd_boolean is_unsigned = FALSE;
+
+ memset (reg_brackets, 0, sizeof (reg_brackets));
+
+ if (template->arg_type & DSP_ARGS_1)
+ {
+ bfd_boolean is_template = FALSE;
+ const char *addr_reg = NULL;
+ bfd_boolean qr = FALSE;
+ bfd_boolean is_acc_add = FALSE;
+ bfd_boolean is_acc_sub = FALSE;
+ bfd_boolean is_acc_zero = FALSE;
+ bfd_boolean is_split8 = (template->arg_type & DSP_ARGS_SPLIT8);
+
+ /* Read DU bit. */
+ data_unit = ((insn_word >> 24) & 0x1) ? UNIT_D1 : UNIT_D0;
+
+ conditional = ((insn_word >> 24) & 0x4);
+
+ /* Templates can't be conditional. */
+ is_template = (((insn_word & 0x02000002) == 0x2) && !conditional);
+
+ if (is_split8)
+ is_mod = (insn_word & 0x80);
+
+ if (template->arg_type & DSP_ARGS_QR)
+ {
+ if (!conditional)
+ is_quickrot64 = ((insn_word >> 5) & 0x1);
+ }
+
+ if (template->arg_type & DSP_ARGS_DACC)
+ {
+ is_mod = (insn_word & 0x8);
+ is_unsigned = (insn_word & 0x40);
+ }
+
+ if (is_template)
+ {
+ is_w_mx = (insn_word & 0x1);
+ is_dual = ((insn_word >> 0x4) & 0x1);
+
+ /* De.r,Dx.r,De.r|ACe.r */
+ if (template->arg_type & DSP_ARGS_ACC2)
+ {
+ is_mod = (insn_word & 0x8);
+ is_overflow = (insn_word & 0x20);
+ }
+
+ /* ACe.e,ACx.r,ACo.e? */
+ if ((template->arg_type & DSP_ARGS_XACC) &&
+ (((insn_word >> 6) & 0x5) == 0x5))
+ {
+ enum metag_unit ac_unit, ao_unit;
+
+ ac_unit = (data_unit == UNIT_D0) ? UNIT_ACC_D0 : UNIT_ACC_D1;
+
+ if (ac_unit == UNIT_ACC_D0)
+ ao_unit = UNIT_ACC_D1;
+ else
+ ao_unit = UNIT_ACC_D0;
+
+ reg_nums[1] = ((insn_word >> 19) & REG_MASK);
+
+ /* These are dummy arguments anyway so the register
+ number does not matter. */
+ reg_names[0] = lookup_dsp_name (16, ac_unit); /* ACe.0 */
+ reg_names[1] = lookup_dsp_name (16, ac_unit); /* ACx.0 */
+ reg_names[2] = lookup_dsp_name (16, ao_unit); /* ACo.0 */
+ }
+ else
+ {
+ /* De.r|ACe.r,Dx.r,De.r */
+ if (template->arg_type & DSP_ARGS_DACC &&
+ ((insn_word & 0x84) != 0))
+ {
+ enum metag_unit ac_unit;
+
+ ac_unit = (data_unit == UNIT_D0) ? UNIT_ACC_D0 : UNIT_ACC_D1;
+ reg_names[0] = lookup_dsp_name (16, ac_unit);
+
+ is_acc_zero = ((insn_word & 0x84) == 0x04);
+ is_acc_add = ((insn_word & 0x84) == 0x80);
+ is_acc_sub = ((insn_word & 0x84) == 0x84);
+ }
+ else
+ reg_names[0] = lookup_any_reg_name (data_unit, 0, FALSE);
+
+ /* These are dummy arguments anyway so the register
+ number does not matter. */
+ reg_names[1] = lookup_any_reg_name (data_unit, 0, TRUE);
+
+ /* De.r,Dx.r,De.r|ACe.r */
+ if ((template->arg_type & DSP_ARGS_ACC2) &&
+ ((insn_word & 0x80) == 0x80))
+ {
+ enum metag_unit ac_unit;
+
+ ac_unit = (data_unit == UNIT_D0) ? UNIT_ACC_D0 : UNIT_ACC_D1;
+ reg_names[2] = lookup_dsp_name (16, ac_unit);
+ }
+ /* Detection of QUICKRoT and accumulator usage uses the
+ same bits. They are mutually exclusive. */
+ else if (ac && (template->arg_type & DSP_ARGS_ACC2))
+ {
+ reg_nums[2] = ((insn_word >> 9) & REG_MASK);
+
+ if (data_unit == UNIT_D0)
+ reg_names[2] = lookup_dsp_name (reg_nums[2], UNIT_ACC_D0);
+ else
+ reg_names[2] = lookup_dsp_name (reg_nums[2], UNIT_ACC_D1);
+ }
+ else
+ {
+ if ((template->arg_type & DSP_ARGS_QR) &&
+ ((insn_word & 0x40) == 0x40))
+ {
+ enum metag_unit aunit;
+ int reg_no;
+
+ if (conditional)
+ reg_no = ((insn_word >> 5) & 0x1);
+ else
+ reg_no = ((insn_word >> 7) & 0x1);
+
+ aunit = (data_unit == UNIT_D0) ? UNIT_A0 : UNIT_A1;
+ addr_reg = lookup_reg_name (aunit, reg_no + 2);
+
+ qr = TRUE;
+ }
+
+ reg_names[2] = lookup_any_reg_name (data_unit, 0, TRUE);
+ }
+ }
+
+ if (qr)
+ {
+ len = snprintf (buf, OPERAND_WIDTH, "%s,%s,%s,%s",
+ reg_names[0], reg_names[1], reg_names[2],
+ addr_reg);
+ }
+ else
+ {
+ len = snprintf (buf, OPERAND_WIDTH, "%s,%s,%s%s%s",
+ reg_names[0], reg_names[1],
+ reg_brackets[2] ? "[" : "",
+ reg_names[2], reg_brackets[2] ? "]" : "");
+ }
+
+ decode_template_definition (insn_word, buf + len,
+ OPERAND_WIDTH - len);
+ }
+ else /* Not a template definiton. */
+ {
+ reg_nums[0] = ((insn_word >> 19) & REG_MASK);
+ reg_nums[1] = ((insn_word >> 14) & REG_MASK);
+ reg_nums[2] = ((insn_word >> 9) & REG_MASK);
+
+ imm = (((insn_word >> 24) & 0x2) && (template->arg_type & DSP_ARGS_IMM));
+
+ if (imm)
+ is_dual = (insn_word & 0x4);
+ else if (!conditional)
+ is_dual = (insn_word & 0x10);
+ else
+ cc_flags = lookup_scc_flags ((insn_word >> 1) & CC_MASK);
+
+ /* De.r,Dx.r,De.r|ACe.r */
+ if (template->arg_type & DSP_ARGS_ACC2)
+ {
+ is_mod = (insn_word & 0x8);
+ is_overflow = (insn_word & 0x20);
+ }
+
+ if (template->arg_type & DSP_ARGS_SPLIT8)
+ {
+ is_overflow = (insn_word & 0x20);
+ }
+
+ /* ACe.e,ACx.r,ACo.e? */
+ if ((template->arg_type & DSP_ARGS_XACC) &&
+ (((insn_word >> 6) & 0x5) == 0x5))
+ {
+ enum metag_unit ac_unit, ao_unit;
+
+ ac_unit = (data_unit == UNIT_D0) ? UNIT_ACC_D0 : UNIT_ACC_D1;
+
+ if (ac_unit == UNIT_ACC_D0)
+ ao_unit = UNIT_ACC_D1;
+ else
+ ao_unit = UNIT_ACC_D0;
+
+ reg_nums[1] = ((insn_word >> 19) & REG_MASK);
+ reg_names[0] = lookup_dsp_name (reg_nums[1], ac_unit);
+ reg_names[1] = lookup_dsp_name (reg_nums[1], ac_unit);
+ reg_names[2] = lookup_dsp_name (reg_nums[1], ao_unit);
+ }
+ else
+ {
+ bfd_boolean o2r = (insn_word & 0x1);
+
+ /* De.r|ACe.r,Dx.r,De.r */
+ if ((template->arg_type & DSP_ARGS_DACC) &&
+ ((insn_word & 0x84) != 0))
+ {
+ enum metag_unit ac_unit;
+
+ ac_unit = (data_unit == UNIT_D0) ? UNIT_ACC_D0 : UNIT_ACC_D1;
+ reg_names[0] = lookup_dsp_name (reg_nums[0], ac_unit);
+
+ is_acc_zero = ((insn_word & 0x84) == 0x04);
+ is_acc_add = ((insn_word & 0x84) == 0x80);
+ is_acc_sub = ((insn_word & 0x84) == 0x84);
+ }
+ else if (conditional)
+ {
+ reg_names[0] = lookup_reg_name (data_unit, reg_nums[0]);
+ }
+ else
+ {
+ reg_names[0] = lookup_any_reg_name (data_unit,
+ reg_nums[0], FALSE);
+ if (reg_nums[0] > 15)
+ reg_brackets[0] = 1;
+ }
+
+ if (imm)
+ {
+ reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[0], TRUE);
+
+ if (reg_brackets[0])
+ reg_brackets[1] = 1;
+ }
+ else
+ {
+ if (is_split8 && is_mod)
+ {
+ reg_names[1] = lookup_reg_name (data_unit, reg_nums[1]);
+ }
+ else
+ {
+ reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[1], TRUE);
+
+ if (reg_nums[1] > 15)
+ reg_brackets[1] = 1;
+ }
+ }
+
+ /* Detection of QUICKRoT and accumulator usage uses the
+ same bits. They are mutually exclusive. */
+ if (ac && (template->arg_type & DSP_ARGS_ACC2))
+ {
+ if (data_unit == UNIT_D0)
+ reg_names[2] = lookup_dsp_name (reg_nums[2], UNIT_ACC_D0);
+ else
+ reg_names[2] = lookup_dsp_name (reg_nums[2], UNIT_ACC_D1);
+ }
+
+ else
+ {
+ if ((template->arg_type & DSP_ARGS_QR) &&
+ ((insn_word & 0x40) == 0x40))
+ {
+ enum metag_unit aunit;
+ int reg_no;
+
+ if (conditional)
+ reg_no = ((insn_word >> 5) & 0x1);
+ else
+ reg_no = ((insn_word >> 7) & 0x1);
+
+ aunit = (data_unit == UNIT_D0) ? UNIT_A0 : UNIT_A1;
+ addr_reg = lookup_reg_name (aunit, reg_no + 2);
+
+ qr = TRUE;
+ }
+
+ if (o2r)
+ reg_names[2] = lookup_o2r (data_unit, reg_nums[2]);
+ else
+ {
+ /* Can't use a DSPRAM reg if both QD and L1 are
+ set on a QUICKRoT instruction or if we're a
+ split 8. */
+ if (((template->arg_type & DSP_ARGS_QR)
+ && ((insn_word & 0x30) == 0x30 && !conditional)) ||
+ (is_split8 && is_mod))
+ reg_names[2] = lookup_reg_name (data_unit, reg_nums[2]);
+ else
+ {
+ reg_names[2] = lookup_any_reg_name (data_unit,
+ reg_nums[2], TRUE);
+ if (reg_nums[2] > 15)
+ reg_brackets[2] = 1;
+ }
+ }
+ }
+ }
+
+ if (qr)
+ {
+ len = snprintf (buf, OPERAND_WIDTH, "%s%s%s,%s%s%s,%s%s%s,%s",
+ reg_brackets[0] ? "[" : "",
+ reg_names[0], reg_brackets[0] ? "]" : "",
+ reg_brackets[1] ? "[" : "",
+ reg_names[1], reg_brackets[1] ? "]" : "",
+ reg_brackets[2] ? "[" : "",
+ reg_names[2], reg_brackets[2] ? "]" : "",
+ addr_reg);
+ }
+ else
+ {
+ if (imm)
+ {
+ /* Conform to the embedded assembler's policy of
+ printing negative numbers as decimal and positive
+ as hex. */
+ int value = ((insn_word >> 3) & IMM16_MASK);
+
+ if ((value & 0x8000) || value == 0)
+ {
+ value = sign_extend (value, IMM16_BITS);
+ len = snprintf (buf, OPERAND_WIDTH, "%s%s%s,%s%s%s,#%d",
+ reg_brackets[0] ? "[" : "",
+ reg_names[0], reg_brackets[0] ? "]" : "",
+ reg_brackets[1] ? "[" : "",
+ reg_names[1], reg_brackets[1] ? "]" : "",
+ value);
+ }
+ else
+ {
+ len = snprintf (buf, OPERAND_WIDTH, "%s%s%s,%s%s%s,#%#x",
+ reg_brackets[0] ? "[" : "",
+ reg_names[0], reg_brackets[0] ? "]" : "",
+ reg_brackets[1] ? "[" : "",
+ reg_names[1], reg_brackets[1] ? "]" : "",
+ value);
+ }
+ }
+ else
+ {
+ len = snprintf (buf, OPERAND_WIDTH, "%s%s%s,%s%s%s,%s%s%s",
+ reg_brackets[0] ? "[" : "",
+ reg_names[0], reg_brackets[0] ? "]" : "",
+ reg_brackets[1] ? "[" : "", reg_names[1],
+ reg_brackets[1] ? "]" : "",
+ reg_brackets[2] ? "[" : "",
+ reg_names[2], reg_brackets[2] ? "]" : "");
+ }
+ }
+ }
+
+ snprintf (prefix, DSP_PREFIX_WIDTH, "D%s%s%s%s%s%s%s%s%s%s%s%s",
+ cc_flags ? cc_flags : "",
+ is_dual ? "L" : "",
+ is_quickrot64 ? "Q" : "",
+ is_unsigned ? "U" : "",
+ is_mod ? "M" : "",
+ is_acc_zero ? "Z" : "",
+ is_acc_add ? "P" : "", is_acc_sub ? "N" : "",
+ is_overflow ? "O" : "",
+ is_w_mx ? "W" : "",
+ is_b_mx ? "B" : "",
+ is_template ? "T" : "");
+ }
+ else if (template->arg_type & DSP_ARGS_2) /* Group 2. */
+ {
+ bfd_boolean is_template;
+ bfd_boolean o2r = FALSE;
+ int major = MAJOR_OPCODE (template->meta_opcode);
+ bfd_boolean is_neg_or_mov = (major == OPC_ADD || major == OPC_SUB);
+ bfd_boolean is_cmp_tst = ((major == OPC_CMP) &&
+ ((insn_word & 0x0000002c) == 0));
+ bfd_boolean is_fpu_mov = template->insn_type == INSN_DSP_FPU;
+ bfd_boolean to_fpu = (template->meta_opcode >> 7) & 0x1;
+
+ if (major == OPC_9)
+ imm = (insn_word & 0x2);
+ else if (template->arg_type & DSP_ARGS_IMM)
+ imm = ((insn_word >> 25) & 0x1);
+
+ is_template = (((insn_word & 0x02000002) == 0x2) &&
+ major != OPC_9);
+
+ if (imm)
+ is_dual = ((insn_word >> 0x2) & 0x1);
+ else
+ is_dual = ((insn_word >> 0x4) & 0x1);
+
+ /* MOV and XSD[BW] do not have o2r. */
+ if (major != OPC_9 && major != OPC_MISC)
+ o2r = (insn_word & 0x1);
+
+ if (is_neg_or_mov)
+ {
+ is_mod = (insn_word & 0x8);
+ is_overflow = (insn_word & 0x20);
+ }
+
+ /* XSD */
+ if (major == OPC_MISC)
+ data_unit = (insn_word & 0x1) ? UNIT_D1 : UNIT_D0;
+ else
+ data_unit = ((insn_word >> 24) & 0x1) ? UNIT_D1 : UNIT_D0;
+
+ /* Check for NEG,MOV,ABS,FFB, etc. */
+ if (is_neg_or_mov || !is_cmp_tst || imm ||
+ MAJOR_OPCODE (insn_word) == OPC_9 ||
+ MAJOR_OPCODE (insn_word) == OPC_MISC)
+ reg_nums[0] = ((insn_word >> 19) & REG_MASK);
+ else
+ reg_nums[0] = ((insn_word >> 14) & REG_MASK);
+
+ if (is_template)
+ {
+ is_w_mx = (insn_word & 0x1);
+
+ /* These are dummy arguments anyway so the register number
+ does not matter. */
+ if (is_fpu_mov)
+ {
+ if (to_fpu)
+ {
+ reg_names[0] = lookup_reg_name (UNIT_FX, 0);
+ reg_names[1] = lookup_reg_name (data_unit, 0);
+ }
+ else
+ {
+ reg_names[0] = lookup_reg_name (data_unit, 0);
+ reg_names[1] = lookup_reg_name (UNIT_FX, 0);
+ }
+ }
+ else
+ {
+ reg_names[0] = lookup_reg_name (data_unit, 0);
+ reg_names[1] = lookup_reg_name (data_unit, 0);
+ }
+
+ len = snprintf (buf, OPERAND_WIDTH, "%s,%s",
+ reg_names[0], reg_names[1]);
+
+ decode_template_definition (insn_word, buf + len,
+ OPERAND_WIDTH - len);
+ }
+ else
+ {
+ if (imm)
+ {
+ /* Conform to the embedded assembler's policy of
+ printing negative numbers as decimal and positive as
+ hex. */
+ unsigned int value = ((insn_word >> 3) & IMM16_MASK);
+
+ if (major == OPC_9)
+ {
+ data_unit = (insn_word & 0x1) ? UNIT_D1 : UNIT_D0;
+ is_dual = (insn_word & 0x4);
+
+ reg_names[0] = __lookup_dsp_name (reg_nums[0], data_unit);
+ }
+ else
+ {
+ reg_names[0] = lookup_any_reg_name (data_unit, reg_nums[0], TRUE);
+ if (reg_nums[0] > 15)
+ reg_brackets[0] = 1;
+ }
+
+ if ((value & 0x8000) || value == 0)
+ {
+ value = sign_extend (value, IMM16_BITS);
+ snprintf (buf, OPERAND_WIDTH, "%s%s%s,#%d",
+ reg_brackets[0] ? "[" : "",
+ reg_names[0], reg_brackets[0] ? "]" : "",
+ value);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s%s%s,#0x%x",
+ reg_brackets[0] ? "[" : "",
+ reg_names[0], reg_brackets[0] ? "]" : "",
+ value);
+ }
+ }
+ else
+ {
+ if (is_neg_or_mov || is_cmp_tst)
+ reg_nums[1] = ((insn_word >> 9) & REG_MASK);
+ else
+ reg_nums[1] = ((insn_word >> 14) & REG_MASK);
+
+ if (major == OPC_9)
+ {
+ is_dual = (insn_word & 0x4);
+ data_unit = (insn_word & 0x1) ? UNIT_D1 : UNIT_D0;
+
+ if (MINOR_OPCODE (template->meta_opcode) == 0x1)
+ reg_names[0] = __lookup_dsp_name (reg_nums[0], data_unit);
+ else
+ reg_names[0] = lookup_reg_name (data_unit, reg_nums[0]);
+ }
+ else
+ {
+ unsigned int reg0_unit = data_unit;
+
+ if (is_fpu_mov && to_fpu)
+ reg0_unit = UNIT_FX;
+
+ reg_names[0] = lookup_any_reg_name (reg0_unit, reg_nums[0],
+ (!is_neg_or_mov && is_cmp_tst));
+ if (reg_nums[0] > 15)
+ reg_brackets[0] = 1;
+ }
+
+ if (o2r)
+ reg_names[1] = lookup_o2r (data_unit, reg_nums[1]);
+ else
+ {
+ /* Check for accumulator argument. */
+ if (is_neg_or_mov && ((insn_word & 0x80) == 0x80))
+ {
+ if (data_unit == UNIT_D0)
+ reg_names[1] = lookup_dsp_name (reg_nums[1], UNIT_ACC_D0);
+ else
+ reg_names[1] = lookup_dsp_name (reg_nums[1], UNIT_ACC_D1);
+ }
+ else
+ {
+ if (major == OPC_9)
+ {
+ if (MINOR_OPCODE (template->meta_opcode) == 0x1)
+ {
+ reg_names[1] = lookup_reg_name (data_unit, reg_nums[1]);
+ }
+ else
+ {
+ enum metag_unit u;
+
+ u = (insn_word & 0x1) ? UNIT_RAM_D1 : UNIT_RAM_D0;
+ reg_names[1] = lookup_dsp_name (reg_nums[1], u);
+ }
+ }
+ else
+ {
+ reg_names[1] = lookup_any_reg_name (data_unit,
+ reg_nums[1], TRUE);
+ if (reg_nums[1] > 15)
+ reg_brackets[1] = 1;
+ }
+ }
+ }
+
+ snprintf (buf, OPERAND_WIDTH, "%s%s%s,%s%s%s",
+ reg_brackets[0] ? "[" : "", reg_names[0],
+ reg_brackets[0] ? "]" : "",
+ reg_brackets[1] ? "[" : "", reg_names[1],
+ reg_brackets[1] ? "]" : "");
+ }
+ }
+
+ snprintf (prefix, DSP_PREFIX_WIDTH, "D%s%s%s%s%s%s",
+ is_fpu_mov ? "F" : "",
+ is_dual ? "L" : "",
+ is_mod ? "M" : "", is_overflow ? "O" : "",
+ is_w_mx ? "W" : "",
+ is_template ? "T" : "");
+ }
+ else /* Group 3. */
+ {
+ /* If both the C and CA bits are set, then the Rd register can
+ be in any unit. Figure out which unit from the Ud field. */
+ bfd_boolean all_units = (((insn_word) & 0x04000020) == 0x04000020);
+ enum metag_unit ud_unit = ((insn_word >> 1) & UNIT_MASK);
+ enum metag_unit ram_unit, acc_unit;
+ bfd_boolean round = FALSE;
+ bfd_boolean clamp9 = FALSE;
+ bfd_boolean clamp8 = FALSE;
+ bfd_boolean is_template = ((insn_word & 0x04000002) == 0x2);
+
+ imm = ((insn_word >> 25) & 0x1);
+ ac = (insn_word & 0x1);
+
+ conditional = (MINOR_OPCODE (insn_word) & 0x4);
+
+ /* Check for conditional and not Condition Always. */
+ if (conditional && !(insn_word & 0x20))
+ cc_flags = lookup_scc_flags ((insn_word >> 1) & CC_MASK);
+ else if (!(conditional && (insn_word & 0x20)))
+ is_dual = ((insn_word >> 0x4) & 0x1);
+
+ /* Conditional instructions don't have the L1 or RSPP fields. */
+ if ((insn_word & 0x04000000) == 0)
+ {
+ round = (((insn_word >> 2) & 0x3) == 0x1);
+ clamp9 = (((insn_word >> 2) & 0x3) == 0x2);
+ clamp8 = (((insn_word >> 2) & 0x3) == 0x3);
+ }
+
+ /* Read DU bit. */
+ data_unit = ((insn_word >> 24) & 0x1) ? UNIT_D1 : UNIT_D0;
+ reg_nums[0] = ((insn_word >> 19) & REG_MASK);
+ reg_nums[1] = ((insn_word >> 14) & REG_MASK);
+
+ ram_unit = (data_unit == UNIT_D0) ? UNIT_RAM_D0 : UNIT_RAM_D1;
+ acc_unit = (data_unit == UNIT_D0) ? UNIT_ACC_D0 : UNIT_ACC_D1;
+
+ if (all_units)
+ reg_names[0] = lookup_reg_name (ud_unit, reg_nums[0]);
+ else
+ {
+ if (conditional)
+ reg_names[0] = lookup_reg_name (data_unit, reg_nums[0]);
+ else
+ {
+ reg_names[0] = lookup_any_reg_name (data_unit, reg_nums[0], FALSE);
+ if (reg_nums[0] > 15)
+ reg_brackets[0] = 1;
+ }
+ }
+
+ if (ac)
+ {
+ reg_names[1] = lookup_dsp_name (reg_nums[1], acc_unit);
+ }
+ else
+ {
+ reg_names[1] = lookup_any_reg_name (data_unit, reg_nums[1], TRUE);
+ if (reg_nums[1] > 15)
+ reg_brackets[1] = 1;
+ }
+
+ if (imm)
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s%s%s,%s%s%s,#%#x",
+ reg_brackets[0] ? "[" : "",
+ reg_names[0], reg_brackets[0] ? "]" : "",
+ reg_brackets[1] ? "[" : "",
+ reg_names[1], reg_brackets[1] ? "]" : "",
+ ((insn_word >> 9) & IMM5_MASK));
+ }
+ else
+ {
+ reg_nums[2] = ((insn_word >> 9) & REG_MASK);
+
+ reg_names[2] = lookup_any_reg_name (data_unit, reg_nums[2], TRUE);
+
+ if (reg_nums[2] > 15)
+ reg_brackets[2] = 1;
+
+ if (is_template)
+ {
+ bfd_boolean load = ((insn_word >> 13) & 0x1);
+ bfd_boolean dspram = (((insn_word >> 17) & 0x3) == 0x3);
+ const char *tname[1];
+ unsigned int tidx = ((insn_word >> 9) & TEMPLATE_REGS_MASK);
+ enum metag_unit au;
+ unsigned int addr_reg_nums[2];
+ const char *addr_reg_names[2];
+ const char *post_op = "";
+ const char *join_op = "";
+
+ is_w_mx = ((insn_word >> 5) & 0x1);
+
+ tname[0] = lookup_dsp_name (tidx, UNIT_DT);
+
+ /* These are dummy arguments anyway */
+ reg_names[0] = lookup_reg_name (data_unit, 0);
+ if (ac)
+ reg_names[1] = lookup_dsp_name (16, acc_unit);
+ else
+ reg_names[1] = lookup_reg_name (data_unit, 0);
+ reg_names[2] = lookup_reg_name (data_unit, 0);
+
+ addr_reg_names[1] = "";
+
+ if (dspram)
+ {
+ ram_unit = (data_unit == UNIT_D0) ? UNIT_RAM_D0 : UNIT_RAM_D1;
+ addr_reg_nums[0] = ((insn_word >> 19) & REG_MASK);
+ addr_reg_names[0] = lookup_dspram_name (addr_reg_nums[0],
+ ram_unit, load);
+ }
+ else
+ {
+ bfd_boolean im = (((insn_word >> 18) & 0x1) != 0);
+
+ au = (((insn_word >> 23) & 0x1) == 0) ? UNIT_A0 : UNIT_A1;
+ addr_reg_nums[0] = ((insn_word >> 19) & DSP_REG_MASK);
+
+ addr_reg_names[0] = lookup_reg_name (au, addr_reg_nums[0]);
+
+ if (im)
+ {
+ unsigned int im_value = ((insn_word >> 14) & 0x3);
+
+ switch (im_value)
+ {
+ case 0x1:
+ post_op = "++";
+ break;
+ case 0x3:
+ post_op = "--";
+ break;
+ }
+ }
+ else
+ {
+ addr_reg_nums[1] = ((insn_word >> 14) & DSP_REG_MASK);
+ addr_reg_names[1] = lookup_reg_name (au, addr_reg_nums[1]);
+ join_op = "+";
+ post_op = "++";
+ }
+ }
+
+ if (load)
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s %s,[%s%s%s%s]",
+ reg_names[0], reg_names[1], reg_names[2],
+ tname[0], addr_reg_names[0], join_op,
+ addr_reg_names[1], post_op);
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s,%s,%s [%s%s%s%s],%s",
+ reg_names[0], reg_names[1], reg_names[2],
+ addr_reg_names[0], join_op, addr_reg_names[1],
+ post_op, tname[0]);
+ }
+ }
+ else
+ {
+ snprintf (buf, OPERAND_WIDTH, "%s%s%s,%s%s%s,%s%s%s",
+ reg_brackets[0] ? "[" : "",
+ reg_names[0], reg_brackets[0] ? "]" : "",
+ reg_brackets[1] ? "[" : "",
+ reg_names[1], reg_brackets[1] ? "]" : "",
+ reg_brackets[2] ? "[" : "",
+ reg_names[2], reg_brackets[2] ? "]" : "");
+ }
+ }
+
+ snprintf (prefix, DSP_PREFIX_WIDTH, "D%s%s%s%s%s%s%s",
+ cc_flags ? cc_flags : "",
+ is_dual ? "L" : "", clamp9 ? "G" : "",
+ clamp8 ? "B" : "", round ? "R" : "",
+ is_w_mx ? "W" : "",
+ is_template ? "T" : "");
+ }
+
+ print_insn (outf, prefix, template->name, buf);
+
+}
+
+typedef void (*insn_printer)(unsigned int, bfd_vma, const insn_template *,
+ disassemble_info *);
+
+/* Printer table. */
+static const insn_printer insn_printers[ENC_MAX] =
+ {
+ [ENC_NONE] = print_none,
+ [ENC_MOV_U2U] = print_mov_u2u,
+ [ENC_MOV_PORT] = print_mov_port,
+ [ENC_MMOV] = print_mmov,
+ [ENC_MDRD] = print_mdrd,
+ [ENC_MOVL_TTREC] = print_movl_ttrec,
+ [ENC_GET_SET] = print_get_set,
+ [ENC_GET_SET_EXT] = print_get_set_ext,
+ [ENC_MGET_MSET] = print_mget_mset,
+ [ENC_COND_SET] = print_cond_set,
+ [ENC_XFR] = print_xfr,
+ [ENC_MOV_CT] = print_mov_ct,
+ [ENC_SWAP] = print_swap,
+ [ENC_JUMP] = print_jump,
+ [ENC_CALLR] = print_callr,
+ [ENC_ALU] = print_alu,
+ [ENC_SHIFT] = print_shift,
+ [ENC_MIN_MAX] = print_min_max,
+ [ENC_BITOP] = print_bitop,
+ [ENC_CMP] = print_cmp,
+ [ENC_BRANCH] = print_branch,
+ [ENC_KICK] = print_mov_u2u,
+ [ENC_SWITCH] = print_switch,
+ [ENC_CACHER] = print_cacher,
+ [ENC_CACHEW] = print_cachew,
+ [ENC_ICACHE] = print_icache,
+ [ENC_LNKGET] = print_lnkget,
+ [ENC_FMOV] = print_fmov,
+ [ENC_FMMOV] = print_fmmov,
+ [ENC_FMOV_DATA] = print_fmov_data,
+ [ENC_FMOV_I] = print_fmov_i,
+ [ENC_FPACK] = print_fpack,
+ [ENC_FSWAP] = print_fswap,
+ [ENC_FCMP] = print_fcmp,
+ [ENC_FMINMAX] = print_fminmax,
+ [ENC_FCONV] = print_fconv,
+ [ENC_FCONVX] = print_fconvx,
+ [ENC_FBARITH] = print_fbarith,
+ [ENC_FEARITH] = print_fearith,
+ [ENC_FREC] = print_frec,
+ [ENC_FSIMD] = print_fsimd,
+ [ENC_FGET_SET_ACF] = print_fget_set_acf,
+ [ENC_DGET_SET] = print_dget_set,
+ [ENC_DTEMPLATE] = print_dtemplate,
+ [ENC_DALU] = print_dalu,
+ };
+
+/* Entry point for instruction printing. */
+int
+print_insn_metag (bfd_vma pc, disassemble_info *outf)
+{
+ bfd_byte buf[4];
+ unsigned int insn_word;
+ size_t i;
+
+ (*outf->read_memory_func) (pc & ~0x03, buf, 4, outf);
+ insn_word = bfd_getl32 (buf);
+
+ for (i = 0; i < sizeof(metag_optab)/sizeof(metag_optab[0]); i++)
+ {
+ const insn_template *template = &metag_optab[i];
+
+ if ((insn_word & template->meta_mask) == template->meta_opcode)
+ {
+ enum insn_encoding encoding = template->encoding;
+ insn_printer printer = insn_printers[encoding];
+
+ if (printer)
+ printer (insn_word, pc, template, outf);
+
+ return 4;
+ }
+ }
+
+ return 4;
+}
projects / binutils-gdb.git / commitdiff