i965: Pass a cfg pointer to generate_{code,assembly}.

The loop over all instructions is now two-fold, over all of the blocks
and all of the instructions in each block.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index 24358a806dfba2b2d11945e93c9a7df6860f6019..82ece732d184100a0904317df0585f40c331f25d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -24,6 +24,7 @@
 #include "util/ralloc.h"
 #include "brw_blorp_blit_eu.h"
 #include "brw_blorp.h"
+#include "brw_cfg.h"
 
 brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw,
                                            bool debug_flag)
@@ -43,7 +44,8 @@ brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
 const unsigned *
 brw_blorp_eu_emitter::get_program(unsigned *program_size)
 {
-   return generator.generate_assembly(NULL, &insts, program_size);
+   cfg_t cfg(&insts);
+   return generator.generate_assembly(NULL, &cfg, program_size);
 }
 
 /**

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 20485aa40369f60b9643101c8dbb3f88db079446..5c70f500896b4e03b3124eccf38ba61723e10d83 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3355,6 +3355,8 @@ fs_visitor::run()
     */
    assert(sanity_param_count == fp->Base.Parameters->NumParameters);
 
+   calculate_cfg();
+
    return !failed;
 }
 
@@ -3398,7 +3400,7 @@ brw_wm_fs_emit(struct brw_context *brw,
       return NULL;
    }
 
-   exec_list *simd16_instructions = NULL;
+   cfg_t *simd16_cfg = NULL;
    fs_visitor v2(brw, mem_ctx, key, prog_data, prog, fp, 16);
    if (brw->gen >= 5 && likely(!(INTEL_DEBUG & DEBUG_NO16))) {
       if (!v.simd16_unsupported) {
@@ -3408,7 +3410,7 @@ brw_wm_fs_emit(struct brw_context *brw,
             perf_debug("SIMD16 shader failed to compile, falling back to "
                        "SIMD8 at a 10-20%% performance cost: %s", v2.fail_msg);
          } else {
-            simd16_instructions = &v2.instructions;
+            simd16_cfg = v2.cfg;
          }
       } else {
          perf_debug("SIMD16 shader unsupported, falling back to "
@@ -3416,20 +3418,20 @@ brw_wm_fs_emit(struct brw_context *brw,
       }
    }
 
-   exec_list *simd8_instructions;
+   cfg_t *simd8_cfg;
    int no_simd8 = (INTEL_DEBUG & DEBUG_NO8) || brw->no_simd8;
-   if (no_simd8 && simd16_instructions) {
-      simd8_instructions = NULL;
+   if (no_simd8 && simd16_cfg) {
+      simd8_cfg = NULL;
       prog_data->no_8 = true;
    } else {
-      simd8_instructions = &v.instructions;
+      simd8_cfg = v.cfg;
       prog_data->no_8 = false;
    }
 
    const unsigned *assembly = NULL;
    fs_generator g(brw, mem_ctx, key, prog_data, prog, fp,
                   v.runtime_check_aads_emit, INTEL_DEBUG & DEBUG_WM);
-   assembly = g.generate_assembly(simd8_instructions, simd16_instructions,
+   assembly = g.generate_assembly(simd8_cfg, simd16_cfg,
                                   final_assembly_size);
 
    if (unlikely(brw->perf_debug) && shader) {

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 9e5b5d7eff38037962cb48504d0c736d645c573c..d0422c3d4130fc5078cf1a3377efaada236f363f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -580,12 +580,12 @@ public:
                 bool debug_flag);
    ~fs_generator();
 
-   const unsigned *generate_assembly(exec_list *simd8_instructions,
-                                     exec_list *simd16_instructions,
+   const unsigned *generate_assembly(const cfg_t *simd8_cfg,
+                                     const cfg_t *simd16_cfg,
                                      unsigned *assembly_size);
 
 private:
-   void generate_code(exec_list *instructions);
+   void generate_code(const cfg_t *cfg);
    void fire_fb_write(fs_inst *inst,
                       GLuint base_reg,
                       struct brw_reg implied_header,

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index a2430034086079947eb8fb38079653c7aa451ef8..0ed0ee357990bfea19494bee82697111d8c0406b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1480,18 +1480,14 @@ fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
 }
 
 void
-fs_generator::generate_code(exec_list *instructions)
+fs_generator::generate_code(const cfg_t *cfg)
 {
    int start_offset = p->next_insn_offset;
 
    struct annotation_info annotation;
    memset(&annotation, 0, sizeof(annotation));
 
-   cfg_t *cfg = NULL;
-   if (unlikely(debug_flag))
-      cfg = new(mem_ctx) cfg_t(instructions);
-
-   foreach_in_list(fs_inst, inst, instructions) {
+   foreach_block_and_inst (block, fs_inst, inst, cfg) {
       struct brw_reg src[3], dst;
       unsigned int last_insn_offset = p->next_insn_offset;
 
@@ -1983,18 +1979,18 @@ fs_generator::generate_code(exec_list *instructions)
 }
 
 const unsigned *
-fs_generator::generate_assembly(exec_list *simd8_instructions,
-                                exec_list *simd16_instructions,
+fs_generator::generate_assembly(const cfg_t *simd8_cfg,
+                                const cfg_t *simd16_cfg,
                                 unsigned *assembly_size)
 {
-   assert(simd8_instructions || simd16_instructions);
+   assert(simd8_cfg || simd16_cfg);
 
-   if (simd8_instructions) {
+   if (simd8_cfg) {
       dispatch_width = 8;
-      generate_code(simd8_instructions);
+      generate_code(simd8_cfg);
    }
 
-   if (simd16_instructions) {
+   if (simd16_cfg) {
       /* align to 64 byte boundary. */
       while (p->next_insn_offset % 64) {
          brw_NOP(p);
@@ -2006,7 +2002,7 @@ fs_generator::generate_assembly(exec_list *simd8_instructions,
       brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
 
       dispatch_width = 16;
-      generate_code(simd16_instructions);
+      generate_code(simd16_cfg);
    }
 
    return brw_get_program(p, assembly_size);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index e49cdb28d358d88cc4653eacbb5b9452510a89e0..bfb0fba39871f7e6effe03a73d6cf4df92920b2f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1742,6 +1742,8 @@ vec4_visitor::run()
     */
    assert(sanity_param_count == prog->Parameters->NumParameters);
 
+   calculate_cfg();
+
    return !failed;
 }
 
@@ -1794,7 +1796,7 @@ brw_vs_emit(struct brw_context *brw,
    const unsigned *assembly = NULL;
    vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base,
                     mem_ctx, INTEL_DEBUG & DEBUG_VS);
-   assembly = g.generate_assembly(&v.instructions, final_assembly_size);
+   assembly = g.generate_assembly(v.cfg, final_assembly_size);
 
    if (unlikely(brw->perf_debug) && shader) {
       if (shader->compiled_once) {

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index c59d24f403b0f5a0b818bf89f9189747dea8c0e2..517eab13c1b6824e4042cd36c3c9f42f34813bbe 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -622,10 +622,10 @@ public:
                   bool debug_flag);
    ~vec4_generator();
 
-   const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
+   const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
 
 private:
-   void generate_code(exec_list *instructions);
+   void generate_code(const cfg_t *cfg);
    void generate_vec4_instruction(vec4_instruction *inst,
                                   struct brw_reg dst,
                                   struct brw_reg *src);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 1b1e64773e62b2a46043951a0f4a0591fb9ade77..a5c2d1a2f8cdbeed2b847a25762771013ab60758 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1314,16 +1314,12 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
 }
 
 void
-vec4_generator::generate_code(exec_list *instructions)
+vec4_generator::generate_code(const cfg_t *cfg)
 {
    struct annotation_info annotation;
    memset(&annotation, 0, sizeof(annotation));
 
-   cfg_t *cfg = NULL;
-   if (unlikely(debug_flag))
-      cfg = new(mem_ctx) cfg_t(instructions);
-
-   foreach_in_list(vec4_instruction, inst, instructions) {
+   foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
       struct brw_reg src[3], dst;
 
       if (unlikely(debug_flag))
@@ -1383,11 +1379,11 @@ vec4_generator::generate_code(exec_list *instructions)
 }
 
 const unsigned *
-vec4_generator::generate_assembly(exec_list *instructions,
+vec4_generator::generate_assembly(const cfg_t *cfg,
                                   unsigned *assembly_size)
 {
    brw_set_default_access_mode(p, BRW_ALIGN_16);
-   generate_code(instructions);
+   generate_code(cfg);
 
    return brw_get_program(p, assembly_size);
 }

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index b7995adab3af3065d22bfdc04d30da328a6f05ba..0b95002ca9f950446cc0b6c5e3d687c3cfb4849a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -612,12 +612,12 @@ generate_assembly(struct brw_context *brw,
                   struct gl_program *prog,
                   struct brw_vec4_prog_data *prog_data,
                   void *mem_ctx,
-                  exec_list *instructions,
+                  const cfg_t *cfg,
                   unsigned *final_assembly_size)
 {
    vec4_generator g(brw, shader_prog, prog, prog_data, mem_ctx,
                     INTEL_DEBUG & DEBUG_GS);
-   return g.generate_assembly(instructions, final_assembly_size);
+   return g.generate_assembly(cfg, final_assembly_size);
 }
 
 extern "C" const unsigned *
@@ -645,7 +645,7 @@ brw_gs_emit(struct brw_context *brw,
       vec4_gs_visitor v(brw, c, prog, mem_ctx, true /* no_spills */);
       if (v.run()) {
          return generate_assembly(brw, prog, &c->gp->program.Base,
-                                  &c->prog_data.base, mem_ctx, &v.instructions,
+                                  &c->prog_data.base, mem_ctx, v.cfg,
                                   final_assembly_size);
       }
    }
@@ -670,7 +670,7 @@ brw_gs_emit(struct brw_context *brw,
    }
 
    return generate_assembly(brw, prog, &c->gp->program.Base, &c->prog_data.base,
-                            mem_ctx, &v.instructions, final_assembly_size);
+                            mem_ctx, v.cfg, final_assembly_size);
 }
 
 

diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.c b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
index 5aee45850ea97815d465fe0f4519190a7d133146..953a60ad1ecc6c6b6a307c87ae56f66d184d0346 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_asm_annotation.c
+++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
@@ -92,7 +92,7 @@ dump_assembly(void *assembly, int num_annotations, struct annotation *annotation
 }
 
 void annotate(struct brw_context *brw,
-              struct annotation_info *annotation, struct cfg_t *cfg,
+              struct annotation_info *annotation, const struct cfg_t *cfg,
               struct backend_instruction *inst, unsigned offset)
 {
    if (annotation->ann_size <= annotation->ann_count) {

diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.h b/src/mesa/drivers/dri/i965/intel_asm_annotation.h
index 79f337211b10f884effc6ee6396a0b40c191d3d2..d80f32052817dc06889caf761328475df99f8bb3 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_asm_annotation.h
+++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.h
@@ -64,7 +64,7 @@ dump_assembly(void *assembly, int num_annotations, struct annotation *annotation
 
 void
 annotate(struct brw_context *brw,
-         struct annotation_info *annotation, struct cfg_t *cfg,
+         struct annotation_info *annotation, const struct cfg_t *cfg,
          struct backend_instruction *inst, unsigned offset);
 void
 annotation_finalize(struct annotation_info *annotation, unsigned offset);