mem-ruby: MESI_Three_Level fix L1 MRU absence

The L1 cache is updating the MRU tag after acessing a cache line.
This patch updates MRU for cases when the L0 cache loads/stores
a line from/to the L1 cache.

Change-Id: I1f0ccef26b3c7614dc865a38c39145840dabfd01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24258
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
index a2f2d807bc3a3ce0289b740d3610f2a42e39ca7f..eec07ca31d5be8f016b25c5181ac03c44e4f7717 100644 (file)
--- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
@@ -617,6 +617,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
           out_msg.DataBlk := cache_entry.DataBlk;
           out_msg.MessageSize := MessageSizeType:Response_Data;
       }
+
+      cache.setMRU(address);
   }
 
   action(hh_xdata_to_l0, "\h", desc="If not prefetch, notify sequencer that store completed.") {
@@ -633,6 +635,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
 
           //cache_entry.Dirty := true;
       }
+
+      cache.setMRU(address);
   }
 
   action(h_stale_data_to_l0, "hs", desc="If not prefetch, send data to the L0 cache.") {