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sparc: Fixup bit ordering in the PSTATE bit union
authorAndreas Sandberg <Andreas.Sandberg@ARM.com>
Tue, 26 Aug 2014 14:13:23 +0000 (10:13 -0400)
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>
Tue, 26 Aug 2014 14:13:23 +0000 (10:13 -0400)
The order of the MSB and LSB bit of the mm field in the PSTATE union
is wrong. Any access to this field will currently be ignored and reads
will always return zero. This patch fixes the ordering so it is <MSB,
LSB> instead of <LSB, MSB>.

src/arch/sparc/miscregs.hh patch | blob | history

diff --git a/src/arch/sparc/miscregs.hh b/src/arch/sparc/miscregs.hh
index b55fb7d44d428a82b95d1763c1c0d08fc0bdc9ec..6c5118f8a3baaf487624d51fc3fc8a4f305dcce8 100644 (file)
--- a/src/arch/sparc/miscregs.hh
+++ b/src/arch/sparc/miscregs.hh
@@ -129,7 +129,7 @@ BitUnion16(PSTATE)
     Bitfield<2> priv;
     Bitfield<3> am;
     Bitfield<4> pef;
-    Bitfield<6, 7> mm;
+    Bitfield<7, 6> mm;
     Bitfield<8> tle;
     Bitfield<9> cle;
     Bitfield<10> pid0;