cpu,arch: Delegate fetching ROM microops to the decoder.

In most cases, the microcode ROM doesn't actually do anything. The
structural existence of a microcode ROM doesn't make sense in the
general case, and in architectures that know they have one and need to
interact with it, they can cast their decoder into an arch specific type
and access the ROM that way.

Change-Id: I25b67bfe65df1fdb84eb5bc894cfcb83da1ce64b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32898
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index e3c2567ae1daa3013a9105c29af5cdc3338c0594..0cba60a5b5e9dfd38be46e17a26a81f9664fd626 100644 (file)
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -42,6 +42,7 @@ if env['TARGET_ISA'] == 'null':
     Return()
 
 Source('decode_cache.cc')
+Source('decoder.cc')
 
 SimObject('BaseInterrupts.py')
 SimObject('BaseISA.py')

diff --git a/src/arch/generic/decoder.cc b/src/arch/generic/decoder.cc
new file mode 100644 (file)
index 0000000..c28fa00
--- /dev/null
+++ b/src/arch/generic/decoder.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2020 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/generic/decoder.hh"
+
+#include "base/logging.hh"
+
+StaticInstPtr
+InstDecoder::fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop)
+{
+    panic("ROM based microcode isn't implemented.");
+}

diff --git a/src/arch/generic/decoder.hh b/src/arch/generic/decoder.hh
index 00aecf2cc3ac60973f58ac91054a2c09116b241f..3df4dccfd6104bc6ccaa0912e5244d6663c81837 100644 (file)
--- a/src/arch/generic/decoder.hh
+++ b/src/arch/generic/decoder.hh
@@ -28,8 +28,14 @@
 #ifndef __ARCH_GENERIC_DECODER_HH__
 #define __ARCH_GENERIC_DECODER_HH__
 
+#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
+
 class InstDecoder
 {
+  public:
+    virtual StaticInstPtr fetchRomMicroop(
+            MicroPC micropc, StaticInstPtr curMacroop);
 };
 
 #endif // __ARCH_DECODER_GENERIC_HH__

diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
index 28034cba4940035170d0f502bba6fc0f4f1320ef..415c7b4c84decd935c0f45501428b57e6d3fbef9 100644 (file)
--- a/src/arch/x86/decoder.cc
+++ b/src/arch/x86/decoder.cc
@@ -37,6 +37,8 @@
 namespace X86ISA
 {
 
+X86ISAInst::MicrocodeRom Decoder::microcodeRom;
+
 Decoder::State
 Decoder::doResetState()
 {
@@ -725,4 +727,10 @@ Decoder::decode(PCState &nextPC)
     return si;
 }
 
+StaticInstPtr
+Decoder::fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop)
+{
+    return microcodeRom.fetchMicroop(micropc, curMacroop);
+}
+
 }

diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 6b05324b8ae1f2cf502ddc55f22fbdbe3e214516..94ebd0cf2f597532cd2cadcf96e9bdb731a37156 100644 (file)
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -34,6 +34,7 @@
 #include <vector>
 
 #include "arch/generic/decoder.hh"
+#include "arch/x86/microcode_rom.hh"
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/types.hh"
 #include "base/bitfield.hh"
@@ -67,6 +68,8 @@ class Decoder : public InstDecoder
     static ByteTable ImmediateTypeThreeByte0F3A;
     static ByteTable ImmediateTypeVex[10];
 
+    static X86ISAInst::MicrocodeRom microcodeRom;
+
   protected:
     struct InstBytes
     {
@@ -332,6 +335,9 @@ class Decoder : public InstDecoder
     /// @retval A pointer to the corresponding StaticInst object.
     StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
     StaticInstPtr decode(X86ISA::PCState &nextPC);
+
+    StaticInstPtr fetchRomMicroop(
+            MicroPC micropc, StaticInstPtr curMacroop) override;
 };
 
 } // namespace X86ISA

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index b48f6daefeeacd1f9dc8772655ce485a973a731b..0656035c837fd34293f6338d0b42c911b4288a28 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -287,8 +287,8 @@ Checker<Impl>::verify(const DynInstPtr &completed_inst)
 
                 if (isRomMicroPC(pcState.microPC())) {
                     fetchDone = true;
-                    curStaticInst =
-                        microcodeRom.fetchMicroop(pcState.microPC(), NULL);
+                    curStaticInst = thread->decoder.fetchRomMicroop(
+                            pcState.microPC(), nullptr);
                 } else if (!curMacroStaticInst) {
                     //We're not in the middle of a macro instruction
                     StaticInstPtr instPtr = nullptr;

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 6a0184a4b6c719d8388c9b8bc3e469f15447abc8..7ecab54618a58953a32f91ab7833341af03bb25b 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1316,7 +1316,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
             bool newMacro = false;
             if (curMacroop || inRom) {
                 if (inRom) {
-                    staticInst = cpu->microcodeRom.fetchMicroop(
+                    staticInst = decoder[tid]->fetchRomMicroop(
                             thisPC.microPC(), curMacroop);
                 } else {
                     staticInst = curMacroop->fetchMicroop(thisPC.microPC());

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index e63ad4edaaab67285ef0029ef3a25a71ee3d4014..a597f0616d7b1d04ef75ac1c2be5071e8a697ce8 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -500,8 +500,8 @@ BaseSimpleCPU::preExecute()
 
     if (isRomMicroPC(pcState.microPC())) {
         t_info.stayAtPC = false;
-        curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
-                                                  curMacroStaticInst);
+        curStaticInst = thread->decoder.fetchRomMicroop(
+                pcState.microPC(), curMacroStaticInst);
     } else if (!curMacroStaticInst) {
         //We're not in the middle of a macro instruction
         StaticInstPtr instPtr = NULL;