boards/platforms/kcu105: add ddr4 dram pinout

diff --git a/litex/boards/platforms/kcu105.py b/litex/boards/platforms/kcu105.py
index a16ee4d0afb9ad1e532f060ca5181878fe2658d2..ae07d96d73084124581ddda0845a993308acbe89 100644 (file)
--- a/litex/boards/platforms/kcu105.py
+++ b/litex/boards/platforms/kcu105.py
@@ -89,6 +89,49 @@ _io = [
         IOStandard("LVCMOS18")
     ),
 
+    ("ddram", 0,
+        Subsignal("a", Pins(
+            "AE17 AH17 AE18 AJ15 AG16 AL17 AK18 AG17",
+            "AF18 AH19 AF15 AD19 AJ14 AG19"),
+            IOStandard("SSTL12_DCI")),
+        Subsignal("ba", Pins("AF17 AL15"), IOStandard("SSTL12_DCI")),
+        Subsignal("bg", Pins("AG15"), IOStandard("SSTL12_DCI")),
+        Subsignal("ras_n", Pins("AF14"), IOStandard("SSTL12_DCI")), # A16
+        Subsignal("cas_n", Pins("AG14 "), IOStandard("SSTL12_DCI")), # A15
+        Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")), # A14
+        Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")),
+        Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")),
+        Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
+        Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
+        Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
+        Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"),
+            IOStandard("POD12_DCI")),
+        Subsignal("dq", Pins(
+            "AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20",
+            "AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25",
+            
+            "AL22 AL25 AM20 AK23 AK22 AL20 AL24 AL23",
+            "AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22",
+
+            "AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26",
+            "AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27",
+            
+            "AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32",
+            "AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32",
+            ),
+            IOStandard("POD12_DCI")),
+        Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"),
+            IOStandard("DIFF_POD12")),
+        Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"),
+            IOStandard("DIFF_POD12")),
+        Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL2_DCI")),
+        Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL2_DCI")),
+        Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")),
+        Subsignal("odt", Pins("AJ18"), IOStandard("SSTL12_DCI")),
+        Subsignal("reset_n", Pins("AL18"), IOStandard("LVCMOS12")),
+        Misc("SLEW=FAST"),
+    ),
+
     ("pcie_x1", 0,
         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
         Subsignal("clk_p", Pins("AB6")),