(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 5bccb480e37695642f42bcd8075fd23770957c41..4ef3ab8808a26842e5f42581c8ad7d5b42b32430 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -70,7 +70,8 @@ CPU ISA.
 
 Vectorisation of the VSX Packed SIMD system makes no sense whatsoever,
 the sole exceptions potentially being any operations with 128-bit
-operands such as `vrlq` (Rotate Quad Word).
+operands such as `vrlq` (Rotate Quad Word) and `xsaddqp` (Scalar
+Quad-precision Add).
 SV effectively *replaces* VSX requiring far less instructions, and provides,
 at the very minimum, predication (which VSX was designed without).
 Thus all VSX Major Opcodes - all of them - are "unused" and must raise