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add SERV submodule
author
Florent Kermarrec
<florent@enjoy-digital.fr>
Fri, 27 Sep 2019 22:41:28 +0000
(
00:41
+0200)
committer
Florent Kermarrec
<florent@enjoy-digital.fr>
Fri, 27 Sep 2019 22:41:28 +0000
(
00:41
+0200)
.gitmodules
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diff --git
a/.gitmodules
b/.gitmodules
index 17eaf734d30bb58526a0fc3ce4c43102c1ae8c4f..8587dd82d2883b6b016ef026ef4c7b7a0f5a3981 100644
(file)
--- a/
.gitmodules
+++ b/
.gitmodules
@@
-22,3
+22,6
@@
[submodule "litex/soc/cores/cpu/rocket/verilog"]
path = litex/soc/cores/cpu/rocket/verilog
url = https://github.com/enjoy-digital/rocket-litex-verilog
+[submodule "litex/soc/cores/cpu/serv/verilog"]
+ path = litex/soc/cores/cpu/serv/verilog
+ url = https://github.com/olofk/serv