MIPS: Fix mode mismatch error between Loongson builtin arguments and insn

operands.

gcc/

	* config/mips/mips.c (mips_expand_builtin_insn): Convert the QImode
	argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
	builtins to SImode and emit a zero-extend, if necessary.

From-SVN: r245243

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 38f1971df8fa7cd3f0fca2fee7be7888bf0bab74..8affcaba43008db0b5edbeb74e647c874b954b7f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-02-07  Toma Tabacu  <toma.tabacu@imgtec.com>
+
+       * config/mips/mips.c (mips_expand_builtin_insn): Convert the QImode
+       argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
+       builtins to SImode and emit a zero-extend, if necessary.
+
 2017-02-06  Palmer Dabbelt  <palmer@dabbelt.com>
 
        * docs/invoke.texi (RISC-V Options): Alphabetize.

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index da7fa8fcea118da64376a425698fcae17c573564..7974a16541d50261e3a38e73ba299f0feb9201f4 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -16571,9 +16571,27 @@ mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
 {
   machine_mode imode;
   int rangelo = 0, rangehi = 0, error_opno = 0;
+  rtx sireg;
 
   switch (icode)
     {
+    /* The third operand of these instructions is in SImode, so we need to
+       bring the corresponding builtin argument from QImode into SImode.  */
+    case CODE_FOR_loongson_pshufh:
+    case CODE_FOR_loongson_psllh:
+    case CODE_FOR_loongson_psllw:
+    case CODE_FOR_loongson_psrah:
+    case CODE_FOR_loongson_psraw:
+    case CODE_FOR_loongson_psrlh:
+    case CODE_FOR_loongson_psrlw:
+      gcc_assert (has_target_p && nops == 3 && ops[2].mode == QImode);
+      sireg = gen_reg_rtx (SImode);
+      emit_insn (gen_zero_extendqisi2 (sireg,
+                                      force_reg (QImode, ops[2].value)));
+      ops[2].value = sireg;
+      ops[2].mode = SImode;
+      break;
+
     case CODE_FOR_msa_addvi_b:
     case CODE_FOR_msa_addvi_h:
     case CODE_FOR_msa_addvi_w: