radeon: fixup r500 FP emission for new CS

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index ca9d36a8b66aeb9ed9c2b17c9b14b1cf48fe6015..ed94520aba249947ae03f34800eb95b175bc2d97 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -284,6 +284,45 @@ void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom)
     }
 }
 
+void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom)
+{
+       BATCH_LOCALS(r300);
+       drm_r300_cmd_header_t cmd;
+       uint32_t addr, ndw, i, sz;
+       int type, clamp, stride;
+
+       if (!r300->radeon.radeonScreen->kernel_mm) {
+               uint32_t dwords;
+               dwords = (*atom->check) (r300, atom);
+               BEGIN_BATCH_NO_AUTOSTATE(dwords);
+               OUT_BATCH_TABLE(atom->cmd, dwords);
+               END_BATCH();
+               return;
+       }
+
+       cmd.u = atom->cmd[0];
+       sz = cmd.r500fp.count;
+       addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
+       type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
+       clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
+
+       addr |= (type << 16);
+       addr |= (clamp << 17);
+
+       stride = type ? 4 : 6;
+
+       ndw = sz * stride;
+       if (ndw) {
+
+               OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
+               OUT_BATCH(addr);
+               OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
+               for (i = 0; i < ndw; i++) {
+                       OUT_BATCH(atom->cmd[i+1]);
+               }
+       }
+}
+
 static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom)
 {
        BATCH_LOCALS(r300);
@@ -395,7 +434,7 @@ int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom)
        return cnt ? (cnt * 4) + 1 : 0;
 }
 
-static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
+int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
 {
        int cnt;
 
@@ -403,11 +442,11 @@ static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
        return cnt ? (cnt * 6) + 1 : 0;
 }
 
-static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom)
+int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom)
 {
        int cnt;
 
-    cnt = r500fp_count(atom->cmd);
+       cnt = r500fp_count(atom->cmd);
        return cnt ? (cnt * 4) + 1 : 0;
 }
 
@@ -570,10 +609,12 @@ void r300InitCmdBuf(r300ContextPtr r300)
 
                ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
                r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
-            cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
+                       cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
+               r300->hw.r500fp.emit = emit_r500fp;
                ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
                r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
-            cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
+                       cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
+               r300->hw.r500fp_const.emit = emit_r500fp;
        } else {
                ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
                r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
index 1a249c8d52cbbf8c6c69d788a81d5bb8606a7a2c..95701b49b435dae512e2db4ac44c3b6cb02d7322 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
@@ -132,4 +132,8 @@ void r300BeginBatch(r300ContextPtr r300,
 void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom);
 int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom);
 
+void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom);
+int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom);
+int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom);
+
 #endif                         /* __R300_CMDBUF_H__ */

diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index a86841cea41fd2277f77ed3fd82ac50651f4ba25..0cf084bde54c694dde4386a40645e9d5ccd7ff2b 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -387,6 +387,9 @@ static void r300EmitClearState(GLcontext * ctx)
                        FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
                END_BATCH();
        } else {
+               struct r300_state_atom r500fp;
+               uint32_t _cmd[10];
+
                R300_STATECHANGE(r300, fp);
                R300_STATECHANGE(r300, r500fp);
 
@@ -398,44 +401,49 @@ static void r300EmitClearState(GLcontext * ctx)
                OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
                OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
                OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
-
-               OUT_BATCH(cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0));
-               OUT_BATCH(R500_INST_TYPE_OUT |
-                         R500_INST_TEX_SEM_WAIT |
-                         R500_INST_LAST |
-                         R500_INST_RGB_OMASK_R |
-                         R500_INST_RGB_OMASK_G |
-                         R500_INST_RGB_OMASK_B |
-                         R500_INST_ALPHA_OMASK |
-                         R500_INST_RGB_CLAMP |
-                         R500_INST_ALPHA_CLAMP);
-               OUT_BATCH(R500_RGB_ADDR0(0) |
-                         R500_RGB_ADDR1(0) |
-                         R500_RGB_ADDR1_CONST |
-                         R500_RGB_ADDR2(0) |
-                         R500_RGB_ADDR2_CONST);
-               OUT_BATCH(R500_ALPHA_ADDR0(0) |
-                         R500_ALPHA_ADDR1(0) |
-                         R500_ALPHA_ADDR1_CONST |
-                         R500_ALPHA_ADDR2(0) |
-                         R500_ALPHA_ADDR2_CONST);
-               OUT_BATCH(R500_ALU_RGB_SEL_A_SRC0 |
-                         R500_ALU_RGB_R_SWIZ_A_R |
-                         R500_ALU_RGB_G_SWIZ_A_G |
-                         R500_ALU_RGB_B_SWIZ_A_B |
-                         R500_ALU_RGB_SEL_B_SRC0 |
-                         R500_ALU_RGB_R_SWIZ_B_R |
-                         R500_ALU_RGB_B_SWIZ_B_G |
-                         R500_ALU_RGB_G_SWIZ_B_B);
-               OUT_BATCH(R500_ALPHA_OP_CMP |
-                         R500_ALPHA_SWIZ_A_A |
-                         R500_ALPHA_SWIZ_B_A);
-               OUT_BATCH(R500_ALU_RGBA_OP_CMP |
-                         R500_ALU_RGBA_R_SWIZ_0 |
-                         R500_ALU_RGBA_G_SWIZ_0 |
-                         R500_ALU_RGBA_B_SWIZ_0 |
-                         R500_ALU_RGBA_A_SWIZ_0);
                END_BATCH();
+
+               r500fp.check = check_r500fp;
+               r500fp.cmd = _cmd;
+               r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
+               r500fp.cmd[1] = R500_INST_TYPE_OUT |
+                       R500_INST_TEX_SEM_WAIT |
+                       R500_INST_LAST |
+                       R500_INST_RGB_OMASK_R |
+                       R500_INST_RGB_OMASK_G |
+                       R500_INST_RGB_OMASK_B |
+                       R500_INST_ALPHA_OMASK |
+                       R500_INST_RGB_CLAMP |
+                       R500_INST_ALPHA_CLAMP;
+               r500fp.cmd[2] = R500_RGB_ADDR0(0) |
+                       R500_RGB_ADDR1(0) |
+                       R500_RGB_ADDR1_CONST |
+                       R500_RGB_ADDR2(0) |
+                       R500_RGB_ADDR2_CONST;
+               r500fp.cmd[3] = R500_ALPHA_ADDR0(0) |
+                       R500_ALPHA_ADDR1(0) |
+                       R500_ALPHA_ADDR1_CONST |
+                       R500_ALPHA_ADDR2(0) |
+                       R500_ALPHA_ADDR2_CONST;
+               r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 |
+                       R500_ALU_RGB_R_SWIZ_A_R |
+                       R500_ALU_RGB_G_SWIZ_A_G |
+                       R500_ALU_RGB_B_SWIZ_A_B |
+                       R500_ALU_RGB_SEL_B_SRC0 |
+                       R500_ALU_RGB_R_SWIZ_B_R |
+                       R500_ALU_RGB_B_SWIZ_B_G |
+                       R500_ALU_RGB_G_SWIZ_B_B;
+               r500fp.cmd[5] = R500_ALPHA_OP_CMP |
+                       R500_ALPHA_SWIZ_A_A |
+                       R500_ALPHA_SWIZ_B_A;
+               r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP |
+                       R500_ALU_RGBA_R_SWIZ_0 |
+                       R500_ALU_RGBA_G_SWIZ_0 |
+                       R500_ALU_RGBA_B_SWIZ_0 |
+                       R500_ALU_RGBA_A_SWIZ_0;
+               
+               r500fp.cmd[7] = 0;
+               emit_r500fp(r300, &r500fp);
        }
 
        BEGIN_BATCH(2);