Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"

This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1.

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 953fc28d1366d7a60bf0281a65ff6275ce88c9dd..3ca69b7b1ab2817a72d9a589f6959c57658270bb 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -61,6 +61,8 @@ module _80_mul (A, B, Y);
        input [B_WIDTH-1:0] B;\r
        output [Y_WIDTH-1:0] Y;\r
 \r
+       parameter _TECHMAP_CELLTYPE_ = "";\r
+\r
        generate\r
        if (0) begin end\r
 `ifdef DSP_A_MINWIDTH\r
@@ -75,8 +77,10 @@ module _80_mul (A, B, Y);
        else if (Y_WIDTH < `DSP_Y_MINWIDTH)\r
                wire _TECHMAP_FAIL_ = 1;\r
 `endif\r
+       else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)\r
+               wire _TECHMAP_FAIL_ = 1;\r
 `ifdef DSP_SIGNEDONLY\r
-       else if (!A_SIGNED)\r
+       else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)\r
                \$mul #(\r
                        .A_SIGNED(1),\r
                        .B_SIGNED(1),\r
@@ -89,7 +93,7 @@ module _80_mul (A, B, Y);
                        .Y(Y)\r
                );\r
 `endif\r
-       else if (A_WIDTH < B_WIDTH)\r
+       else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)\r
                \$mul #(\r
                        .A_SIGNED(B_SIGNED),\r
                        .B_SIGNED(A_SIGNED),\r