soc_sdram: update litedram

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 30548cef0de3a48001870adedba860ad67df2562..71789a4fe8a8ae679014489e54343130f15d8a4b 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -5,7 +5,6 @@ from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import AutoCSR
 from litex.soc.integration.soc_core import *
 
-from litedram.frontend import crossbar
 from litedram.frontend.wishbone import LiteDRAMWishbone2Native
 from litedram import dfii, core
 
@@ -27,7 +26,7 @@ class ControllerInjector(Module, AutoCSR):
             phy.settings, geom_settings, timing_settings, **kwargs)
         self.comb += controller.dfi.connect(self.dfii.slave)
 
-        self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits)
+        self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface)
 
 
 class SoCSDRAM(SoCCore):