sim.core: warn when driving a clock domain not in the simulation.

Closes #566.

diff --git a/nmigen/sim/core.py b/nmigen/sim/core.py
index 886cea1820d0771a1e13c742485d78014c299e70..270f8475beae4af25714fa2b4f49b6d4ee2c3f93 100644 (file)
--- a/nmigen/sim/core.py
+++ b/nmigen/sim/core.py
@@ -1,4 +1,5 @@
 import inspect
+import warnings
 
 from .._utils import deprecated
 from ..hdl.cd import *
@@ -112,7 +113,13 @@ class Simulator:
             in this case.
         """
         if isinstance(domain, ClockDomain):
-            pass
+            if (domain.name in self._fragment.domains and
+                    domain is not self._fragment.domains[domain.name]):
+                warnings.warn("Adding a clock process that drives a clock domain object "
+                              "named {!r}, which is distinct from an identically named domain "
+                              "in the simulated design"
+                              .format(domain.name),
+                              UserWarning, stacklevel=2)
         elif domain in self._fragment.domains:
             domain = self._fragment.domains[domain]
         elif if_exists:

diff --git a/tests/test_sim.py b/tests/test_sim.py
index 136cdb6e7a97bef5d4a91f436b0e9583ecaec656..8bf100a61f72f68f8589f4937599ae1544f4b971 100644 (file)
--- a/tests/test_sim.py
+++ b/tests/test_sim.py
@@ -851,3 +851,12 @@ class SimulatorRegressionTestCase(FHDLTestCase):
                 r"^Value defined at .+?/test_sim\.py:\d+ is 4294967327 bits wide, "
                 r"which is unlikely to simulate in reasonable time$"):
             Simulator(dut)
+
+    def test_bug_566(self):
+        dut = Module()
+        dut.d.sync += Signal().eq(0)
+        sim = Simulator(dut)
+        with self.assertWarnsRegex(UserWarning,
+                r"^Adding a clock process that drives a clock domain object named 'sync', "
+                r"which is distinct from an identically named domain in the simulated design$"):
+            sim.add_clock(1e-6, domain=ClockDomain("sync"))