Merge remote-tracking branch 'origin/master' into xaig_dff

diff --cc passes/techmap/abc9.cc
index 6b893695809bc5b1082b810bf6d09ccb7bd7d700,8276c3c16f815dbf65b4dd0a182458693b2978d3..8f2d45b6271bb07cf1afd5eb4a9a0494b6dae31d
--- 1/passes/techmap/abc9.cc
--- 2/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@@ -354,24 -428,8 +364,6 @@@ void abc9_module(RTLIL::Design *design
                design->remove(design->module(ID($__abc9__)));
  #endif
  
-               // Now 'unexpose' those wires by undoing
-               // the expose operation -- remove them from PO/PI
-               // and re-connecting them back together
-               for (auto wire : module->wires()) {
-                       auto it = wire->attributes.find(ID(abc9_scc_break));
-                       if (it != wire->attributes.end()) {
-                               wire->attributes.erase(it);
-                               log_assert(wire->port_output);
-                               wire->port_output = false;
-                               RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
-                               log_assert(i_wire);
-                               log_assert(i_wire->port_input);
-                               i_wire->port_input = false;
-                               module->connect(i_wire, wire);
-                       }
-               }
-               module->fixup_ports();
 -              design->selection_stack.pop_back();
--
                log_header(design, "Executing ABC9.\n");
  
                if (!lut_costs.empty()) {

diff --cc techlibs/xilinx/cells_sim.v
Simple merge

diff --cc techlibs/xilinx/synth_xilinx.cc
index 30be9832ce137a241e7b71fd98707d343734ad02,2c5686a3564a28448abe285a1e7ebbdce92547a6..de262c8adaa36992ffb244a439007d29128e52df
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -560,18 -567,10 +566,11 @@@ struct SynthXilinxPass : public ScriptP
                }
  
                if (check_label("finalize")) {
-                       bool do_iopad = iopad || (ise && !noiopad);
-                       if (help_mode || !noclkbuf) {
-                               if (help_mode || do_iopad)
-                                       run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')");
-                               else
-                                       run("clkbufmap -buf BUFG O:I");
-                       }
-                       if (help_mode || do_iopad)
-                               run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
+                       if (help_mode || !noclkbuf)
+                               run("clkbufmap -buf BUFG O:I ", "(skip if '-noclkbuf')");
                        if (help_mode || ise)
                                run("extractinv -inv INV O:I", "(only if '-ise')");
 +                      run("clean");
                }
  
                if (check_label("check")) {

diff --cc tests/simple_abc9/abc9.v
index 961e7605e2c9d2e27355bc60547df86c7876d35b,de60619d1b71ebf54929995e3c79add0942d96df..8afd0ce963afb325db7622bbf9d449fb7fcec8a4
--- 1/tests/simple_abc9/abc9.v
--- 2/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@@ -259,29 -259,8 +259,35 @@@ assign o = { 1'b1, 1'bx }
  assign p = { 1'b1, 1'bx, 1'b0 };
  endmodule
  
- module abc9_test029(input clk1, clk2, d, output reg q1, q2);
+ module abc9_test030(input [3:0] d, input en, output reg [3:0] q);
+ always @*
+   if (en)
+     q <= d;
+ endmodule
++
++module abc9_test031(input clk1, clk2, d, output reg q1, q2);
 +always @(posedge clk1) q1 <= d;
 +always @(negedge clk2) q2 <= q1;
 +endmodule
 +
- module abc9_test030(input clk, d, r, output reg q);
++module abc9_test032(input clk, d, r, output reg q);
 +always @(posedge clk or posedge r)
 +    if (r) q <= 1'b0;
 +    else q <= d;
 +endmodule
 +
- module abc9_test031(input clk, d, r, output reg q);
++module abc9_test033(input clk, d, r, output reg q);
 +always @(negedge clk or posedge r)
 +    if (r) q <= 1'b1;
 +    else q <= d;
 +endmodule
 +
- module abc9_test033(input clk, d, output reg q1, q2);
++module abc9_test034(input clk, d, output reg q1, q2);
 +always @(posedge clk) q1 <= d;
 +always @(posedge clk) q2 <= q1;
 +endmodule
 +
- module abc9_test034(input clk, d, output reg [1:0] q);
++module abc9_test035(input clk, d, output reg [1:0] q);
 +always @(posedge clk) q[0] <= d;
 +always @(negedge clk) q[1] <= q[0];
 +endmodule