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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index a4a11cae69176cfaced6f155d97aca319a29931d..252f08c5547756f975aa418940c590610e0a65b7 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -812,15 +812,25 @@ be happy that a Processing Element (PE) has to execute Power ISA binaries.
 At least the Power ISA is much richer, more powerful, still RISC,
 and is an Open Standard, as discussed in a earlier sections.
 
-A reasonable compromise in this regard however is illustrated with
+A reasonable compromise as a JEDEC Standard is illustrated with
 the following diagram: a 3-way Bridge PHY that allows for full
 direct interaction between DRAM ICs, PEs, and one or more main CPUs
 (* a variant of the Northbridge and/or IBM POWER10 OMI-to-DDR5 PHY concept*).
-It is also the ideal location for a "Management Core"
+It is also the ideal location for a "Management Core".
+If the 3-way Bridge (4-way if connectivity to other Bridge PHYs
+is also included) does not itself have PEs built-in then the ISA
+utilised on any PE or CPU is non-critical.  The only concern regarding
+mixed ISAs is that the PHY should be capable of transferring all and
+any types of "Management" packets, particularly PE Virtual Memory Management
+and Register File Control (Context-switch Management given that the PEs
+are expected to be ALU-heavy and not capable of running a full SMP Operating
+System).
+
 There is also no reason why this type of arrangement should not be deployed
 in Multi-Chip-Module (aka "Chiplet") form, giving all the advantages of
 the performance boost that goes with smaller line-drivers.
 
+
 Draft Image (placeholder):
 
 <img src="/openpower/sv/bridge_phy.jpg" width=800 />