fhdl/verilog: fix tristate to instance connection

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index c34b11bd4b4359e48cb9bd3de18185a808138a68..b4bd534e9458936ada6dd263367149781bff8741 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -275,7 +275,7 @@ def _printinit(f, ios, ns):
        signals = (list_signals(f) | list_special_ios(f, True, False, False)) \
                - ios \
                - list_targets(f) \
-               - list_special_ios(f, False, True, False)
+               - list_special_ios(f, False, True, True)
        if signals:
                r += "initial begin\n"
                for s in sorted(signals, key=lambda x: x.huid):