r600: improve state emission

Slowing migrating to atom based system like
the other radeon drivers.

diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h
index 17ac088901195d5202c8899f02011d6438fff5a0..0cf2eb2daa53bd382ef6a54b3d9f41f3bc373214 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_context.h
+++ b/src/mesa/drivers/dri/r600/r600_context.h
@@ -137,6 +137,19 @@ extern GLboolean r600CreateContext(const __GLcontextModes * glVisual,
 
 #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw))
 
+#define R600_NEWPRIM( rmesa )                  \
+do {                                           \
+       if ( rmesa->radeon.dma.flush )                  \
+               rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
+} while (0)
+
+#define R600_STATECHANGE(r600, atom)                   \
+do {                                                   \
+       R600_NEWPRIM(r600);                                     \
+       (atom) = GL_TRUE;                                       \
+       r600->radeon.hw.is_dirty = GL_TRUE;                     \
+} while(0)
+
 extern GLboolean r700SendSPIState(context_t *context);
 extern GLboolean r700SendVGTState(context_t *context);
 extern GLboolean r700SendSXState(context_t *context);

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index e67e544d5384138ba12abe86d7bddaec67490015..7f46b0c46883b388909cbf3d2881fb13a65b77fb 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -258,6 +258,8 @@ GLboolean r700SendDepthTargetState(context_t *context)
        r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
                     DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
 
+       r700->db_target_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -310,6 +312,8 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
        r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
                     CB_ACTION_ENA_bit | (1 << (id + 6)));
 
+       r700->render_target[id].dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -343,6 +347,8 @@ GLboolean r700SendPSState(context_t *context)
 
        COMMIT_BATCH();
 
+       r700->ps.dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -375,6 +381,8 @@ GLboolean r700SendVSState(context_t *context)
 
        COMMIT_BATCH();
 
+       r700->vs.dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -416,6 +424,8 @@ GLboolean r700SendFSState(context_t *context)
 
        COMMIT_BATCH();
 
+       r700->fs.dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -448,6 +458,8 @@ GLboolean r700SendViewportState(context_t *context, int id)
 
        COMMIT_BATCH();
 
+       r700->viewport[id].dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -485,6 +497,8 @@ GLboolean r700SendSQConfig(context_t *context)
 
        COMMIT_BATCH();
 
+       r700->sq_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -495,7 +509,7 @@ GLboolean r700SendUCPState(context_t *context)
        int i;
 
        for (i = 0; i < R700_MAX_UCP; i++) {
-               if (r700->ucp[i].enabled) {
+               if (r700->ucp[i].enabled && r700->ucp[i].dirty) {
                        BEGIN_BATCH_NO_AUTOSTATE(6);
                        R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
                        R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
@@ -504,6 +518,7 @@ GLboolean r700SendUCPState(context_t *context)
                        R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
                        END_BATCH();
                        COMMIT_BATCH();
+                       r700->ucp[i].dirty = GL_FALSE;
                }
        }
 
@@ -582,6 +597,8 @@ GLboolean r700SendSPIState(context_t *context)
        END_BATCH();
        COMMIT_BATCH();
 
+       r700->spi_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -628,6 +645,8 @@ GLboolean r700SendVGTState(context_t *context)
        END_BATCH();
        COMMIT_BATCH();
 
+       r700->vgt_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -643,6 +662,8 @@ GLboolean r700SendSXState(context_t *context)
        END_BATCH();
        COMMIT_BATCH();
 
+       r700->sx_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -675,6 +696,8 @@ GLboolean r700SendDBState(context_t *context)
        END_BATCH();
        COMMIT_BATCH();
 
+       r700->db_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -734,6 +757,8 @@ GLboolean r700SendCBState(context_t *context)
 
        COMMIT_BATCH();
 
+       r700->cb_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -764,6 +789,8 @@ GLboolean r700SendSUState(context_t *context)
        END_BATCH();
        COMMIT_BATCH();
 
+       r700->su_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -787,6 +814,8 @@ GLboolean r700SendCLState(context_t *context)
        END_BATCH();
        COMMIT_BATCH();
 
+       r700->cl_dirty = GL_FALSE;
+
        return GL_TRUE;
 }
 
@@ -832,5 +861,7 @@ GLboolean r700SendSCState(context_t *context)
        END_BATCH();
        COMMIT_BATCH();
 
+       r700->sc_dirty = GL_FALSE;
+
        return GL_TRUE;
 }

diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h
index 545e4a188a282ec0cba832dbd701ba363614caad..c0ec4b0dd593a346a8923f3aae74ac2c798cd8a9 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.h
+++ b/src/mesa/drivers/dri/r600/r700_chip.h
@@ -275,6 +275,7 @@ typedef struct _R700_CHIP_CONTEXT
        union UINT_FLOAT                DB_DEPTH_VIEW             ;  /* 0xA001 */
        union UINT_FLOAT                DB_DEPTH_BASE             ;  /* 0xA003 */
        union UINT_FLOAT                DB_DEPTH_INFO             ;  /* 0xA004 */
+       GLboolean                       db_target_dirty;
        union UINT_FLOAT                DB_HTILE_DATA_BASE        ;  /* 0xA005 */
        union UINT_FLOAT                DB_STENCIL_CLEAR          ;  /* 0xA00A */
        union UINT_FLOAT                DB_DEPTH_CLEAR            ;  /* 0xA00B */

diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c
index 05d4af331e04f1f6d62150e7f5137c407bfcdd88..6d4ea90ccc631b5a9edf64a77c842310461ae30b 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_clear.c
+++ b/src/mesa/drivers/dri/r600/r700_clear.c
@@ -46,12 +46,6 @@ static GLboolean r700ClearFast(context_t *context, GLbitfield mask)
     return GL_FALSE;
 }
 
-#define R600_NEWPRIM( rmesa )                  \
-  do {                                         \
-  if ( rmesa->radeon.dma.flush )                       \
-    rmesa->radeon.dma.flush( rmesa->radeon.glCtx );    \
-  } while (0)
-
 void r700Clear(GLcontext * ctx, GLbitfield mask)
 {
     context_t *context = R700_CONTEXT(ctx);

diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 1cc886d5e9c9e9e71dbd1f127c89add08b3af204..52f8f90dad37f9ec6d2b94960bf40f2f9e1cd83a 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -332,30 +332,70 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim
 
 }
 
+static void r700EmitAtoms(GLcontext * ctx, GLboolean dirty)
+{
+       context_t *context = R700_CONTEXT(ctx);
+       radeonContextPtr radeon = &context->radeon;
+       R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+
+       if ((r700->sq_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendSQConfig(context);
+       r700SendUCPState(context);
+       if ((r700->sc_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendSCState(context);
+       if ((r700->su_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendSUState(context);
+       if ((r700->cl_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendCLState(context);
+       if ((r700->cb_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendCBState(context);
+       if ((r700->db_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendDBState(context);
+       if ((r700->sx_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendSXState(context);
+       if ((r700->vgt_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendVGTState(context);
+       if ((r700->spi_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendSPIState(context);
+       if ((r700->viewport[0].dirty || radeon->hw.all_dirty) == dirty)
+               r700SendViewportState(context, 0);
+       if ((r700->render_target[0].dirty || radeon->hw.all_dirty) == dirty)
+               r700SendRenderTargetState(context, 0);
+       if ((r700->db_target_dirty || radeon->hw.all_dirty) == dirty)
+               r700SendDepthTargetState(context);
+
+}
+
 void r700EmitState(GLcontext * ctx)
 {
        context_t *context = R700_CONTEXT(ctx);
        radeonContextPtr radeon = &context->radeon;
 
+       if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
+               fprintf(stderr, "%s\n", __FUNCTION__);
+
+       if (radeon->vtbl.pre_emit_state)
+               radeon->vtbl.pre_emit_state(radeon);
+
        if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty)
                return;
 
        rcommonEnsureCmdBufSpace(&context->radeon,
                                 652, __FUNCTION__);
 
-       r700SendSQConfig(context);
-       r700SendUCPState(context);
-       r700SendSCState(context);
-       r700SendSUState(context);
-       r700SendCLState(context);
-       r700SendCBState(context);
-       r700SendDBState(context);
-       r700SendSXState(context);
-       r700SendVGTState(context);
-       r700SendSPIState(context);
-       r700SendViewportState(context, 0);
-       r700SendRenderTargetState(context, 0);
-       r700SendDepthTargetState(context);
+       if (!radeon->cmdbuf.cs->cdw) {
+               if (RADEON_DEBUG & DEBUG_STATE)
+                       fprintf(stderr, "Begin reemit state\n");
+
+               r700EmitAtoms(ctx, GL_FALSE);
+       }
+
+       if (RADEON_DEBUG & DEBUG_STATE)
+               fprintf(stderr, "Begin dirty state\n");
+
+       r700EmitAtoms(ctx, GL_TRUE);
+       radeon->hw.is_dirty = GL_FALSE;
+       radeon->hw.all_dirty = GL_FALSE;
 
 }
 

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 835b5e18c2cb5bb2a1e7b1210830433aa6b710d3..ada394ec61b4a5e7234c0d064f3dc589bec06f64 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -148,8 +148,15 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------
        GLfloat tx = v[MAT_TX] + xoffset;
        GLfloat ty = (-v[MAT_TY]) + yoffset;
 
-       r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
-       r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
+       if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
+           r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
+               /* Note: this should also modify whatever data the context reset
+                * code uses...
+                */
+               R600_STATECHANGE(context, r700->viewport[id].dirty);
+               r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
+               r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
+       }
 
        radeonUpdateScissor(ctx);
 }
@@ -161,6 +168,10 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------
 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
 {
        context_t *context = R700_CONTEXT(ctx);
+       R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+       R600_STATECHANGE(context, r700->render_target[0].dirty);
+       R600_STATECHANGE(context, r700->db_target_dirty);
 
        r700SetRenderTarget(context, 0);
        r700SetDepthTarget(context);
@@ -233,6 +244,9 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-----------
 
        r700UpdateStateParameters(ctx, new_state);
 
+    R600_STATECHANGE(context, r700->cl_dirty);
+    R600_STATECHANGE(context, r700->spi_dirty);
+
     if(GL_TRUE == r700->bEnablePerspective)
     {
         /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
@@ -256,14 +270,15 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-----------
         SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
     }
 
-       context->radeon.NewGLState |= new_state;
+    context->radeon.NewGLState |= new_state;
 }
 
 static void r700SetDepthState(GLcontext * ctx)
 {
        context_t *context = R700_CONTEXT(ctx);
+       R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
-    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+       R600_STATECHANGE(context, r700->db_dirty);
 
     if (ctx->Depth.Test)
     {
@@ -331,6 +346,8 @@ static void r700SetAlphaState(GLcontext * ctx)
        uint32_t alpha_func = REF_ALWAYS;
        GLboolean really_enabled = ctx->Color.AlphaEnabled;
 
+       R600_STATECHANGE(context, r700->sx_dirty);
+
        switch (ctx->Color.AlphaFunc) {
        case GL_NEVER:
                alpha_func = REF_NEVER;
@@ -383,6 +400,8 @@ static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //-------------
        context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+       R600_STATECHANGE(context, r700->cb_dirty);
+
        r700->CB_BLEND_RED.f32All = cf[0];
        r700->CB_BLEND_GREEN.f32All = cf[1];
        r700->CB_BLEND_BLUE.f32All = cf[2];
@@ -451,6 +470,8 @@ static void r700SetBlendState(GLcontext * ctx)
        int id = 0;
        uint32_t blend_reg = 0, eqn, eqnA;
 
+       R600_STATECHANGE(context, r700->cb_dirty);
+
        if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
                SETfield(blend_reg,
                         BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
@@ -637,8 +658,11 @@ static GLuint translate_logicop(GLenum logicop)
  */
 static void r700SetLogicOpState(GLcontext *ctx)
 {
+       context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
 
+       R600_STATECHANGE(context, r700->cb_dirty);
+
        if (RGBA_LOGICOP_ENABLED(ctx))
                SETfield(r700->CB_COLOR_CONTROL.u32All,
                         translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
@@ -658,7 +682,10 @@ static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
 
 static void r700UpdateCulling(GLcontext * ctx)
 {
-    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
+       context_t *context = R700_CONTEXT(ctx);
+       R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
+
+    R600_STATECHANGE(context, r700->su_dirty);
 
     CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
     CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
@@ -703,7 +730,11 @@ static void r700UpdateCulling(GLcontext * ctx)
 
 static void r700UpdateLineStipple(GLcontext * ctx)
 {
-    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
+       context_t *context = R700_CONTEXT(ctx);
+       R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
+
+    R600_STATECHANGE(context, r700->sc_dirty);
+
     if (ctx->Line.StippleFlag)
     {
        SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
@@ -778,14 +809,17 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 static void r700ColorMask(GLcontext * ctx,
                          GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
 {
+       context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
        unsigned int mask = ((r ? 1 : 0) |
                             (g ? 2 : 0) |
                             (b ? 4 : 0) |
                             (a ? 8 : 0));
 
-       if (mask != r700->CB_SHADER_MASK.u32All)
+       if (mask != r700->CB_SHADER_MASK.u32All) {
+               R600_STATECHANGE(context, r700->cb_dirty);
                SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
+       }
 }
 
 /**
@@ -841,6 +875,8 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
        context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+       R600_STATECHANGE(context, r700->spi_dirty);
+
        /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
        switch (mode) {
        case GL_FLAT:
@@ -862,6 +898,8 @@ static void r700PointSize(GLcontext * ctx, GLfloat size)
        context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+       R600_STATECHANGE(context, r700->su_dirty);
+
        /* We need to clamp to user defined range here, because
         * the HW clamping happens only for per vertex point size. */
        size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
@@ -882,6 +920,8 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa
        context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+       R600_STATECHANGE(context, r700->su_dirty);
+
        /* format is 12.4 fixed point */
        switch (pname) {
        case GL_POINT_SIZE_MIN:
@@ -966,6 +1006,7 @@ static void r700SetStencilState(GLcontext * ctx, GLboolean state)
        }
 
        if (hw_stencil) {
+               R600_STATECHANGE(context, r700->db_dirty);
                if (state)
                        SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
                else
@@ -983,6 +1024,8 @@ static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
        //fixme
        //r300CatchStencilFallback(ctx);
 
+       R600_STATECHANGE(context, r700->db_dirty);
+
        //front
        SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
                 STENCILREF_shift, STENCILREF_mask);
@@ -1012,6 +1055,8 @@ static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) /
        //fixme
        //r300CatchStencilFallback(ctx);
 
+       R600_STATECHANGE(context, r700->db_dirty);
+
        // front
        SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
                 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
@@ -1032,6 +1077,8 @@ static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
        //fixme
        //r300CatchStencilFallback(ctx);
 
+       R600_STATECHANGE(context, r700->db_dirty);
+
        SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
                 STENCILFAIL_shift, STENCILFAIL_mask);
        SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
@@ -1074,7 +1121,7 @@ static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
        GLfloat sz = v[MAT_SZ] * depthScale;
        GLfloat tz = v[MAT_TZ] * depthScale;
 
-       /* TODO : Need DMA flush as well. */
+       R600_STATECHANGE(context, r700->viewport[id].dirty);
 
        r700->viewport[id].PA_CL_VPORT_XSCALE.f32All  = sx;
        r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
@@ -1112,10 +1159,13 @@ static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
     context_t *context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
     uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
+
+    R600_STATECHANGE(context, r700->su_dirty);
+
     if (lineWidth > 0xFFFF)
-       lineWidth = 0xFFFF;
+           lineWidth = 0xFFFF;
     SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
-       PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
+            PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
 }
 
 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
@@ -1123,6 +1173,8 @@ static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
     context_t *context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+    R600_STATECHANGE(context, r700->sc_dirty);
+
     SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
     SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
     SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
@@ -1133,6 +1185,8 @@ static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
        context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+       R600_STATECHANGE(context, r700->su_dirty);
+
        if (state) {
                SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
                SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
@@ -1161,6 +1215,8 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //
 
        factor *= 12.0;
 
+       R600_STATECHANGE(context, r700->su_dirty);
+
        r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
        r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
        r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
@@ -1172,6 +1228,8 @@ static void r700UpdatePolygonMode(GLcontext * ctx)
        context_t *context = R700_CONTEXT(ctx);
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+       R600_STATECHANGE(context, r700->su_dirty);
+
        SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
 
        /* Only do something if a polygon mode is wanted, default is GL_FILL */
@@ -1247,6 +1305,8 @@ static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
        p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
        ip = (GLint *)ctx->Transform._ClipUserPlane[p];
 
+       R600_STATECHANGE(context, r700->ucp[p].dirty);
+
        r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
        r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
        r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
@@ -1260,6 +1320,9 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
        GLuint p;
 
        p = cap - GL_CLIP_PLANE0;
+
+       R600_STATECHANGE(context, r700->cl_dirty);
+
        if (state) {
                r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
                r700->ucp[p].enabled = GL_TRUE;
@@ -1293,6 +1356,8 @@ void r700SetScissor(context_t *context) //---------------
                y2 = rrb->dPriv->y + rrb->dPriv->h;
        }
 
+       R600_STATECHANGE(context, r700->sc_dirty);
+
        /* window */
        SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
        SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
@@ -1361,6 +1426,9 @@ static void r700SetRenderTarget(context_t *context, int id)
            return;
     }
 
+    R600_STATECHANGE(context, r700->render_target[id].dirty);
+    R600_STATECHANGE(context, r700->cb_dirty);
+
     /* screen/window/view */
     SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
 
@@ -1407,6 +1475,9 @@ static void r700SetDepthTarget(context_t *context)
     if (!rrb)
            return;
 
+    R600_STATECHANGE(context, r700->db_target_dirty);
+    R600_STATECHANGE(context, r700->db_dirty);
+
     /* depth buf */
     r700->DB_DEPTH_SIZE.u32All = 0;
     r700->DB_DEPTH_BASE.u32All = 0;
@@ -1467,6 +1538,8 @@ static void r700InitSQConfig(GLcontext * ctx)
     int num_gs_stack_entries;
     int num_es_stack_entries;
 
+    R600_STATECHANGE(context, r700->sq_dirty);
+
     // SQ
     ps_prio = 0;
     vs_prio = 1;