MIPS: Add support for P6600

gas/
	* config/tc-mips.c (mips_cpu_info_table): Update comment. Add
	p6600 entry.
	* doc/c-mips.texi: Document p6600 -march option.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 272f8fe49f586a69698086fe3e95b839ed763029..328299b1ab580c6e08a66610f1e0b42436918b6e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2016-05-20  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (mips_cpu_info_table): Update comment.  Add
+       p6600 entry.
+       * doc/c-mips.texi: Document p6600 -march option.
+
 2016-05-20  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/19600

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 233c6415ea5e5e56021ed183149757e1c128bf22..f58955c5232d99129a71b53f674189de4f55315d 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -18756,8 +18756,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
      MIPS64R2 rather than MIPS64.  */
   { "xlp",           0, 0,                     ISA_MIPS64R2, CPU_XLR },
 
-  /* i6400.  */
+  /* MIPS 64 Release 6 */
   { "i6400",         0, ASE_MSA,               ISA_MIPS64R6, CPU_MIPS64R6},
+  { "p6600",         0, ASE_VIRT | ASE_MSA,    ISA_MIPS64R6, CPU_MIPS64R6},
 
   /* End marker */
   { NULL, 0, 0, 0, 0 }

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 5fa64cbab16d2f1dd9e322a9dd9d812885aea63b..718ac94298c57c4ff253413e3a9e90780c8ab74f 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -387,6 +387,7 @@ p5600,
 sb1,
 sb1a,
 i6400,
+p6600,
 loongson2e,
 loongson2f,
 loongson3a,