fhdl: pad support in fragments

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index a1a49526ab46fb7101cd6a7eb71644e427930542..d00de9edb3de17de34e022a65388b6e5112bb591 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -194,15 +194,20 @@ class Instance:
                return id(self)
 
 class Fragment:
-       def __init__(self, comb=StatementList(), sync=StatementList(), instances=[]):
+       def __init__(self, comb=StatementList(), sync=StatementList(), instances=[], pads=set()):
                self.comb = _sl(comb)
                self.sync = _sl(sync)
                self.instances = instances
+               self.pads = pads
        
        def __add__(self, other):
-               return Fragment(self.comb.l + other.comb.l, self.sync.l + other.sync.l, self.instances + other.instances)
+               return Fragment(self.comb.l + other.comb.l,
+                       self.sync.l + other.sync.l,
+                       self.instances + other.instances,
+                       self.pads | other.pads)
        def __iadd__(self, other):
                self.comb.l += other.comb.l
                self.sync.l += other.sync.l
                self.instances += other.instances
-               return self
\ No newline at end of file
+               self.pads |= other.pads
+               return self

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 7f386cb8bda73b1cdd629ce39c23d071adef1ecc..8fa9c480d79d5b2bfb2ff697a05fcf3647e08147 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -118,6 +118,8 @@ def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst"):
        
        clks = Signal(name=clkname)
        rsts = Signal(name=rstname)
+       
+       ios |= f.pads
 
        sigs = ListSignals(f)
        targets = ListTargets(f)