#include <iostream>
#include <iomanip>
+#include "arch/alpha/faults.hh"
#include "config/ss_compatible_fp.hh"
#include "cpu/static_inst.hh"
-#include "arch/alpha/faults.hh"
#include "mem/request.hh" // some constructors use MemReq flags
+#include "mem/packet.hh"
}};
output decoder {{
+#include <cmath>
+
#include "base/cprintf.hh"
#include "base/fenv.hh"
#include "base/loader/symtab.hh"
#include "config/ss_compatible_fp.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
-
-#include <math.h>
+#include "mem/packet.hh"
using namespace AlphaISA;
}};
def template CompleteAccDeclare {{
- Fault completeAcc(Packet *, %(CPU_exec_context)s *,
+ Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
Trace::InstRecord *) const;
}};
def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
def template MiscCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
def template CompleteAccDeclare {{
- Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
}};
def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
def template MiscCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
#include <iostream>
#include <iomanip>
-#include "cpu/static_inst.hh"
#include "arch/mips/isa_traits.hh"
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
}};
output decoder {{
+#include <cmath>
+#if defined(linux)
+#include <fenv.h>
+#endif
+
+#include "arch/mips/faults.hh"
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/isa_traits.hh"
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/utility.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
-#include "arch/mips/faults.hh"
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-
-#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
using namespace MipsISA;
}};
// translate to physical address
translateDataReadReq(memReq);
- Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
pkt->dataStatic(&data);
T inst_data;
/*
// This code would work if the LSQ allowed for snooping.
- Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
pkt.dataStatic(&inst_data);
dcachePort->sendFunctional(pkt);
}
if (fault == NoFault) {
- Packet *pkt = new Packet(memReq, Packet::ReadReq,
+ PacketPtr pkt = new Packet(memReq, Packet::ReadReq,
Packet::Broadcast);
pkt->dataStatic(&machInst);
int TESTER_ALLOCATOR=0;
bool
-MemTest::CpuPort::recvTiming(Packet *pkt)
+MemTest::CpuPort::recvTiming(PacketPtr pkt)
{
memtest->completeRequest(pkt);
return true;
}
Tick
-MemTest::CpuPort::recvAtomic(Packet *pkt)
+MemTest::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("MemTest doesn't expect recvAtomic callback!");
return curTick;
}
void
-MemTest::CpuPort::recvFunctional(Packet *pkt)
+MemTest::CpuPort::recvFunctional(PacketPtr pkt)
{
//Do nothing if we see one come through
// if (curTick != 0)//Supress warning durring initialization
}
void
-MemTest::sendPkt(Packet *pkt) {
+MemTest::sendPkt(PacketPtr pkt) {
if (atomic) {
cachePort.sendAtomic(pkt);
pkt->makeAtomicResponse();
}
void
-MemTest::completeRequest(Packet *pkt)
+MemTest::completeRequest(PacketPtr pkt)
{
MemTestSenderState *state =
dynamic_cast<MemTestSenderState *>(pkt->senderState);
<< dec << curTick << endl;
}
- Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
<< dec << curTick << endl;
}
*/
- Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
};
// Request *dataReq;
- Packet *retryPkt;
+ PacketPtr retryPkt;
// MemInterface *cacheInterface;
// PhysicalMemory *mainMem;
// PhysicalMemory *checkMem;
Stats::Scalar<> numCopiesStat;
// called by MemCompleteEvent::process()
- void completeRequest(Packet *pkt);
+ void completeRequest(PacketPtr pkt);
- void sendPkt(Packet *pkt);
+ void sendPkt(PacketPtr pkt);
void doRetry();
Fault initiateAcc();
/** Completes the access. Only valid for memory operations. */
- Fault completeAcc(Packet *pkt);
+ Fault completeAcc(PacketPtr pkt);
private:
/** Initializes variables. */
template <class Impl>
Fault
-AlphaDynInst<Impl>::completeAcc(Packet *pkt)
+AlphaDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
template<class Impl>
bool
-DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
+DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
fetch->processCacheCompletion(pkt);
void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Handles completing the send of a store to memory. */
- void storePostSend(Packet *pkt);
+ void storePostSend(PacketPtr pkt);
/** Completes the store at the specified index. */
void completeStore(int store_idx);
template <class Impl>
void
-LSQUnit<Impl>::storePostSend(Packet *pkt)
+LSQUnit<Impl>::storePostSend(PacketPtr pkt)
{
if (isStalled() &&
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
Fault initiateAcc();
/** Completes the access. Only valid for memory operations. */
- Fault completeAcc(Packet *pkt);
+ Fault completeAcc(PacketPtr pkt);
private:
/** Initializes variables. */
template <class Impl>
Fault
-MipsDynInst<Impl>::completeAcc(Packet *pkt)
+MipsDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
Fault initiateAcc();
- Fault completeAcc(Packet *pkt);
+ Fault completeAcc(PacketPtr pkt);
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural
template <class Impl>
Fault
-OzoneDynInst<Impl>::completeAcc(Packet *pkt)
+OzoneDynInst<Impl>::completeAcc(PacketPtr pkt)
{
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
const bool is_branch = false, const bool branch_taken = false);
DynInstPtr getInst();
- void processCacheCompletion(Packet *pkt);
+ void processCacheCompletion(PacketPtr pkt);
void addFreeRegs(int num_freed);
template<class Impl>
bool
-FrontEnd<Impl>::IcachePort::recvTiming(Packet *pkt)
+FrontEnd<Impl>::IcachePort::recvTiming(PacketPtr pkt)
{
fe->processCacheCompletion(pkt);
return true;
void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Handles completing the send of a store to memory. */
- void storePostSend(Packet *pkt, DynInstPtr &inst);
+ void storePostSend(PacketPtr pkt, DynInstPtr &inst);
/** Completes the store at the specified index. */
void completeStore(DynInstPtr &inst);
template <class Impl>
void
-OzoneLWLSQ<Impl>::storePostSend(Packet *pkt, DynInstPtr &inst)
+OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
{
if (isStalled() &&
inst->seqNum == stallingStoreIsn) {
}
bool
-AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
{
panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
return true;
}
Tick
-AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
//Snooping a coherence request, just return
return curTick;
}
void
-AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
{
//No internal storage to update, just return
return;
{
// use the CPU's statically allocated read request and packet objects
Request *req = data_read_req;
- Packet *pkt = data_read_pkt;
+ PacketPtr pkt = data_read_pkt;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
{
// use the CPU's statically allocated write request and packet objects
Request *req = data_write_req;
- Packet *pkt = data_write_pkt;
+ PacketPtr pkt = data_write_pkt;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
CpuPort icachePort;
CpuPort dcachePort;
- Request *ifetch_req;
- Packet *ifetch_pkt;
- Request *data_read_req;
- Packet *data_read_pkt;
- Request *data_write_req;
- Packet *data_write_pkt;
+ Request *ifetch_req;
+ PacketPtr ifetch_pkt;
+ Request *data_read_req;
+ PacketPtr data_read_pkt;
+ Request *data_write_req;
+ PacketPtr data_write_pkt;
bool dcache_access;
Tick dcache_latency;
}
Tick
-TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
+TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
return curTick;
}
void
-TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
+TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
{
//No internal storage to update, jusst return
return;
void
-TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
+TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
{
pkt = _pkt;
Event::schedule(t);
// Now do the access.
if (fault == NoFault) {
- Packet *pkt =
+ PacketPtr pkt =
new Packet(req, Packet::ReadReq, Packet::Broadcast);
pkt->dataDynamic<T>(new T);
void
-TimingSimpleCPU::completeIfetch(Packet *pkt)
+TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
// received a response from the icache: execute the received
// instruction
}
bool
-TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
+TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
// waiting to transmit
assert(cpu->ifetch_pkt != NULL);
assert(cpu->_status == IcacheRetry);
- Packet *tmp = cpu->ifetch_pkt;
+ PacketPtr tmp = cpu->ifetch_pkt;
if (sendTiming(tmp)) {
cpu->_status = IcacheWaitResponse;
cpu->ifetch_pkt = NULL;
}
void
-TimingSimpleCPU::completeDataAccess(Packet *pkt)
+TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
{
// received a response from the dcache: complete the load or store
// instruction
}
bool
-TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
+TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
// waiting to transmit
assert(cpu->dcache_pkt != NULL);
assert(cpu->_status == DcacheRetry);
- Packet *tmp = cpu->dcache_pkt;
+ PacketPtr tmp = cpu->dcache_pkt;
if (sendTiming(tmp)) {
cpu->_status = DcacheWaitResponse;
// memory system takes ownership of packet
protected:
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
struct TickEvent : public Event
{
- Packet *pkt;
+ PacketPtr pkt;
TimingSimpleCPU *cpu;
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
const char *description() { return "Timing CPU clock event"; }
- void schedule(Packet *_pkt, Tick t);
+ void schedule(PacketPtr _pkt, Tick t);
};
};
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
IcachePort icachePort;
DcachePort dcachePort;
- Packet *ifetch_pkt;
- Packet *dcache_pkt;
+ PacketPtr ifetch_pkt;
+ PacketPtr dcache_pkt;
int cpu_id;
Tick previousTick;
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
void fetch();
- void completeIfetch(Packet *);
- void completeDataAccess(Packet *);
+ void completeIfetch(PacketPtr );
+ void completeDataAccess(PacketPtr );
void advanceInst(Fault fault);
private:
void completeDrain();
}
Tick
-AlphaConsole::read(Packet *pkt)
+AlphaConsole::read(PacketPtr pkt)
{
/** XXX Do we want to push the addr munging to a bus brige or something? So
}
Tick
-AlphaConsole::write(Packet *pkt)
+AlphaConsole::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
/**
* memory mapped reads and writes
*/
- virtual Tick read(Packet *pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
/**
* standard serialization routines for checkpointing
}
Tick
-BadDevice::read(Packet *pkt)
+BadDevice::read(PacketPtr pkt)
{
panic("Device %s not imlpmented\n", devname);
}
Tick
-BadDevice::write(Packet *pkt)
+BadDevice::write(PacketPtr pkt)
{
panic("Device %s not imlpmented\n", devname);
}
*/
BadDevice(Params *p);
- virtual Tick read(Packet *pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
};
#endif // __DEV_BADDEV_HH__
Tick
-IGbE::writeConfig(Packet *pkt)
+IGbE::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
}
Tick
-IGbE::read(Packet *pkt)
+IGbE::read(PacketPtr pkt)
{
int bar;
Addr daddr;
}
Tick
-IGbE::write(Packet *pkt)
+IGbE::write(PacketPtr pkt)
{
int bar;
Addr daddr;
IGbE(Params *params);
~IGbE() {;}
- virtual Tick read(Packet *pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
- virtual Tick writeConfig(Packet *pkt);
+ virtual Tick writeConfig(PacketPtr pkt);
bool ethRxPkt(EthPacketPtr packet);
void ethTxDone();
////
Tick
-IdeController::readConfig(Packet *pkt)
+IdeController::readConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
Tick
-IdeController::writeConfig(Packet *pkt)
+IdeController::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC) {
Tick
-IdeController::read(Packet *pkt)
+IdeController::read(PacketPtr pkt)
{
Addr offset;
IdeChannel channel;
}
Tick
-IdeController::write(Packet *pkt)
+IdeController::write(PacketPtr pkt)
{
Addr offset;
IdeChannel channel;
IdeController(Params *p);
~IdeController();
- virtual Tick writeConfig(Packet *pkt);
- virtual Tick readConfig(Packet *pkt);
+ virtual Tick writeConfig(PacketPtr pkt);
+ virtual Tick readConfig(PacketPtr pkt);
void setDmaComplete(IdeDisk *disk);
* @param pkt Packet describing what is to be read
* @return The amount of time to complete this request
*/
- virtual Tick read(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
/**
* Write a done field for a given target.
* @param pkt Packet describing what is to be written
* @return The amount of time to complete this request
*/
- virtual Tick write(Packet *pkt);
+ virtual Tick write(PacketPtr pkt);
/**
* Serialize this object to the given output stream.
Tick
-PioPort::recvAtomic(Packet *pkt)
+PioPort::recvAtomic(PacketPtr pkt)
{
return pkt->isRead() ? device->read(pkt) : device->write(pkt);
}
{ }
bool
-DmaPort::recvTiming(Packet *pkt)
+DmaPort::recvTiming(PacketPtr pkt)
{
void
DmaPort::recvRetry()
{
- Packet* pkt = transmitList.front();
+ PacketPtr pkt = transmitList.front();
bool result = true;
while (result && transmitList.size()) {
DPRINTF(DMA, "Retry on Packet %#x with senderState: %#x\n",
for (ChunkGenerator gen(addr, size, peerBlockSize());
!gen.done(); gen.next()) {
Request *req = new Request(gen.addr(), gen.size(), 0);
- Packet *pkt = new Packet(req, cmd, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, cmd, Packet::Broadcast);
// Increment the data pointer on a write
if (data)
void
-DmaPort::sendDma(Packet *pkt, bool front)
+DmaPort::sendDma(PacketPtr pkt, bool front)
{
// some kind of selction between access methods
// more work is going to have to be done to make
/** The device that this port serves. */
PioDevice *device;
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop);
};
DmaDevice *device;
- std::list<Packet*> transmitList;
+ std::list<PacketPtr> transmitList;
/** The system that device/port are in. This is used to select which mode
* we are currently operating in. */
* here.*/
Event *drainEvent;
- virtual bool recvTiming(Packet *pkt);
- virtual Tick recvAtomic(Packet *pkt)
+ virtual bool recvTiming(PacketPtr pkt);
+ virtual Tick recvAtomic(PacketPtr pkt)
{ panic("dma port shouldn't be used for pio access."); }
- virtual void recvFunctional(Packet *pkt)
+ virtual void recvFunctional(PacketPtr pkt)
{ panic("dma port shouldn't be used for pio access."); }
virtual void recvStatusChange(Status status)
AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
- void sendDma(Packet *pkt, bool front = false);
+ void sendDma(PacketPtr pkt, bool front = false);
public:
DmaPort(DmaDevice *dev, System *s);
* @param pkt Packet describing this request
* @return number of ticks it took to complete
*/
- virtual Tick read(Packet *pkt) = 0;
+ virtual Tick read(PacketPtr pkt) = 0;
/** Pure virtual function that the device must implement. Called when a
* write command is recieved by the port.
* @param pkt Packet describing this request
* @return number of ticks it took to complete
*/
- virtual Tick write(Packet *pkt) = 0;
+ virtual Tick write(PacketPtr pkt) = 0;
public:
/** Params struct which is extended through each device based on
}
Tick
-IsaFake::read(Packet *pkt)
+IsaFake::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
}
Tick
-IsaFake::write(Packet *pkt)
+IsaFake::write(PacketPtr pkt)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
pkt->result = Packet::Success;
* @param pkt The memory request.
* @param data Where to put the data.
*/
- virtual Tick read(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
/**
* All writes are simply ignored.
* @param pkt The memory request.
* @param data the data to not write.
*/
- virtual Tick write(Packet *pkt);
+ virtual Tick write(PacketPtr pkt);
};
#endif // __TSUNAMI_FAKE_HH__
* This is to write to the PCI general configuration registers
*/
Tick
-NSGigE::writeConfig(Packet *pkt)
+NSGigE::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
* spec sheet
*/
Tick
-NSGigE::read(Packet *pkt)
+NSGigE::read(PacketPtr pkt)
{
assert(ioEnable);
}
Tick
-NSGigE::write(Packet *pkt)
+NSGigE::write(PacketPtr pkt)
{
assert(ioEnable);
~NSGigE();
const Params *params() const { return (const Params *)_params; }
- virtual Tick writeConfig(Packet *pkt);
+ virtual Tick writeConfig(PacketPtr pkt);
- virtual Tick read(Packet *pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
Tick
-PciConfigAll::read(Packet *pkt)
+PciConfigAll::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
}
Tick
-PciConfigAll::write(Packet *pkt)
+PciConfigAll::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
panic("Attempting to write to config space on non-existant device\n");
* @param pkt Contains information about the read operation
* @return Amount of time to do the read
*/
- virtual Tick read(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
/**
* Write to PCI config spcae. If the device does not exit the simulator
* @return Amount of time to do the read
*/
- virtual Tick write(Packet *pkt);
+ virtual Tick write(PacketPtr pkt);
void addressRanges(AddrRangeList &range_list);
Tick
-PciDev::PciConfigPort::recvAtomic(Packet *pkt)
+PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= configAddr &&
}
Tick
-PciDev::readConfig(Packet *pkt)
+PciDev::readConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
}
Tick
-PciDev::writeConfig(Packet *pkt)
+PciDev::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
protected:
PciDev *device;
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop);
* for normal operations that it does not need to override.
* @param pkt packet containing the write the offset into config space
*/
- virtual Tick writeConfig(Packet *pkt);
+ virtual Tick writeConfig(PacketPtr pkt);
/**
* for normal operations that it does not need to override.
* @param pkt packet containing the write the offset into config space
*/
- virtual Tick readConfig(Packet *pkt);
+ virtual Tick readConfig(PacketPtr pkt);
public:
Addr pciToDma(Addr pciAddr) const
* I/O read of device register
*/
Tick
-Device::read(Packet *pkt)
+Device::read(PacketPtr pkt)
{
assert(config.command & PCI_CMD_MSE);
assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
* I/O write of device register
*/
Tick
-Device::write(Packet *pkt)
+Device::write(PacketPtr pkt)
{
assert(config.command & PCI_CMD_MSE);
assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
* Memory Interface
*/
public:
- virtual Tick read(Packet *pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
virtual void resume();
void prepareIO(int cpu, int index);
}
Tick
-TsunamiCChip::read(Packet *pkt)
+TsunamiCChip::read(PacketPtr pkt)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
}
Tick
-TsunamiCChip::write(Packet *pkt)
+TsunamiCChip::write(PacketPtr pkt)
{
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;
*/
TsunamiCChip(Params *p);
- virtual Tick read(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick write(PacketPtr pkt);
/**
* post an RTC interrupt to the CPU
}
Tick
-TsunamiIO::read(Packet *pkt)
+TsunamiIO::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
}
Tick
-TsunamiIO::write(Packet *pkt)
+TsunamiIO::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
*/
TsunamiIO(Params *p);
- virtual Tick read(Packet *pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
/**
* Post an PIC interrupt to the CPU via the CChip
}
Tick
-TsunamiPChip::read(Packet *pkt)
+TsunamiPChip::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
}
Tick
-TsunamiPChip::write(Packet *pkt)
+TsunamiPChip::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr calcConfigAddr(int bus, int dev, int func);
- virtual Tick read(Packet *pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
/**
* Serialize this object to the given output stream.
}
Tick
-Uart8250::read(Packet *pkt)
+Uart8250::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
}
Tick
-Uart8250::write(Packet *pkt)
+Uart8250::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
public:
Uart8250(Params *p);
- virtual Tick read(Packet *pkt);
- virtual Tick write(Packet *pkt);
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
virtual void addressRanges(AddrRangeList &range_list);
/** Function called by the port when the bus is receiving a Timing
* transaction.*/
bool
-Bridge::BridgePort::recvTiming(Packet *pkt)
+Bridge::BridgePort::recvTiming(PacketPtr pkt)
{
DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n",
pkt->getSrc(), pkt->getDest(), pkt->getAddr());
bool
-Bridge::BridgePort::queueForSendTiming(Packet *pkt)
+Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
{
if (queueFull())
return false;
assert(buf->ready <= curTick);
- Packet *pkt = buf->pkt;
+ PacketPtr pkt = buf->pkt;
DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n",
buf->origSrc, pkt->getDest(), pkt->getAddr());
/** Function called by the port when the bus is receiving a Atomic
* transaction.*/
Tick
-Bridge::BridgePort::recvAtomic(Packet *pkt)
+Bridge::BridgePort::recvAtomic(PacketPtr pkt)
{
return otherPort->sendAtomic(pkt) + delay;
}
/** Function called by the port when the bus is receiving a Functional
* transaction.*/
void
-Bridge::BridgePort::recvFunctional(Packet *pkt)
+Bridge::BridgePort::recvFunctional(PacketPtr pkt)
{
std::list<PacketBuffer*>::iterator i;
bool pktContinue = true;
public:
Tick ready;
- Packet *pkt;
+ PacketPtr pkt;
Packet::SenderState *origSenderState;
short origSrc;
bool expectResponse;
- PacketBuffer(Packet *_pkt, Tick t)
+ PacketBuffer(PacketPtr _pkt, Tick t)
: ready(t), pkt(_pkt),
origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()),
expectResponse(_pkt->needsResponse())
pkt->senderState = this;
}
- void fixResponse(Packet *pkt)
+ void fixResponse(PacketPtr pkt)
{
assert(pkt->senderState == this);
pkt->setDest(origSrc);
*/
bool queueFull() { return (sendQueue.size() == queueLimit); }
- bool queueForSendTiming(Packet *pkt);
+ bool queueForSendTiming(PacketPtr pkt);
void finishSend(PacketBuffer *buf);
/** When receiving a timing request from the peer port,
pass it to the bridge. */
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
/** When receiving a retry request from the peer port,
pass it to the bridge. */
/** When receiving a Atomic requestfrom the peer port,
pass it to the bridge. */
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
/** When receiving a Functional request from the peer port,
pass it to the bridge. */
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
/** When receiving a status changefrom the peer port,
pass it to the bridge. */
/** Function called by the port when the bus is receiving a Timing
* transaction.*/
bool
-Bus::recvTiming(Packet *pkt)
+Bus::recvTiming(PacketPtr pkt)
{
Port *port;
DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n",
}
Tick
-Bus::atomicSnoop(Packet *pkt)
+Bus::atomicSnoop(PacketPtr pkt)
{
std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
Tick response_time = 0;
}
void
-Bus::functionalSnoop(Packet *pkt)
+Bus::functionalSnoop(PacketPtr pkt)
{
std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
}
bool
-Bus::timingSnoop(Packet *pkt)
+Bus::timingSnoop(PacketPtr pkt)
{
std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc());
bool success = true;
/** Function called by the port when the bus is receiving a Atomic
* transaction.*/
Tick
-Bus::recvAtomic(Packet *pkt)
+Bus::recvAtomic(PacketPtr pkt)
{
DPRINTF(Bus, "recvAtomic: packet src %d dest %d addr 0x%x cmd %s\n",
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
/** Function called by the port when the bus is receiving a Functional
* transaction.*/
void
-Bus::recvFunctional(Packet *pkt)
+Bus::recvFunctional(PacketPtr pkt)
{
DPRINTF(Bus, "recvFunctional: packet src %d dest %d addr 0x%x cmd %s\n",
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
/** Function called by the port when the bus is recieving a Timing
transaction.*/
- bool recvTiming(Packet *pkt);
+ bool recvTiming(PacketPtr pkt);
/** Function called by the port when the bus is recieving a Atomic
transaction.*/
- Tick recvAtomic(Packet *pkt);
+ Tick recvAtomic(PacketPtr pkt);
/** Function called by the port when the bus is recieving a Functional
transaction.*/
- void recvFunctional(Packet *pkt);
+ void recvFunctional(PacketPtr pkt);
/** Timing function called by port when it is once again able to process
* requests. */
std::vector<int> findSnoopPorts(Addr addr, int id);
/** Snoop all relevant ports atomicly. */
- Tick atomicSnoop(Packet *pkt);
+ Tick atomicSnoop(PacketPtr pkt);
/** Snoop all relevant ports functionally. */
- void functionalSnoop(Packet *pkt);
+ void functionalSnoop(PacketPtr pkt);
/** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want
* the snoop to happen
* @return True if succeds.
*/
- bool timingSnoop(Packet *pkt);
+ bool timingSnoop(PacketPtr pkt);
/** Process address range request.
* @param resp addresses that we can respond to
/** When reciving a timing request from the peer port (at id),
pass it to the bus. */
- virtual bool recvTiming(Packet *pkt)
+ virtual bool recvTiming(PacketPtr pkt)
{ pkt->setSrc(id); return bus->recvTiming(pkt); }
/** When reciving a Atomic requestfrom the peer port (at id),
pass it to the bus. */
- virtual Tick recvAtomic(Packet *pkt)
+ virtual Tick recvAtomic(PacketPtr pkt)
{ pkt->setSrc(id); return bus->recvAtomic(pkt); }
/** When reciving a Functional requestfrom the peer port (at id),
pass it to the bus. */
- virtual void recvFunctional(Packet *pkt)
+ virtual void recvFunctional(PacketPtr pkt)
{ pkt->setSrc(id); bus->recvFunctional(pkt); }
/** When reciving a status changefrom the peer port (at id),
}
bool
-BaseCache::CachePort::recvTiming(Packet *pkt)
+BaseCache::CachePort::recvTiming(PacketPtr pkt)
{
if (isCpuSide
&& !pkt->req->isUncacheable()
}
Tick
-BaseCache::CachePort::recvAtomic(Packet *pkt)
+BaseCache::CachePort::recvAtomic(PacketPtr pkt)
{
return cache->doAtomicAccess(pkt, isCpuSide);
}
void
-BaseCache::CachePort::recvFunctional(Packet *pkt)
+BaseCache::CachePort::recvFunctional(PacketPtr pkt)
{
//Check storage here first
- list<Packet *>::iterator i = drainList.begin();
- list<Packet *>::iterator end = drainList.end();
+ list<PacketPtr>::iterator i = drainList.begin();
+ list<PacketPtr>::iterator end = drainList.end();
for (; i != end; ++i) {
- Packet * target = *i;
+ PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->intersect(pkt)) {
void
BaseCache::CachePort::recvRetry()
{
- Packet *pkt;
+ PacketPtr pkt;
assert(waitingOnRetry);
if (!drainList.empty()) {
DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
pkt = cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;
//Copy the packet, it may be modified/destroyed elsewhere
- Packet * copyPkt = new Packet(*pkt);
+ PacketPtr copyPkt = new Packet(*pkt);
copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
mshr->pkt = copyPkt;
pkt = NULL;
}
-BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
+BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, PacketPtr _pkt)
: Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
{
this->setFlags(AutoDelete);
pkt = cachePort->cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;
//Copy the packet, it may be modified/destroyed elsewhere
- Packet * copyPkt = new Packet(*pkt);
+ PacketPtr copyPkt = new Packet(*pkt);
copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
mshr->pkt = copyPkt;
CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
bool waitingOnRetry;
- std::list<Packet *> drainList;
+ std::list<PacketPtr> drainList;
};
struct CacheEvent : public Event
{
CachePort *cachePort;
- Packet *pkt;
+ PacketPtr pkt;
CacheEvent(CachePort *_cachePort);
- CacheEvent(CachePort *_cachePort, Packet *_pkt);
+ CacheEvent(CachePort *_cachePort, PacketPtr _pkt);
void process();
const char *description();
};
private:
//To be defined in cache_impl.hh not in base class
- virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+ virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
{
fatal("No implementation");
}
- virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
+ virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide)
{
fatal("No implementation");
}
- virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
+ virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
{
fatal("No implementation");
}
}
}
- virtual Packet *getPacket()
+ virtual PacketPtr getPacket()
{
fatal("No implementation");
}
- virtual Packet *getCoherencePacket()
+ virtual PacketPtr getCoherencePacket()
{
fatal("No implementation");
}
- virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
+ virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
{
fatal("No implementation");
}
- virtual void sendCoherenceResult(Packet* &pkt, MSHR* mshr, bool success)
+ virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* mshr, bool success)
{
fatal("No implementation");
* @param pkt The request being responded to.
* @param time The time the response is ready.
*/
- void respond(Packet *pkt, Tick time)
+ void respond(PacketPtr pkt, Tick time)
{
if (pkt->needsResponse()) {
CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
* @param pkt The request to respond to.
* @param time The time the response is ready.
*/
- void respondToMiss(Packet *pkt, Tick time)
+ void respondToMiss(PacketPtr pkt, Tick time)
{
if (!pkt->req->isUncacheable()) {
missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
* Suppliess the data if cache to cache transfers are enabled.
* @param pkt The bus transaction to fulfill.
*/
- void respondToSnoop(Packet *pkt, Tick time)
+ void respondToSnoop(PacketPtr pkt, Tick time)
{
assert (pkt->needsResponse());
CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
* A permanent mem req to always be used to cause invalidations.
* Used to append to target list, to cause an invalidation.
*/
- Packet * invalidatePkt;
+ PacketPtr invalidatePkt;
Request *invalidateReq;
public:
/** Instantiates a basic cache object. */
Cache(const std::string &_name, Params ¶ms);
- virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
+ virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort,
bool isCpuSide);
- virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
+ virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide);
- virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
+ virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide);
virtual void recvStatusChange(Port::Status status, bool isCpuSide);
* @param pkt The request to perform.
* @return The result of the access.
*/
- bool access(Packet * &pkt);
+ bool access(PacketPtr &pkt);
/**
* Selects a request to send on the bus.
* @return The memory request to service.
*/
- virtual Packet * getPacket();
+ virtual PacketPtr getPacket();
/**
* Was the request was sent successfully?
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
- virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
+ virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
/**
* Was the CSHR request was sent successfully?
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
- virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success);
+ virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
/**
* Handles a response (cache line fill/write ack) from the bus.
* @param pkt The request being responded to.
*/
- void handleResponse(Packet * &pkt);
+ void handleResponse(PacketPtr &pkt);
/**
* Selects a coherence message to forward to lower levels of the hierarchy.
* @return The coherence message to forward.
*/
- virtual Packet * getCoherencePacket();
+ virtual PacketPtr getCoherencePacket();
/**
* Snoops bus transactions to maintain coherence.
* @param pkt The current bus transaction.
*/
- void snoop(Packet * &pkt);
+ void snoop(PacketPtr &pkt);
- void snoopResponse(Packet * &pkt);
+ void snoopResponse(PacketPtr &pkt);
/**
* Invalidates the block containing address if found.
* request.
* @return The estimated completion time.
*/
- Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
+ Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
/**
* Snoop for the provided request in the cache and return the estimated
* request.
* @return The estimated completion time.
*/
- Tick snoopProbe(Packet * &pkt);
+ Tick snoopProbe(PacketPtr &pkt);
};
#endif // __CACHE_HH__
template<class TagStore, class Buffering, class Coherence>
bool
Cache<TagStore,Buffering,Coherence>::
-doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
{
if (isCpuSide)
{
template<class TagStore, class Buffering, class Coherence>
Tick
Cache<TagStore,Buffering,Coherence>::
-doAtomicAccess(Packet *pkt, bool isCpuSide)
+doAtomicAccess(PacketPtr pkt, bool isCpuSide)
{
if (isCpuSide)
{
template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::
-doFunctionalAccess(Packet *pkt, bool isCpuSide)
+doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
{
if (isCpuSide)
{
template<class TagStore, class Buffering, class Coherence>
-Packet *
+PacketPtr
Cache<TagStore,Buffering,Coherence>::getPacket()
{
assert(missQueue->havePending());
- Packet * pkt = missQueue->getPacket();
+ PacketPtr pkt = missQueue->getPacket();
if (pkt) {
if (!pkt->req->isUncacheable()) {
if (pkt->cmd == Packet::HardPFReq)
template<class TagStore, class Buffering, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
+Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
{
BlkType *blk = NULL;
if (pkt->senderState) {
}
template<class TagStore, class Buffering, class Coherence>
-Packet *
+PacketPtr
Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
{
return coherence->getPacket();
template<class TagStore, class Buffering, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
+Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
MSHR *cshr,
bool success)
{
template<class TagStore, class Buffering, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
+Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
{
if (pkt->req->isUncacheable()) {
//Can't get a hit on an uncacheable address
template<class TagStore, class Buffering, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
+Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
{
//Need to handle the response, if NACKED
if (pkt->flags & NACKED_LINE) {
*/
template<class TagStore, class Buffering, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
+Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
CachePort* otherSidePort)
{
// MemDebug::cacheProbe(pkt);
MSHR::TargetList::iterator i = targets->begin();
MSHR::TargetList::iterator end = targets->end();
for (; i != end; ++i) {
- Packet * target = *i;
+ PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->isWrite() && target->intersect(pkt)) {
}
}
for (int i = 0; i < writes.size(); ++i) {
- Packet * write = writes[i]->pkt;
+ PacketPtr write = writes[i]->pkt;
if (write->intersect(pkt)) {
warn("Found outstanding write on an non-update probe");
uint8_t* pkt_data;
Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
(blk)? blk->status : 0);
- Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
+ PacketPtr busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
busPkt->allocate();
// Handle writebacks if needed
while (!writebacks.empty()){
- Packet *wbPkt = writebacks.front();
+ PacketPtr wbPkt = writebacks.front();
memSidePort->sendAtomic(wbPkt);
writebacks.pop_front();
delete wbPkt;
bool
-CoherenceProtocol::invalidateTrans(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::invalidateTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk, MSHR *mshr,
CacheBlk::State & new_state)
{
bool
-CoherenceProtocol::supplyTrans(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::supplyTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state
bool
-CoherenceProtocol::supplyAndGotoSharedTrans(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::supplyAndGotoSharedTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
bool
-CoherenceProtocol::supplyAndGotoOwnedTrans(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::supplyAndGotoOwnedTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
bool
-CoherenceProtocol::supplyAndInvalidateTrans(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::supplyAndInvalidateTrans(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
}
bool
-CoherenceProtocol::assertShared(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::assertShared(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
CacheBlk::State
-CoherenceProtocol::getNewState(Packet * &pkt, CacheBlk::State oldState)
+CoherenceProtocol::getNewState(PacketPtr &pkt, CacheBlk::State oldState)
{
CacheBlk::State state = oldState & stateMask;
int cmd_idx = pkt->cmdToIndex();
bool
-CoherenceProtocol::handleBusRequest(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::handleBusRequest(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk,
MSHR *mshr,
CacheBlk::State & new_state)
}
bool
-CoherenceProtocol::nullTransition(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::nullTransition(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk, MSHR *mshr,
CacheBlk::State & new_state)
{
bool
-CoherenceProtocol::invalidTransition(BaseCache *cache, Packet * &pkt,
+CoherenceProtocol::invalidTransition(BaseCache *cache, PacketPtr &pkt,
CacheBlk *blk, MSHR *mshr,
CacheBlk::State & new_state)
{
* @param oldState The current block state.
* @return The new state.
*/
- CacheBlk::State getNewState(Packet * &pkt,
+ CacheBlk::State getNewState(PacketPtr &pkt,
CacheBlk::State oldState);
/**
* @param new_state The new coherence state of the block.
* @return True if the request should be satisfied locally.
*/
- bool handleBusRequest(BaseCache *cache, Packet * &pkt, CacheBlk *blk,
+ bool handleBusRequest(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk,
MSHR *mshr, CacheBlk::State &new_state);
protected:
/** Snoop function type. */
- typedef bool (*SnoopFuncType)(BaseCache *, Packet *&, CacheBlk *,
+ typedef bool (*SnoopFuncType)(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
//
/**
* Do nothing transition.
*/
- static bool nullTransition(BaseCache *, Packet *&, CacheBlk *,
+ static bool nullTransition(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Invalid transition, basically panic.
*/
- static bool invalidTransition(BaseCache *, Packet *&, CacheBlk *,
+ static bool invalidTransition(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Invalidate block, move to Invalid state.
*/
- static bool invalidateTrans(BaseCache *, Packet *&, CacheBlk *,
+ static bool invalidateTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Supply data, no state transition.
*/
- static bool supplyTrans(BaseCache *, Packet *&, CacheBlk *,
+ static bool supplyTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Supply data and go to Shared state.
*/
- static bool supplyAndGotoSharedTrans(BaseCache *, Packet *&, CacheBlk *,
+ static bool supplyAndGotoSharedTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Supply data and go to Owned state.
*/
- static bool supplyAndGotoOwnedTrans(BaseCache *, Packet *&, CacheBlk *,
+ static bool supplyAndGotoOwnedTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Invalidate block, supply data, and go to Invalid state.
*/
- static bool supplyAndInvalidateTrans(BaseCache *, Packet *&, CacheBlk *,
+ static bool supplyAndInvalidateTrans(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* Assert the shared line for a block that is shared/exclusive.
*/
- static bool assertShared(BaseCache *, Packet *&, CacheBlk *,
+ static bool assertShared(BaseCache *, PacketPtr &, CacheBlk *,
MSHR *, CacheBlk::State&);
/**
* This policy does not forward invalidates, return NULL.
* @return NULL.
*/
- Packet * getPacket()
+ PacketPtr getPacket()
{
return NULL;
}
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
- void sendResult(Packet * &pkt, MSHR* cshr, bool success)
+ void sendResult(PacketPtr &pkt, MSHR* cshr, bool success)
{
//Don't do coherence
return;
* @param current The current block state.
* @return The new state.
*/
- CacheBlk::State getNewState(Packet * &pkt, CacheBlk::State current)
+ CacheBlk::State getNewState(PacketPtr &pkt, CacheBlk::State current)
{
return protocol->getNewState(pkt, current);
}
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state Return the new state for the block.
*/
- bool handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
+ bool handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
CacheBlk::State &new_state)
{
// assert(mshr == NULL);
bool hasProtocol() { return true; }
- void propogateInvalidate(Packet *pkt, bool isTiming)
+ void propogateInvalidate(PacketPtr pkt, bool isTiming)
{
//For now we do nothing, asssumes simple coherence is top level of cache
return;
{
}
-Packet *
+PacketPtr
UniCoherence::getPacket()
{
- Packet* pkt = cshrs.getReq();
+ PacketPtr pkt = cshrs.getReq();
return pkt;
}
void
-UniCoherence::sendResult(Packet * &pkt, MSHR* cshr, bool success)
+UniCoherence::sendResult(PacketPtr &pkt, MSHR* cshr, bool success)
{
if (success)
{
* @todo add support for returning slave requests, not doing them here.
*/
bool
-UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
+UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
CacheBlk::State &new_state)
{
new_state = 0;
}
void
-UniCoherence::propogateInvalidate(Packet *pkt, bool isTiming)
+UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming)
{
if (pkt->isInvalidate()) {
if (isTiming) {
// Forward to other caches
- Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+ PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
cshrs.allocate(tmp);
cache->setSlaveRequest(Request_Coherence, curTick);
if (cshrs.isFull())
cache->setBlockedForSnoop(Blocked_Coherence);
}
else {
- Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+ PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
cache->cpuSidePort->sendAtomic(tmp);
delete tmp;
}
* @param current The current block state.
* @return The new state.
*/
- CacheBlk::State getNewState(Packet * &pkt, CacheBlk::State current)
+ CacheBlk::State getNewState(PacketPtr &pkt, CacheBlk::State current)
{
if (pkt->senderState) //Blocking Buffers don't get mshrs
{
* Return outstanding invalidate to forward.
* @return The next invalidate to forward to lower levels of cache.
*/
- Packet * getPacket();
+ PacketPtr getPacket();
/**
* Was the CSHR request was sent successfully?
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
- void sendResult(Packet * &pkt, MSHR* cshr, bool success);
+ void sendResult(PacketPtr &pkt, MSHR* cshr, bool success);
/**
* Handle snooped bus requests.
* @param new_state The new coherence state of the block.
* @return True if the request should be satisfied locally.
*/
- bool handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
+ bool handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
CacheBlk::State &new_state);
/**
bool hasProtocol() { return false; }
- void propogateInvalidate(Packet *pkt, bool isTiming);
+ void propogateInvalidate(PacketPtr pkt, bool isTiming);
};
#endif //__UNI_COHERENCE_HH__
prefetcher = _prefetcher;
}
void
-BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
+BlockingBuffer::handleMiss(PacketPtr &pkt, int blk_size, Tick time)
{
Addr blk_addr = pkt->getAddr() & ~(Addr)(blk_size - 1);
if (pkt->isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
cache->setMasterRequest(Request_MSHR, time);
}
-Packet *
+PacketPtr
BlockingBuffer::getPacket()
{
if (miss.pkt && !miss.inService) {
}
void
-BlockingBuffer::setBusCmd(Packet * &pkt, Packet::Command cmd)
+BlockingBuffer::setBusCmd(PacketPtr &pkt, Packet::Command cmd)
{
MSHR *mshr = (MSHR*) pkt->senderState;
mshr->originalCmd = pkt->cmd;
}
void
-BlockingBuffer::restoreOrigCmd(Packet * &pkt)
+BlockingBuffer::restoreOrigCmd(PacketPtr &pkt)
{
pkt->cmdOverride(((MSHR*)(pkt->senderState))->originalCmd);
}
void
-BlockingBuffer::markInService(Packet * &pkt, MSHR* mshr)
+BlockingBuffer::markInService(PacketPtr &pkt, MSHR* mshr)
{
if (!pkt->isCacheFill() && pkt->isWrite()) {
// Forwarding a write/ writeback, don't need to change
}
void
-BlockingBuffer::handleResponse(Packet * &pkt, Tick time)
+BlockingBuffer::handleResponse(PacketPtr &pkt, Tick time)
{
if (pkt->isCacheFill()) {
// targets were handled in the cache tags
if (((MSHR*)(pkt->senderState))->hasTargets()) {
// Should only have 1 target if we had any
assert(((MSHR*)(pkt->senderState))->getNumTargets() == 1);
- Packet * target = ((MSHR*)(pkt->senderState))->getTarget();
+ PacketPtr target = ((MSHR*)(pkt->senderState))->getTarget();
((MSHR*)(pkt->senderState))->popTarget();
if (pkt->isRead()) {
memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), target->getSize());
BlockingBuffer::squash(int threadNum)
{
if (miss.threadNum == threadNum) {
- Packet * target = miss.getTarget();
+ PacketPtr target = miss.getTarget();
miss.popTarget();
assert(0/*target->req->getThreadNum()*/ == threadNum);
target = NULL;
{
// Generate request
Request * req = new Request(addr, size, 0);
- Packet * pkt = new Packet(req, Packet::Writeback, -1);
+ PacketPtr pkt = new Packet(req, Packet::Writeback, -1);
pkt->allocate();
if (data) {
memcpy(pkt->getPtr<uint8_t>(), data, size);
void
-BlockingBuffer::doWriteback(Packet * &pkt)
+BlockingBuffer::doWriteback(PacketPtr &pkt)
{
writebacks[0/*pkt->req->getThreadNum()*/]++;
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
- void handleMiss(Packet * &pkt, int blk_size, Tick time);
+ void handleMiss(PacketPtr &pkt, int blk_size, Tick time);
/**
* Fetch the block for the given address and buffer the given target.
* @param target The target for the fetch.
*/
MSHR* fetchBlock(Addr addr, int blk_size, Tick time,
- Packet * &target)
+ PacketPtr &target)
{
fatal("Unimplemented");
}
* Selects a outstanding pktuest to service.
* @return The pktuest to service, NULL if none found.
*/
- Packet * getPacket();
+ PacketPtr getPacket();
/**
* Set the command to the given bus command.
* @param pkt The request to update.
* @param cmd The bus command to use.
*/
- void setBusCmd(Packet * &pkt, Packet::Command cmd);
+ void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
* @param pkt The request to reset.
*/
- void restoreOrigCmd(Packet * &pkt);
+ void restoreOrigCmd(PacketPtr &pkt);
/**
* Marks a pktuest as in service (sent on the bus). This can have side
* are successfully sent.
* @param pkt The request that was sent on the bus.
*/
- void markInService(Packet * &pkt, MSHR* mshr);
+ void markInService(PacketPtr &pkt, MSHR* mshr);
/**
* Frees the resources of the pktuest and unblock the cache.
* @param pkt The request that has been satisfied.
* @param time The time when the pktuest is satisfied.
*/
- void handleResponse(Packet * &pkt, Tick time);
+ void handleResponse(PacketPtr &pkt, Tick time);
/**
* Removes all outstanding pktuests for a given thread number. If a request
* Perform a writeback pktuest.
* @param pkt The writeback request.
*/
- void doWriteback(Packet * &pkt);
+ void doWriteback(PacketPtr &pkt);
/**
* Returns true if there are outstanding pktuests.
* @param mshr The mshr to add a target to.
* @param pkt The target to add.
*/
- void addTarget(MSHR *mshr, Packet * &pkt)
+ void addTarget(MSHR *mshr, PacketPtr &pkt)
{
fatal("Shouldn't call this on a blocking buffer.");
}
}
MSHR*
-MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
+MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time)
{
MSHR* mshr = mq.allocate(pkt, size);
mshr->order = order++;
MSHR*
-MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
+MissQueue::allocateWrite(PacketPtr &pkt, int size, Tick time)
{
MSHR* mshr = wb.allocate(pkt,size);
mshr->order = order++;
* @todo Remove SW prefetches on mshr hits.
*/
void
-MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
+MissQueue::handleMiss(PacketPtr &pkt, int blkSize, Tick time)
{
// if (!cache->isTopLevel())
if (prefetchMiss) prefetcher->handleMiss(pkt, time);
MSHR*
MissQueue::fetchBlock(Addr addr, int blk_size, Tick time,
- Packet * &target)
+ PacketPtr &target)
{
Addr blkAddr = addr & ~(Addr)(blk_size - 1);
assert(mq.findMatch(addr) == NULL);
return mshr;
}
-Packet *
+PacketPtr
MissQueue::getPacket()
{
- Packet * pkt = mq.getReq();
+ PacketPtr pkt = mq.getReq();
if (((wb.isFull() && wb.inServiceMSHRs == 0) || !pkt ||
pkt->time > curTick) && wb.havePending()) {
pkt = wb.getReq();
}
void
-MissQueue::setBusCmd(Packet * &pkt, Packet::Command cmd)
+MissQueue::setBusCmd(PacketPtr &pkt, Packet::Command cmd)
{
assert(pkt->senderState != 0);
MSHR * mshr = (MSHR*)pkt->senderState;
}
void
-MissQueue::restoreOrigCmd(Packet * &pkt)
+MissQueue::restoreOrigCmd(PacketPtr &pkt)
{
pkt->cmd = ((MSHR*)(pkt->senderState))->originalCmd;
}
void
-MissQueue::markInService(Packet * &pkt, MSHR* mshr)
+MissQueue::markInService(PacketPtr &pkt, MSHR* mshr)
{
bool unblock = false;
BlockedCause cause = NUM_BLOCKED_CAUSES;
void
-MissQueue::handleResponse(Packet * &pkt, Tick time)
+MissQueue::handleResponse(PacketPtr &pkt, Tick time)
{
MSHR* mshr = (MSHR*)pkt->senderState;
if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
if (mshr->hasTargets() && pkt->req->isUncacheable()) {
// Should only have 1 target if we had any
assert(num_targets == 1);
- Packet * target = mshr->getTarget();
+ PacketPtr target = mshr->getTarget();
mshr->popTarget();
if (pkt->isRead()) {
memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(),
//Must be a no_allocate with possibly more than one target
assert(mshr->pkt->isNoAllocate());
while (mshr->hasTargets()) {
- Packet * target = mshr->getTarget();
+ PacketPtr target = mshr->getTarget();
mshr->popTarget();
if (pkt->isRead()) {
memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(),
{
// Generate request
Request * req = new Request(addr, size, 0);
- Packet * pkt = new Packet(req, Packet::Writeback, -1);
+ PacketPtr pkt = new Packet(req, Packet::Writeback, -1);
pkt->allocate();
if (data) {
memcpy(pkt->getPtr<uint8_t>(), data, size);
void
-MissQueue::doWriteback(Packet * &pkt)
+MissQueue::doWriteback(PacketPtr &pkt)
{
writebacks[0/*pkt->req->getThreadNum()*/]++;
allocateWrite(pkt, 0, curTick);
* @param time The time the miss occurs.
* @return A pointer to the new MSHR.
*/
- MSHR* allocateMiss(Packet * &pkt, int size, Tick time);
+ MSHR* allocateMiss(PacketPtr &pkt, int size, Tick time);
/**
* Allocate a new WriteBuffer to handle the provided write.
* @param time The time the write occurs.
* @return A pointer to the new write buffer.
*/
- MSHR* allocateWrite(Packet * &pkt, int size, Tick time);
+ MSHR* allocateWrite(PacketPtr &pkt, int size, Tick time);
public:
/**
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
- void handleMiss(Packet * &pkt, int blk_size, Tick time);
+ void handleMiss(PacketPtr &pkt, int blk_size, Tick time);
/**
* Fetch the block for the given address and buffer the given target.
* @param target The target for the fetch.
*/
MSHR* fetchBlock(Addr addr, int blk_size, Tick time,
- Packet * &target);
+ PacketPtr &target);
/**
* Selects a outstanding pktuest to service.
* @return The pktuest to service, NULL if none found.
*/
- Packet * getPacket();
+ PacketPtr getPacket();
/**
* Set the command to the given bus command.
* @param pkt The request to update.
* @param cmd The bus command to use.
*/
- void setBusCmd(Packet * &pkt, Packet::Command cmd);
+ void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
* @param pkt The request to reset.
*/
- void restoreOrigCmd(Packet * &pkt);
+ void restoreOrigCmd(PacketPtr &pkt);
/**
* Marks a pktuest as in service (sent on the bus). This can have side
* are successfully sent.
* @param pkt The request that was sent on the bus.
*/
- void markInService(Packet * &pkt, MSHR* mshr);
+ void markInService(PacketPtr &pkt, MSHR* mshr);
/**
* Collect statistics and free resources of a satisfied pktuest.
* @param pkt The request that has been satisfied.
* @param time The time when the pktuest is satisfied.
*/
- void handleResponse(Packet * &pkt, Tick time);
+ void handleResponse(PacketPtr &pkt, Tick time);
/**
* Removes all outstanding pktuests for a given thread number. If a request
* Perform the given writeback pktuest.
* @param pkt The writeback request.
*/
- void doWriteback(Packet * &pkt);
+ void doWriteback(PacketPtr &pkt);
/**
* Returns true if there are outstanding pktuests.
* @param mshr The mshr to add a target to.
* @param pkt The target to add.
*/
- void addTarget(MSHR *mshr, Packet * &pkt)
+ void addTarget(MSHR *mshr, PacketPtr &pkt)
{
mq.allocateTarget(mshr, pkt);
}
void
MSHR::allocate(Packet::Command cmd, Addr _addr, int size,
- Packet * &target)
+ PacketPtr &target)
{
addr = _addr;
if (target)
* @todo When we have a "global" data flag, might want to copy data here.
*/
void
-MSHR::allocateAsBuffer(Packet * &target)
+MSHR::allocateAsBuffer(PacketPtr &target)
{
addr = target->getAddr();
threadNum = 0/*target->req->getThreadNum()*/;
* Adds a target to an MSHR
*/
void
-MSHR::allocateTarget(Packet * &target)
+MSHR::allocateTarget(PacketPtr &target)
{
//If we append an invalidate and we issued a read to the bus,
//but now have some pending writes, we need to move
//the invalidate to before the first non-read
if (inService && pkt->isRead() && target->isInvalidate()) {
- std::list<Packet *> temp;
+ std::list<PacketPtr> temp;
while (!targets.empty()) {
if (!targets.front()->isRead()) break;
class MSHR {
public:
/** Defines the Data structure of the MSHR targetlist. */
- typedef std::list<Packet *> TargetList;
+ typedef std::list<PacketPtr> TargetList;
/** Target list iterator. */
- typedef std::list<Packet *>::iterator TargetListIterator;
+ typedef std::list<PacketPtr>::iterator TargetListIterator;
/** A list of MSHRs. */
typedef std::list<MSHR *> List;
/** MSHR list iterator. */
/** Thread number of the miss. */
int threadNum;
/** The pktuest that is forwarded to the next level of the hierarchy. */
- Packet * pkt;
+ PacketPtr pkt;
/** The number of currently allocated targets. */
short ntargets;
/** The original pktuesting command. */
* @param pkt The original miss.
*/
void allocate(Packet::Command cmd, Addr addr, int size,
- Packet * &pkt);
+ PacketPtr &pkt);
/**
* Allocate this MSHR as a buffer for the given pktuest.
* @param target The memory pktuest to buffer.
*/
- void allocateAsBuffer(Packet * &target);
+ void allocateAsBuffer(PacketPtr &target);
/**
* Mark this MSHR as free.
* Add a pktuest to the list of targets.
* @param target The target.
*/
- void allocateTarget(Packet * &target);
+ void allocateTarget(PacketPtr &target);
/** A simple constructor. */
MSHR();
* Returns a reference to the first target.
* @return A pointer to the first target.
*/
- Packet * getTarget()
+ PacketPtr getTarget()
{
return targets.front();
}
}
MSHR*
-MSHRQueue::findPending(Packet * &pkt) const
+MSHRQueue::findPending(PacketPtr &pkt) const
{
MSHR::ConstIterator i = pendingList.begin();
MSHR::ConstIterator end = pendingList.end();
}
MSHR*
-MSHRQueue::allocate(Packet * &pkt, int size)
+MSHRQueue::allocate(PacketPtr &pkt, int size)
{
Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1);
assert(!freeList.empty());
}
MSHR*
-MSHRQueue::allocateFetch(Addr addr, int size, Packet * &target)
+MSHRQueue::allocateFetch(Addr addr, int size, PacketPtr &target)
{
MSHR *mshr = freeList.front();
assert(mshr->getNumTargets() == 0);
MSHR *mshr = freeList.front();
assert(mshr->getNumTargets() == 0);
freeList.pop_front();
- Packet * dummy;
+ PacketPtr dummy;
mshr->allocate(Packet::ReadReq, addr, size, dummy);
mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
mshr->inService = true;
MSHR *mshr = *i;
if (mshr->threadNum == threadNum) {
while (mshr->hasTargets()) {
- Packet * target = mshr->getTarget();
+ PacketPtr target = mshr->getTarget();
mshr->popTarget();
assert(0/*target->req->getThreadNum()*/ == threadNum);
* @param pkt The request to find.
* @return A pointer to the earliest matching MSHR.
*/
- MSHR* findPending(Packet * &pkt) const;
+ MSHR* findPending(PacketPtr &pkt) const;
/**
* Allocates a new MSHR for the pktuest and size. This places the request
*
* @pre There are free MSHRs.
*/
- MSHR* allocate(Packet * &pkt, int size = 0);
+ MSHR* allocate(PacketPtr &pkt, int size = 0);
/**
* Allocate a read pktuest for the given address, and places the given
* @param target The first target for the pktuest.
* @return Pointer to the new MSHR.
*/
- MSHR* allocateFetch(Addr addr, int size, Packet * &target);
+ MSHR* allocateFetch(Addr addr, int size, PacketPtr &target);
/**
* Allocate a target list for the given address.
* @param mshr The MSHR to allocate the target to.
* @param pkt The target request.
*/
- void allocateTarget(MSHR* mshr, Packet * &pkt)
+ void allocateTarget(MSHR* mshr, PacketPtr &pkt)
{
mshr->allocateTarget(pkt);
allocatedTargets += 1;
* Returns the pktuest at the head of the pendingList.
* @return The next pktuest to service.
*/
- Packet * getReq() const
+ PacketPtr getReq() const
{
if (pendingList.empty()) {
return NULL;
;
}
-Packet *
+PacketPtr
BasePrefetcher::getPacket()
{
DPRINTF(HWPrefetch, "%s:Requesting a hw_pf to issue\n", cache->name());
return NULL;
}
- Packet * pkt;
+ PacketPtr pkt;
bool keepTrying = false;
do {
pkt = *pf.begin();
}
void
-BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
+BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time)
{
if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && only_data))
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
//Check if miss is in pfq, if so remove it
- std::list<Packet *>::iterator iter = inPrefetch(blkAddr);
+ std::list<PacketPtr>::iterator iter = inPrefetch(blkAddr);
if (iter != pf.end()) {
DPRINTF(HWPrefetch, "%s:Saw a miss to a queued prefetch, removing it\n", cache->name());
pfRemovedMSHR++;
pfIdentified++;
//create a prefetch memreq
Request * prefetchReq = new Request(*addr, blkSize, 0);
- Packet * prefetch;
+ PacketPtr prefetch;
prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1);
prefetch->allocate();
prefetch->req->setThreadContext(pkt->req->getCpuNum(),
}
}
-std::list<Packet *>::iterator
+std::list<PacketPtr>::iterator
BasePrefetcher::inPrefetch(Addr address)
{
//Guaranteed to only be one match, we always check before inserting
- std::list<Packet *>::iterator iter;
+ std::list<PacketPtr>::iterator iter;
for (iter=pf.begin(); iter != pf.end(); iter++) {
if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) {
return iter;
protected:
/** The Prefetch Queue. */
- std::list<Packet *> pf;
+ std::list<PacketPtr> pf;
// PARAMETERS
void setCache(BaseCache *_cache);
- void handleMiss(Packet * &pkt, Tick time);
+ void handleMiss(PacketPtr &pkt, Tick time);
- Packet * getPacket();
+ PacketPtr getPacket();
bool havePending()
{
return !pf.empty();
}
- virtual void calculatePrefetch(Packet * &pkt,
+ virtual void calculatePrefetch(PacketPtr &pkt,
std::list<Addr> &addresses,
std::list<Tick> &delays) = 0;
- virtual bool inCache(Packet * &pkt) = 0;
+ virtual bool inCache(PacketPtr &pkt) = 0;
virtual bool inMissQueue(Addr address) = 0;
- std::list<Packet *>::iterator inPrefetch(Addr address);
+ std::list<PacketPtr>::iterator inPrefetch(Addr address);
};
~GHBPrefetcher() {}
- void calculatePrefetch(Packet
* &pkt, std::list<Addr> &addresses,
+ void calculatePrefetch(Packet
Ptr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
~StridePrefetcher() {}
- void calculatePrefetch(Packet
* &pkt, std::list<Addr> &addresses,
+ void calculatePrefetch(Packet
Ptr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
~TaggedPrefetcher() {}
- void calculatePrefetch(Packet
* &pkt, std::list<Addr> &addresses,
+ void calculatePrefetch(Packet
Ptr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays);
};
template <class TagStore, class Buffering>
void
TaggedPrefetcher<TagStore, Buffering>::
-calculatePrefetch(Packet
* &pkt, std::list<Addr> &addresses,
+calculatePrefetch(Packet
Ptr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
}
FALRUBlk*
-FALRU::findBlock(Packet * &pkt, int &lat, int *inCache)
+FALRU::findBlock(PacketPtr &pkt, int &lat, int *inCache)
{
Addr addr = pkt->getAddr();
}
FALRUBlk*
-FALRU::findReplacement(Packet * &pkt, PacketList &writebacks,
+FALRU::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
FALRUBlk * blk = tail;
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
*/
- FALRUBlk* findBlock(Packet * &pkt, int &lat, int *inCache = 0);
+ FALRUBlk* findBlock(PacketPtr &pkt, int &lat, int *inCache = 0);
/**
* Find the block in the cache, do not update the replacement data.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
- FALRUBlk* findReplacement(Packet * &pkt, PacketList & writebacks,
+ FALRUBlk* findReplacement(PacketPtr &pkt, PacketList & writebacks,
BlkList &compress_blocks);
/**
}
IICTag*
-IIC::findBlock(Packet * &pkt, int &lat)
+IIC::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
IICTag*
-IIC::findReplacement(Packet * &pkt, PacketList &writebacks,
+IIC::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
DPRINTF(IIC, "Finding Replacement for %x\n", pkt->getAddr());
tag_ptr->refCount = 0;
if (tag_ptr->isModified()) {
-/* Packet * writeback =
+/* PacketPtr writeback =
buildWritebackReq(regenerateBlkAddr(tag_ptr->tag, 0),
tag_ptr->req->asid, tag_ptr->xc, blkSize,
tag_ptr->data,
*/
Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
blkSize, 0);
- Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
+ PacketPtr writeback = new Packet(writebackReq, Packet::Writeback, -1);
writeback->allocate();
memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize);
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
- IICTag* findBlock(Packet * &pkt, int &lat);
+ IICTag* findBlock(PacketPtr &pkt, int &lat);
/**
* Find the block, do not update the replacement data.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
- IICTag* findReplacement(Packet * &pkt, PacketList &writebacks,
+ IICTag* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
/**
}
LRUBlk*
-LRU::findBlock(Packet * &pkt, int &lat)
+LRU::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
}
LRUBlk*
-LRU::findReplacement(Packet * &pkt, PacketList &writebacks,
+LRU::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
unsigned set = extractSet(pkt->getAddr());
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
- LRUBlk* findBlock(Packet * &pkt, int &lat);
+ LRUBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache and update replacement data.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
- LRUBlk* findReplacement(Packet * &pkt, PacketList &writebacks,
+ LRUBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
/**
}
SplitBlk*
-Split::findBlock(Packet * &pkt, int &lat)
+Split::findBlock(PacketPtr &pkt, int &lat)
{
Addr aligned = blkAlign(pkt->getAddr());
}
SplitBlk*
-Split::findReplacement(Packet * &pkt, PacketList &writebacks,
+Split::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
SplitBlk *blk;
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
- SplitBlk* findBlock(Packet * &pkt, int &lat);
+ SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
- SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks,
+ SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
}
SplitBlk*
-SplitLIFO::findBlock(Packet * &pkt, int &lat)
+SplitLIFO::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
}
SplitBlk*
-SplitLIFO::findReplacement(Packet * &pkt, PacketList &writebacks,
+SplitLIFO::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
unsigned set = extractSet(pkt->getAddr());
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
- SplitBlk* findBlock(Packet * &pkt, int &lat);
+ SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
- SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks,
+ SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
/**
}
SplitBlk*
-SplitLRU::findBlock(Packet * &pkt, int &lat)
+SplitLRU::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
}
SplitBlk*
-SplitLRU::findReplacement(Packet * &pkt, PacketList &writebacks,
+SplitLRU::findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks)
{
unsigned set = extractSet(pkt->getAddr());
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
- SplitBlk* findBlock(Packet * &pkt, int &lat);
+ SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
*/
- SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks,
+ SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
BlkList &compress_blocks);
/**
static char *mem_access_output=NULL;
/* latency of access [CPU cycles]*/
Tick
-DRAMMemory::calculateLatency(Packet *pkt)
+DRAMMemory::calculateLatency(PacketPtr pkt)
{
bool cmdIsRead = pkt->isRead();
protected:
- Tick calculateLatency(Packet *pkt);
+ Tick calculateLatency(PacketPtr pkt);
int prechargeBanksAround(int bank);
public:
/** Do the packet modify the same addresses. */
bool
-Packet::intersect(Packet *p)
+Packet::intersect(PacketPtr p)
{
Addr s1 = getAddr();
Addr e1 = getAddr() + getSize() - 1;
}
bool
-fixPacket(Packet *func, Packet *timing)
+fixPacket(PacketPtr func, PacketPtr timing)
{
Addr funcStart = func->getAddr();
Addr funcEnd = func->getAddr() + func->getSize() - 1;
#include "sim/root.hh"
struct Packet;
-typedef Packet* PacketPtr;
+typedef Packet *PacketPtr;
typedef uint8_t* PacketDataPtr;
typedef std::list<PacketPtr> PacketList;
/** Device address (e.g., bus ID) of the source of the
* transaction. The source is not responsible for setting this
* field; it is set implicitly by the interconnect when the
- * packet * is first sent. */
+ * packet is first sent. */
short src;
/** Device address (e.g., bus ID) of the destination of the
void allocate();
/** Do the packet modify the same addresses. */
- bool intersect(Packet *p);
+ bool intersect(PacketPtr p);
};
* in the timing packet. It returns if the functional packet should continue to
* traverse the memory hierarchy or not.
*/
-bool fixPacket(Packet *func, Packet *timing);
+bool fixPacket(PacketPtr func, PacketPtr timing);
std::ostream & operator<<(std::ostream &o, const Packet &p);
}
Tick
-PhysicalMemory::calculateLatency(Packet *pkt)
+PhysicalMemory::calculateLatency(PacketPtr pkt)
{
return lat;
}
}
void
-PhysicalMemory::doFunctionalAccess(Packet *pkt)
+PhysicalMemory::doFunctionalAccess(PacketPtr pkt)
{
assert(pkt->getAddr() + pkt->getSize() <= params()->addrRange.size());
}
Tick
-PhysicalMemory::MemoryPort::recvAtomic(Packet *pkt)
+PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt)
{
memory->doFunctionalAccess(pkt);
return memory->calculateLatency(pkt);
}
void
-PhysicalMemory::MemoryPort::recvFunctional(Packet *pkt)
+PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt)
{
// Default implementation of SimpleTimingPort::recvFunctional()
// calls recvAtomic() and throws away the latency; we can save a
protected:
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
unsigned int drain(Event *de);
protected:
- void doFunctionalAccess(Packet *pkt);
- virtual Tick calculateLatency(Packet *pkt);
+ void doFunctionalAccess(PacketPtr pkt);
+ virtual Tick calculateLatency(PacketPtr pkt);
void recvStatusChange(Port::Status status);
public:
* called by a peer port, never directly by any outside object. */
/** Called to recive a timing call from the peer port. */
- virtual bool recvTiming(Packet *pkt) = 0;
+ virtual bool recvTiming(PacketPtr pkt) = 0;
/** Called to recive a atomic call from the peer port. */
- virtual Tick recvAtomic(Packet *pkt) = 0;
+ virtual Tick recvAtomic(PacketPtr pkt) = 0;
/** Called to recive a functional call from the peer port. */
- virtual void recvFunctional(Packet *pkt) = 0;
+ virtual void recvFunctional(PacketPtr pkt) = 0;
/** Called to recieve a status change from the peer port. */
virtual void recvStatusChange(Status status) = 0;
case a cache has a higher priority request come in while waiting for
the bus to arbitrate.
*/
- bool sendTiming(Packet *pkt) { return peer->recvTiming(pkt); }
+ bool sendTiming(PacketPtr pkt) { return peer->recvTiming(pkt); }
/** Function called by the associated device to send an atomic
* access, an access in which the data is moved and the state is
* updated in one cycle, without interleaving with other memory
* accesses. Returns estimated latency of access.
*/
- Tick sendAtomic(Packet *pkt)
+ Tick sendAtomic(PacketPtr pkt)
{ return peer->recvAtomic(pkt); }
/** Function called by the associated device to send a functional access,
memory system, without affecting the current state of any block or
moving the block.
*/
- void sendFunctional(Packet *pkt)
+ void sendFunctional(PacketPtr pkt)
{ return peer->recvFunctional(pkt); }
/** Called by the associated device to send a status change to the device
{}
protected:
- virtual bool recvTiming(Packet *pkt) { panic("FuncPort is UniDir"); }
- virtual Tick recvAtomic(Packet *pkt) { panic("FuncPort is UniDir"); }
- virtual void recvFunctional(Packet *pkt) { panic("FuncPort is UniDir"); }
+ virtual bool recvTiming(PacketPtr pkt) { panic("FuncPort is UniDir"); }
+ virtual Tick recvAtomic(PacketPtr pkt) { panic("FuncPort is UniDir"); }
+ virtual void recvFunctional(PacketPtr pkt) { panic("FuncPort is UniDir"); }
virtual void recvStatusChange(Status status) {}
public:
#include "mem/tport.hh"
void
-SimpleTimingPort::recvFunctional(Packet *pkt)
+SimpleTimingPort::recvFunctional(PacketPtr pkt)
{
//First check queued events
- std::list<Packet *>::iterator i = transmitList.begin();
- std::list<Packet *>::iterator end = transmitList.end();
+ std::list<PacketPtr>::iterator i = transmitList.begin();
+ std::list<PacketPtr>::iterator end = transmitList.end();
bool cont = true;
while (i != end && cont) {
- Packet * target = *i;
+ PacketPtr target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
if (target->intersect(pkt))
}
bool
-SimpleTimingPort::recvTiming(Packet *pkt)
+SimpleTimingPort::recvTiming(PacketPtr pkt)
{
// If the device is only a slave, it should only be sending
// responses, which should never get nacked. There used to be
protected:
/** A list of outgoing timing response packets that haven't been
* serviced yet. */
- std::list<Packet*> transmitList;
+ std::list<PacketPtr> transmitList;
/**
* This class is used to implemented sendTiming() with a delay. When
class SendEvent : public Event
{
SimpleTimingPort *port;
- Packet *packet;
+ PacketPtr packet;
public:
- SendEvent(SimpleTimingPort *p, Packet *pkt, Tick t)
+ SendEvent(SimpleTimingPort *p, PacketPtr pkt, Tick t)
: Event(&mainEventQueue), port(p), packet(pkt)
{ setFlags(AutoDelete); schedule(curTick + t); }
Event *drainEvent;
/** Schedule a sendTiming() event to be called in the future. */
- void sendTimingLater(Packet *pkt, Tick time)
+ void sendTimingLater(PacketPtr pkt, Tick time)
{ outTiming++; new SendEvent(this, pkt, time); }
/** This function is notification that the device should attempt to send a
virtual void recvRetry();
/** Implemented using recvAtomic(). */
- void recvFunctional(Packet *pkt);
+ void recvFunctional(PacketPtr pkt);
/** Implemented using recvAtomic(). */
- bool recvTiming(Packet *pkt);
+ bool recvTiming(PacketPtr pkt);
/**
* Simple ports generally don't care about any status
projects / gem5.git / commitdiff