an independent 32-bit Defined Word. The only semi-exceptions are
the Post-Increment Mode of LD/ST-Update and Vectorised Branch-Conditional.*
+Note a special application of the above paragraph: due to the fact that
+the Prefix Encodings are independent, **by definition** two new Sandbox
+areas "come into being" in an **inviolate** manner (i.e. they may not
+be called anything else, nor may they be revoked rescinded removed or
+recalled), named `SVP64:EXT022` and `SVP64Single:EXT022`. The **only
+way** that these two new areas may be revoked is if EXT022 itself
+is revoked. **All and any** re-definitions modifications enhancements
+clarifications that apply to EXT022 **also apply to these two new areas**
+because due to the Prefixes being independent Defined Words the three
+areas are actually one and the same area.
+
Encoding spaces and their potential are illustrated:
| Encoding |Available bits|Scalar|Vectoriseable | SVP64Single |PO1-Prefixable |
as EXT1xx). New Primary Opcode areas EXT232-263 allows for immediate growth,
allowing Power ISA to catch up 12-15 years on Intel and ARM. Also the
Simple-V RISC-paradigm "Loop" subsystem based on x86 REP and Zilog Z80
-CPIR and LDIR may be cleanly and smoothly introduced.
+CPIR and LDIR may be cleanly and smoothly introduced. Also several new
+areas are RESERVED which allows significant future expansion.
**Changes**