csr_map = {}
interrupt_map = {}
mem_map = {
- "rom": 0x00000000, # (default shadow @0x80000000)
- "sram": 0x01000000, # (default shadow @0x81000000)
- "csr": 0x02000000, # (default shadow @0x82000000)
- "main_ram": 0x40000000, # (default shadow @0xc0000000)
+ "rom": 0x00000000,
+ "sram": 0x01000000,
+ "main_ram": 0x40000000,
+ "csr": 0x82000000,
}
+ io_regions = {}
+
def __init__(self, platform, clk_freq,
# CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
- # MEM MAP parameters
- shadow_base=0x80000000,
# ROM parameters
integrated_rom_size=0, integrated_rom_init=[],
# SRAM parameters
# Controller parameters
with_ctrl=True,
# Wishbone parameters
- with_wishbone=True, wishbone_timeout_cycles=1e6):
+ with_wishbone=True, wishbone_timeout_cycles=1e6,
+ **kwargs):
self.platform = platform
self.clk_freq = clk_freq
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
+ self.soc_io_regions = self.io_regions
# SoC's Config/Constants/Regions
self.config = {}
# CSR masters list
self._csr_masters = []
+ self.add_retro_compat(kwargs)
+
# Parameters managment ---------------------------------------------------------------------
if cpu_type == "None":
cpu_type = None
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
- self.shadow_base = shadow_base
- self.config["SHADOW_BASE"] = shadow_base
-
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
# Update Memory Map (if defined by CPU)
self.soc_mem_map.update(self.cpu.mem_map)
+ # Update IO Regions (if defined by CPU)
+ self.soc_io_regions.update(self.cpu.io_regions)
+
# Set reset address
self.cpu.set_reset_address(self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address)
self.config["CPU_RESET_ADDR"] = self.cpu.reset_address
raise FinalizeError
self._csr_masters.append(csrm)
- def add_memory_region(self, name, origin, length):
+ def check_io_region(self, name, origin, length):
+ for region_origin, region_length in self.soc_io_regions.items():
+ if (origin >= region_origin) & ((origin + length) < (region_origin + region_length)):
+ return
+ msg = "{} region: 0x{:08x}-0x{:x} not located in an IO region.\n".format(
+ name, origin, origin + length - 1)
+ msg += "Avalaible IO regions:\n"
+ for region_origin, region_length in self.soc_io_regions.items():
+ msg += "- 0x{:08x}-0x{:x}\n".format(region_origin, region_origin + region_length - 1)
+ raise ValueError(msg)
+
+ def add_memory_region(self, name, origin, length, io_region=False):
+ if io_region:
+ self.check_io_region(name, origin, length)
def in_this_region(addr):
return addr >= origin and addr < origin + length
for n, r in self.mem_regions.items():
raise ValueError("CSR region conflict between {} and {}".format(n, name))
def add_csr_region(self, name, origin, busword, obj):
+ self.check_io_region(name, origin, 0x800)
self.check_csr_region(name, origin)
self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
# Check and add CSRs regions
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.check_csr_range(name, 0x800*mapaddr)
- self.add_csr_region(name, (self.soc_mem_map["csr"] + 0x800*mapaddr) | self.shadow_base,
+ self.add_csr_region(name, (self.soc_mem_map["csr"] + 0x800*mapaddr),
self.csr_data_width, csrs)
# Check and add Memory regions
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.check_csr_range(name, 0x800*mapaddr)
self.add_csr_region(name + "_" + memory.name_override,
- (self.soc_mem_map["csr"] + 0x800*mapaddr) | self.shadow_base,
+ (self.soc_mem_map["csr"] + 0x800*mapaddr),
self.csr_data_width, memory)
# Add CSRs / Config items to constants
self.comb += self.cpu.interrupt[_id].eq(module.ev.irq)
self.constants[_name.upper() + "_INTERRUPT"] = _id
+
+ # API retro-compatibility layer ----------------------------------------------------------------
+ # Allow user to build the design the old API for ~3 months after the API change is introduced.
+ # Adds warning and artificical delay to encourage user to update.
+
+ def add_retro_compat(self, kwargs):
+ # 2019-10-09 : deprecate shadow_base, introduce io_regions
+ if "shadow_base" in kwargs.keys():
+ deprecated_warning(": shadow_base replaced by IO regions.")
+ self.retro_compat_shadow_base = kwargs.get("shadow_base", 0x80000000)
+ self.config["SHADOW_BASE"] = self.retro_compat_shadow_base
+
+ def __getattr__(self, name):
+ # 2019-10-09: deprecate shadow_base, introduce io_regions
+ if name == "shadow_base":
+ deprecated_warning(": shadow_base replaced by IO regions.")
+ return self.retro_compat_shadow_base
+ else:
+ return Module.__getattr__(self, name)
+
# SoCCore arguments --------------------------------------------------------------------------------
def soc_core_args(parser):
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