Extend test with renaming cells with prefix too

diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index ee5c6bc7e1eba6b27ee387bc01941db3a007ce59..c2f42d50b197a803c9175eb5051ae9f16095c551 100644 (file)
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -2,6 +2,7 @@ read_verilog <<EOT
 module sub(input i, output o, input j);
 foobar _TECHMAP_REPLACE_(i, o, j);
 wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
 endmodule
 EOT
 design -stash techmap
@@ -14,3 +15,4 @@ EOT
 
 techmap -map %techmap
 select -assert-any w:s0.asdf
+select -assert-any c:s0.blah