split out instructions from openpower/isa/fptrans.mdwn

diff --git a/openpower/isa/fptrans.mdwn b/openpower/isa/fptrans.mdwn
index 9060c79f304455be23f12f62abc74cb9974d9277..78e76b417a9460f4c730cb1cd862767391a8a5e0 100644 (file)
--- a/openpower/isa/fptrans.mdwn
+++ b/openpower/isa/fptrans.mdwn
@@ -2,1585 +2,172 @@
 
 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
 
-# [DRAFT] Floating ATAN2 Single
+[[!inline pagenames="openpower/isa/fptrans/fatan2s" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/fatan2" raw="yes"]]
 
-* fatan2s FRT,FRA,FRB (Rc=0)
-* fatan2s. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fatan2pis" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/fatan2pi" raw="yes"]]
 
-    FRT <- DOUBLE(bfp32_ATAN2(SINGLE(FRA), SINGLE(FRB)))
+[[!inline pagenames="openpower/isa/fptrans/fpows" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fpow" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fpowns" raw="yes"]]
 
-# [DRAFT] Floating ATAN2
+[[!inline pagenames="openpower/isa/fptrans/fpown" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/fpowrs" raw="yes"]]
 
-* fatan2 FRT,FRA,FRB (Rc=0)
-* fatan2. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fpowr" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/frootns" raw="yes"]]
 
-    FRT <- bfp64_ATAN2(FRA, FRB)
+[[!inline pagenames="openpower/isa/fptrans/frootn" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fhypots" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fhypot" raw="yes"]]
 
-# [DRAFT] Floating ATAN2PI Single
+[[!inline pagenames="openpower/isa/fptrans/frsqrts" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/frsqrt" raw="yes"]]
 
-* fatan2pis FRT,FRA,FRB (Rc=0)
-* fatan2pis. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fcbrts" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/fcbrt" raw="yes"]]
 
-    FRT <- DOUBLE(bfp32_ATAN2PI(SINGLE(FRA), SINGLE(FRB)))
+[[!inline pagenames="openpower/isa/fptrans/frecips" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/frecip" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fexp2m1s" raw="yes"]]
 
-# [DRAFT] Floating ATAN2PI
+[[!inline pagenames="openpower/isa/fptrans/fexp2m1" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/flog2p1s" raw="yes"]]
 
-* fatan2pi FRT,FRA,FRB (Rc=0)
-* fatan2pi. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/flog2p1" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/fexp2s" raw="yes"]]
 
-    FRT <- bfp64_ATAN2PI(FRA, FRB)
+[[!inline pagenames="openpower/isa/fptrans/fexp2" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/flog2s" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/flog2" raw="yes"]]
 
-# [DRAFT] Floating POW Single
+[[!inline pagenames="openpower/isa/fptrans/fexpm1s" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/fexpm1" raw="yes"]]
 
-* fpows FRT,FRA,FRB (Rc=0)
-* fpows. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/flogp1s" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/flogp1" raw="yes"]]
 
-    FRT <- DOUBLE(bfp32_POW(SINGLE(FRA), SINGLE(FRB)))
+[[!inline pagenames="openpower/isa/fptrans/fexps" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fexp" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/flogs" raw="yes"]]
 
-# [DRAFT] Floating POW
+[[!inline pagenames="openpower/isa/fptrans/flog" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/fexp10m1s" raw="yes"]]
 
-* fpow FRT,FRA,FRB (Rc=0)
-* fpow. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fexp10m1" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/flog10p1s" raw="yes"]]
 
-    FRT <- bfp64_POW(FRA, FRB)
+[[!inline pagenames="openpower/isa/fptrans/flog10p1" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fexp10s" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fexp10" raw="yes"]]
 
-# [DRAFT] Floating POWN Single
+[[!inline pagenames="openpower/isa/fptrans/flog10s" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/flog10" raw="yes"]]
 
-* fpowns FRT,FRA,RB (Rc=0)
-* fpowns. FRT,FRA,RB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fsins" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/fsin" raw="yes"]]
 
-    FRT <- DOUBLE(bfp32_POWN(SINGLE(FRA), RB))
+[[!inline pagenames="openpower/isa/fptrans/fcoss" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fcos" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/ftans" raw="yes"]]
 
-# [DRAFT] Floating POWN
+[[!inline pagenames="openpower/isa/fptrans/ftan" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/fasins" raw="yes"]]
 
-* fpown FRT,FRA,RB (Rc=0)
-* fpown. FRT,FRA,RB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fasin" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/facoss" raw="yes"]]
 
-    FRT <- bfp64_POWN(FRA, RB)
+[[!inline pagenames="openpower/isa/fptrans/facos" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fatans" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fatan" raw="yes"]]
 
-# [DRAFT] Floating POWR Single
+[[!inline pagenames="openpower/isa/fptrans/fsinpis" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/fsinpi" raw="yes"]]
 
-* fpowrs FRT,FRA,FRB (Rc=0)
-* fpowrs. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fcospis" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/fcospi" raw="yes"]]
 
-    FRT <- DOUBLE(bfp32_POWR(SINGLE(FRA), SINGLE(FRB)))
+[[!inline pagenames="openpower/isa/fptrans/ftanpis" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/ftanpi" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fasinpis" raw="yes"]]
 
-# [DRAFT] Floating POWR
+[[!inline pagenames="openpower/isa/fptrans/fasinpi" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/facospis" raw="yes"]]
 
-* fpowr FRT,FRA,FRB (Rc=0)
-* fpowr. FRT,FRA,FRB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/facospi" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/fatanpis" raw="yes"]]
 
-    FRT <- bfp64_POWR(FRA, FRB)
+[[!inline pagenames="openpower/isa/fptrans/fatanpi" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fsinhs" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fsinh" raw="yes"]]
 
-# [DRAFT] Floating ROOTN Single
+[[!inline pagenames="openpower/isa/fptrans/fcoshs" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/fcosh" raw="yes"]]
 
-* frootns FRT,FRA,RB (Rc=0)
-* frootns. FRT,FRA,RB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/ftanhs" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/ftanh" raw="yes"]]
 
-    FRT <- DOUBLE(bfp32_ROOTN(SINGLE(FRA), RB))
+[[!inline pagenames="openpower/isa/fptrans/fasinhs" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fasinh" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/facoshs" raw="yes"]]
 
-# [DRAFT] Floating ROOTN
+[[!inline pagenames="openpower/isa/fptrans/facosh" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fptrans/fatanhs" raw="yes"]]
 
-* frootn FRT,FRA,RB (Rc=0)
-* frootn. FRT,FRA,RB (Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fatanh" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fptrans/fminmax" raw="yes"]]
 
-    FRT <- bfp64_ROOTN(FRA, RB)
+[[!inline pagenames="openpower/isa/fptrans/fmods" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fptrans/fmod" raw="yes"]]
 
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating HYPOT Single
-
-X-Form
-
-* fhypots FRT,FRA,FRB (Rc=0)
-* fhypots. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_HYPOT(SINGLE(FRA), SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating HYPOT
-
-X-Form
-
-* fhypot FRT,FRA,FRB (Rc=0)
-* fhypot. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_HYPOT(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating RSQRT Single
-
-X-Form
-
-* frsqrts FRT,FRB (Rc=0)
-* frsqrts. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_RSQRT(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating RSQRT
-
-X-Form
-
-* frsqrt FRT,FRB (Rc=0)
-* frsqrt. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_RSQRT(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating CBRT Single
-
-X-Form
-
-* fcbrts FRT,FRB (Rc=0)
-* fcbrts. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_CBRT(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating CBRT
-
-X-Form
-
-* fcbrt FRT,FRB (Rc=0)
-* fcbrt. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_CBRT(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating RECIP Single
-
-X-Form
-
-* frecips FRT,FRB (Rc=0)
-* frecips. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_RECIP(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating RECIP
-
-X-Form
-
-* frecip FRT,FRB (Rc=0)
-* frecip. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_RECIP(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP2M1 Single
-
-X-Form
-
-* fexp2m1s FRT,FRB (Rc=0)
-* fexp2m1s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_EXP2M1(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP2M1
-
-X-Form
-
-* fexp2m1 FRT,FRB (Rc=0)
-* fexp2m1. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_EXP2M1(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG2P1 Single
-
-X-Form
-
-* flog2p1s FRT,FRB (Rc=0)
-* flog2p1s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_LOG2P1(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG2P1
-
-X-Form
-
-* flog2p1 FRT,FRB (Rc=0)
-* flog2p1. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_LOG2P1(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP2 Single
-
-X-Form
-
-* fexp2s FRT,FRB (Rc=0)
-* fexp2s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_EXP2(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP2
-
-X-Form
-
-* fexp2 FRT,FRB (Rc=0)
-* fexp2. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_EXP2(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG2 Single
-
-X-Form
-
-* flog2s FRT,FRB (Rc=0)
-* flog2s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_LOG2(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG2
-
-X-Form
-
-* flog2 FRT,FRB (Rc=0)
-* flog2. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_LOG2(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXPM1 Single
-
-X-Form
-
-* fexpm1s FRT,FRB (Rc=0)
-* fexpm1s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_EXPM1(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXPM1
-
-X-Form
-
-* fexpm1 FRT,FRB (Rc=0)
-* fexpm1. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_EXPM1(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOGP1 Single
-
-X-Form
-
-* flogp1s FRT,FRB (Rc=0)
-* flogp1s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_LOGP1(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOGP1
-
-X-Form
-
-* flogp1 FRT,FRB (Rc=0)
-* flogp1. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_LOGP1(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP Single
-
-X-Form
-
-* fexps FRT,FRB (Rc=0)
-* fexps. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_EXP(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP
-
-X-Form
-
-* fexp FRT,FRB (Rc=0)
-* fexp. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_EXP(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG Single
-
-X-Form
-
-* flogs FRT,FRB (Rc=0)
-* flogs. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_LOG(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG
-
-X-Form
-
-* flog FRT,FRB (Rc=0)
-* flog. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_LOG(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP10M1 Single
-
-X-Form
-
-* fexp10m1s FRT,FRB (Rc=0)
-* fexp10m1s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_EXP10M1(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP10M1
-
-X-Form
-
-* fexp10m1 FRT,FRB (Rc=0)
-* fexp10m1. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_EXP10M1(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG10P1 Single
-
-X-Form
-
-* flog10p1s FRT,FRB (Rc=0)
-* flog10p1s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_LOG10P1(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG10P1
-
-X-Form
-
-* flog10p1 FRT,FRB (Rc=0)
-* flog10p1. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_LOG10P1(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP10 Single
-
-X-Form
-
-* fexp10s FRT,FRB (Rc=0)
-* fexp10s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_EXP10(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating EXP10
-
-X-Form
-
-* fexp10 FRT,FRB (Rc=0)
-* fexp10. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_EXP10(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG10 Single
-
-X-Form
-
-* flog10s FRT,FRB (Rc=0)
-* flog10s. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_LOG10(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating LOG10
-
-X-Form
-
-* flog10 FRT,FRB (Rc=0)
-* flog10. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_LOG10(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating SIN Single
-
-X-Form
-
-* fsins FRT,FRB (Rc=0)
-* fsins. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_SIN(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating SIN
-
-X-Form
-
-* fsin FRT,FRB (Rc=0)
-* fsin. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_SIN(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating COS Single
-
-X-Form
-
-* fcoss FRT,FRB (Rc=0)
-* fcoss. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_COS(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating COS
-
-X-Form
-
-* fcos FRT,FRB (Rc=0)
-* fcos. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_COS(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating TAN Single
-
-X-Form
-
-* ftans FRT,FRB (Rc=0)
-* ftans. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_TAN(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating TAN
-
-X-Form
-
-* ftan FRT,FRB (Rc=0)
-* ftan. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_TAN(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ASIN Single
-
-X-Form
-
-* fasins FRT,FRB (Rc=0)
-* fasins. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ASIN(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ASIN
-
-X-Form
-
-* fasin FRT,FRB (Rc=0)
-* fasin. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ASIN(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ACOS Single
-
-X-Form
-
-* facoss FRT,FRB (Rc=0)
-* facoss. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ACOS(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ACOS
-
-X-Form
-
-* facos FRT,FRB (Rc=0)
-* facos. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ACOS(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ATAN Single
-
-X-Form
-
-* fatans FRT,FRB (Rc=0)
-* fatans. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ATAN(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ATAN
-
-X-Form
-
-* fatan FRT,FRB (Rc=0)
-* fatan. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ATAN(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating SINPI Single
-
-X-Form
-
-* fsinpis FRT,FRB (Rc=0)
-* fsinpis. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_SINPI(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating SINPI
-
-X-Form
-
-* fsinpi FRT,FRB (Rc=0)
-* fsinpi. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_SINPI(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating COSPI Single
-
-X-Form
-
-* fcospis FRT,FRB (Rc=0)
-* fcospis. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_COSPI(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating COSPI
-
-X-Form
-
-* fcospi FRT,FRB (Rc=0)
-* fcospi. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_COSPI(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating TANPI Single
-
-X-Form
-
-* ftanpis FRT,FRB (Rc=0)
-* ftanpis. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_TANPI(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating TANPI
-
-X-Form
-
-* ftanpi FRT,FRB (Rc=0)
-* ftanpi. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_TANPI(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ASINPI Single
-
-X-Form
-
-* fasinpis FRT,FRB (Rc=0)
-* fasinpis. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ASINPI(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ASINPI
-
-X-Form
-
-* fasinpi FRT,FRB (Rc=0)
-* fasinpi. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ASINPI(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ACOSPI Single
-
-X-Form
-
-* facospis FRT,FRB (Rc=0)
-* facospis. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ACOSPI(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ACOSPI
-
-X-Form
-
-* facospi FRT,FRB (Rc=0)
-* facospi. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ACOSPI(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ATANPI Single
-
-X-Form
-
-* fatanpis FRT,FRB (Rc=0)
-* fatanpis. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ATANPI(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ATANPI
-
-X-Form
-
-* fatanpi FRT,FRB (Rc=0)
-* fatanpi. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ATANPI(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating SINH Single
-
-X-Form
-
-* fsinhs FRT,FRB (Rc=0)
-* fsinhs. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_SINH(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating SINH
-
-X-Form
-
-* fsinh FRT,FRB (Rc=0)
-* fsinh. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_SINH(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating COSH Single
-
-X-Form
-
-* fcoshs FRT,FRB (Rc=0)
-* fcoshs. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_COSH(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating COSH
-
-X-Form
-
-* fcosh FRT,FRB (Rc=0)
-* fcosh. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_COSH(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating TANH Single
-
-X-Form
-
-* ftanhs FRT,FRB (Rc=0)
-* ftanhs. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_TANH(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating TANH
-
-X-Form
-
-* ftanh FRT,FRB (Rc=0)
-* ftanh. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_TANH(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ASINH Single
-
-X-Form
-
-* fasinhs FRT,FRB (Rc=0)
-* fasinhs. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ASINH(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ASINH
-
-X-Form
-
-* fasinh FRT,FRB (Rc=0)
-* fasinh. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ASINH(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ACOSH Single
-
-X-Form
-
-* facoshs FRT,FRB (Rc=0)
-* facoshs. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ACOSH(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ACOSH
-
-X-Form
-
-* facosh FRT,FRB (Rc=0)
-* facosh. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ACOSH(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ATANH Single
-
-X-Form
-
-* fatanhs FRT,FRB (Rc=0)
-* fatanhs. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_ATANH(SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating ATANH
-
-X-Form
-
-* fatanh FRT,FRB (Rc=0)
-* fatanh. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_ATANH(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating Minimum/Maximum
-
-MM-Form
-
-* fminmax FRT,FRA,FRB,FMM (Rc=0)
-* fminmax. FRT,FRA,FRB,FMM (Rc=1)
-
-Pseudo-code:
-
-    result <- [0] * 64
-    a <- (FRA)
-    b <- (FRB)
-    abs_a <- 0b0 || a[1:63]
-    abs_b <- 0b0 || b[1:63]
-    a_is_nan <- abs_a >u 0x7FF0_0000_0000_0000
-    a_is_snan <- a_is_nan & (a[12] = 0)
-    b_is_nan <- abs_b >u 0x7FF0_0000_0000_0000
-    b_is_snan <- b_is_nan & (b[12] = 0)
-    any_snan <- a_is_snan | b_is_snan
-    a_quieted <- a
-    a_quieted[12] <- 1
-    b_quieted <- b
-    b_quieted[12] <- 1
-    if a_is_nan | b_is_nan then
-        if FMM[2:3] = 0b00 then  # min/maxnum08
-            if a_is_snan then result <- a_quieted
-            else if b_is_snan then result <- b_quieted
-            else if a_is_nan & b_is_nan then result <- a_quieted
-            else if a_is_nan then result <- b
-            else result <- a
-        if FMM[2:3] = 0b01 then  # min/max19
-            if a_is_nan then result <- a_quieted
-            else result <- b_quieted
-        if FMM[2:3] = 0b10 then  # min/maxnum19
-            if a_is_nan & b_is_nan then result <- a_quieted
-            else if a_is_nan then result <- b
-            else result <- a
-        if FMM[2:3] = 0b11 then  # min/maxc
-            result <- b
-    else
-        cmp_l <- a
-        cmp_r <- b
-        if FMM[1] then  # min/maxmag
-            if abs_a != abs_b then
-                cmp_l <- abs_a
-                cmp_r <- abs_b
-        if FMM[2:3] = 0b11 then  # min/maxc
-            if abs_a = 0 then cmp_l[0:63] <- 0
-            if abs_b = 0 then cmp_r[0:63] <- 0
-        if FMM[0] then  # max
-            # swap cmp_* so comparison goes the other way
-            cmp_l, cmp_r <- cmp_r, cmp_l
-        if cmp_l[0] = 1 then
-            if cmp_r[0] = 0 then result <- a
-            else if cmp_l >u cmp_r then
-                # IEEE 754 is sign-magnitude,
-                # so bigger magnitude negative is smaller
-                result <- a
-            else result <- b
-        else if cmp_r[0] = 1 then result <- b
-        else if cmp_l <u cmp_r then result <- a
-        else result <- b
-    if any_snan then SetFX(FPSCR.VXSNAN)
-    if (FPSCR.VE = 0) | ¬any_snan then (FRT) <- result
-
-Special Registers Altered:
-
-    FX VXSNAN
-    CR1     (if Rc=1)
-
-# [DRAFT] Floating MOD Single
-
-X-Form
-
-* fmods FRT,FRA,FRB (Rc=0)
-* fmods. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_MOD(SINGLE(FRA), SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating MOD
-
-X-Form
-
-* fmod FRT,FRA,FRB (Rc=0)
-* fmod. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_MOD(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating REMAINDER Single
-
-X-Form
-
-* fremainders FRT,FRA,FRB (Rc=0)
-* fremainders. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- DOUBLE(bfp32_REMAINDER(SINGLE(FRA), SINGLE(FRB)))
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# [DRAFT] Floating REMAINDER
-
-X-Form
-
-* fremainder FRT,FRA,FRB (Rc=0)
-* fremainder. FRT,FRA,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- bfp64_REMAINDER(FRA, FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
+[[!inline pagenames="openpower/isa/fptrans/fremainders" raw="yes"]]
 
+[[!inline pagenames="openpower/isa/fptrans/fremainder" raw="yes"]]

diff --git a/openpower/isa/fptrans/facos.mdwn b/openpower/isa/fptrans/facos.mdwn
new file mode 100644 (file)
index 0000000..a6db319
--- /dev/null
+++ b/openpower/isa/fptrans/facos.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ACOS
+
+X-Form
+
+* facos FRT,FRB (Rc=0)
+* facos. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/facos_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/facos_code.mdwn b/openpower/isa/fptrans/facos_code.mdwn
new file mode 100644 (file)
index 0000000..78e8ff4
--- /dev/null
+++ b/openpower/isa/fptrans/facos_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ACOS(FRB)

diff --git a/openpower/isa/fptrans/facosh.mdwn b/openpower/isa/fptrans/facosh.mdwn
new file mode 100644 (file)
index 0000000..a1c1ec8
--- /dev/null
+++ b/openpower/isa/fptrans/facosh.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ACOSH
+
+X-Form
+
+* facosh FRT,FRB (Rc=0)
+* facosh. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/facosh_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/facosh_code.mdwn b/openpower/isa/fptrans/facosh_code.mdwn
new file mode 100644 (file)
index 0000000..139ff8c
--- /dev/null
+++ b/openpower/isa/fptrans/facosh_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ACOSH(FRB)

diff --git a/openpower/isa/fptrans/facoshs.mdwn b/openpower/isa/fptrans/facoshs.mdwn
new file mode 100644 (file)
index 0000000..762ed2f
--- /dev/null
+++ b/openpower/isa/fptrans/facoshs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ACOSH Single
+
+X-Form
+
+* facoshs FRT,FRB (Rc=0)
+* facoshs. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/facoshs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/facoshs_code.mdwn b/openpower/isa/fptrans/facoshs_code.mdwn
new file mode 100644 (file)
index 0000000..0401434
--- /dev/null
+++ b/openpower/isa/fptrans/facoshs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ACOSH(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/facospi.mdwn b/openpower/isa/fptrans/facospi.mdwn
new file mode 100644 (file)
index 0000000..36c2ea2
--- /dev/null
+++ b/openpower/isa/fptrans/facospi.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ACOSPI
+
+X-Form
+
+* facospi FRT,FRB (Rc=0)
+* facospi. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/facospi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/facospi_code.mdwn b/openpower/isa/fptrans/facospi_code.mdwn
new file mode 100644 (file)
index 0000000..abc028c
--- /dev/null
+++ b/openpower/isa/fptrans/facospi_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ACOSPI(FRB)

diff --git a/openpower/isa/fptrans/facospis.mdwn b/openpower/isa/fptrans/facospis.mdwn
new file mode 100644 (file)
index 0000000..bd42a13
--- /dev/null
+++ b/openpower/isa/fptrans/facospis.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ACOSPI Single
+
+X-Form
+
+* facospis FRT,FRB (Rc=0)
+* facospis. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/facospis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/facospis_code.mdwn b/openpower/isa/fptrans/facospis_code.mdwn
new file mode 100644 (file)
index 0000000..f421dcf
--- /dev/null
+++ b/openpower/isa/fptrans/facospis_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ACOSPI(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/facoss.mdwn b/openpower/isa/fptrans/facoss.mdwn
new file mode 100644 (file)
index 0000000..d4ca916
--- /dev/null
+++ b/openpower/isa/fptrans/facoss.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ACOS Single
+
+X-Form
+
+* facoss FRT,FRB (Rc=0)
+* facoss. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/facoss_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/facoss_code.mdwn b/openpower/isa/fptrans/facoss_code.mdwn
new file mode 100644 (file)
index 0000000..f2966d3
--- /dev/null
+++ b/openpower/isa/fptrans/facoss_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ACOS(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fasin.mdwn b/openpower/isa/fptrans/fasin.mdwn
new file mode 100644 (file)
index 0000000..ee8d557
--- /dev/null
+++ b/openpower/isa/fptrans/fasin.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ASIN
+
+X-Form
+
+* fasin FRT,FRB (Rc=0)
+* fasin. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fasin_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fasin_code.mdwn b/openpower/isa/fptrans/fasin_code.mdwn
new file mode 100644 (file)
index 0000000..64444ff
--- /dev/null
+++ b/openpower/isa/fptrans/fasin_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ASIN(FRB)

diff --git a/openpower/isa/fptrans/fasinh.mdwn b/openpower/isa/fptrans/fasinh.mdwn
new file mode 100644 (file)
index 0000000..a8a23b6
--- /dev/null
+++ b/openpower/isa/fptrans/fasinh.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ASINH
+
+X-Form
+
+* fasinh FRT,FRB (Rc=0)
+* fasinh. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fasinh_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fasinh_code.mdwn b/openpower/isa/fptrans/fasinh_code.mdwn
new file mode 100644 (file)
index 0000000..d6237da
--- /dev/null
+++ b/openpower/isa/fptrans/fasinh_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ASINH(FRB)

diff --git a/openpower/isa/fptrans/fasinhs.mdwn b/openpower/isa/fptrans/fasinhs.mdwn
new file mode 100644 (file)
index 0000000..98d432a
--- /dev/null
+++ b/openpower/isa/fptrans/fasinhs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ASINH Single
+
+X-Form
+
+* fasinhs FRT,FRB (Rc=0)
+* fasinhs. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fasinhs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fasinhs_code.mdwn b/openpower/isa/fptrans/fasinhs_code.mdwn
new file mode 100644 (file)
index 0000000..988e8fc
--- /dev/null
+++ b/openpower/isa/fptrans/fasinhs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ASINH(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fasinpi.mdwn b/openpower/isa/fptrans/fasinpi.mdwn
new file mode 100644 (file)
index 0000000..ab100bb
--- /dev/null
+++ b/openpower/isa/fptrans/fasinpi.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ASINPI
+
+X-Form
+
+* fasinpi FRT,FRB (Rc=0)
+* fasinpi. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fasinpi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fasinpi_code.mdwn b/openpower/isa/fptrans/fasinpi_code.mdwn
new file mode 100644 (file)
index 0000000..710f09e
--- /dev/null
+++ b/openpower/isa/fptrans/fasinpi_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ASINPI(FRB)

diff --git a/openpower/isa/fptrans/fasinpis.mdwn b/openpower/isa/fptrans/fasinpis.mdwn
new file mode 100644 (file)
index 0000000..cab8013
--- /dev/null
+++ b/openpower/isa/fptrans/fasinpis.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ASINPI Single
+
+X-Form
+
+* fasinpis FRT,FRB (Rc=0)
+* fasinpis. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fasinpis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fasinpis_code.mdwn b/openpower/isa/fptrans/fasinpis_code.mdwn
new file mode 100644 (file)
index 0000000..270a634
--- /dev/null
+++ b/openpower/isa/fptrans/fasinpis_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ASINPI(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fasins.mdwn b/openpower/isa/fptrans/fasins.mdwn
new file mode 100644 (file)
index 0000000..590f110
--- /dev/null
+++ b/openpower/isa/fptrans/fasins.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ASIN Single
+
+X-Form
+
+* fasins FRT,FRB (Rc=0)
+* fasins. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fasins_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fasins_code.mdwn b/openpower/isa/fptrans/fasins_code.mdwn
new file mode 100644 (file)
index 0000000..518b84f
--- /dev/null
+++ b/openpower/isa/fptrans/fasins_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ASIN(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fatan.mdwn b/openpower/isa/fptrans/fatan.mdwn
new file mode 100644 (file)
index 0000000..aea917a
--- /dev/null
+++ b/openpower/isa/fptrans/fatan.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATAN
+
+X-Form
+
+* fatan FRT,FRB (Rc=0)
+* fatan. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatan_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatan2.mdwn b/openpower/isa/fptrans/fatan2.mdwn
new file mode 100644 (file)
index 0000000..f7826a4
--- /dev/null
+++ b/openpower/isa/fptrans/fatan2.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATAN2
+
+X-Form
+
+* fatan2 FRT,FRA,FRB (Rc=0)
+* fatan2. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatan2_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatan2_code.mdwn b/openpower/isa/fptrans/fatan2_code.mdwn
new file mode 100644 (file)
index 0000000..8588893
--- /dev/null
+++ b/openpower/isa/fptrans/fatan2_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ATAN2(FRA, FRB)

diff --git a/openpower/isa/fptrans/fatan2pi.mdwn b/openpower/isa/fptrans/fatan2pi.mdwn
new file mode 100644 (file)
index 0000000..378a081
--- /dev/null
+++ b/openpower/isa/fptrans/fatan2pi.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATAN2PI
+
+X-Form
+
+* fatan2pi FRT,FRA,FRB (Rc=0)
+* fatan2pi. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatan2pi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatan2pi_code.mdwn b/openpower/isa/fptrans/fatan2pi_code.mdwn
new file mode 100644 (file)
index 0000000..9986591
--- /dev/null
+++ b/openpower/isa/fptrans/fatan2pi_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ATAN2PI(FRA, FRB)

diff --git a/openpower/isa/fptrans/fatan2pis.mdwn b/openpower/isa/fptrans/fatan2pis.mdwn
new file mode 100644 (file)
index 0000000..5502436
--- /dev/null
+++ b/openpower/isa/fptrans/fatan2pis.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATAN2PI Single
+
+X-Form
+
+* fatan2pis FRT,FRA,FRB (Rc=0)
+* fatan2pis. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatan2pis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatan2pis_code.mdwn b/openpower/isa/fptrans/fatan2pis_code.mdwn
new file mode 100644 (file)
index 0000000..532e9c5
--- /dev/null
+++ b/openpower/isa/fptrans/fatan2pis_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ATAN2PI(SINGLE(FRA), SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fatan2s.mdwn b/openpower/isa/fptrans/fatan2s.mdwn
new file mode 100644 (file)
index 0000000..53bac4a
--- /dev/null
+++ b/openpower/isa/fptrans/fatan2s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATAN2 Single
+
+X-Form
+
+* fatan2s FRT,FRA,FRB (Rc=0)
+* fatan2s. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatan2s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatan2s_code.mdwn b/openpower/isa/fptrans/fatan2s_code.mdwn
new file mode 100644 (file)
index 0000000..2c9be12
--- /dev/null
+++ b/openpower/isa/fptrans/fatan2s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ATAN2(SINGLE(FRA), SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fatan_code.mdwn b/openpower/isa/fptrans/fatan_code.mdwn
new file mode 100644 (file)
index 0000000..cc4fb37
--- /dev/null
+++ b/openpower/isa/fptrans/fatan_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ATAN(FRB)

diff --git a/openpower/isa/fptrans/fatanh.mdwn b/openpower/isa/fptrans/fatanh.mdwn
new file mode 100644 (file)
index 0000000..fd67684
--- /dev/null
+++ b/openpower/isa/fptrans/fatanh.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATANH
+
+X-Form
+
+* fatanh FRT,FRB (Rc=0)
+* fatanh. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatanh_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatanh_code.mdwn b/openpower/isa/fptrans/fatanh_code.mdwn
new file mode 100644 (file)
index 0000000..3d8f42a
--- /dev/null
+++ b/openpower/isa/fptrans/fatanh_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ATANH(FRB)

diff --git a/openpower/isa/fptrans/fatanhs.mdwn b/openpower/isa/fptrans/fatanhs.mdwn
new file mode 100644 (file)
index 0000000..a8f0734
--- /dev/null
+++ b/openpower/isa/fptrans/fatanhs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATANH Single
+
+X-Form
+
+* fatanhs FRT,FRB (Rc=0)
+* fatanhs. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatanhs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatanhs_code.mdwn b/openpower/isa/fptrans/fatanhs_code.mdwn
new file mode 100644 (file)
index 0000000..29d3789
--- /dev/null
+++ b/openpower/isa/fptrans/fatanhs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ATANH(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fatanpi.mdwn b/openpower/isa/fptrans/fatanpi.mdwn
new file mode 100644 (file)
index 0000000..fa86b24
--- /dev/null
+++ b/openpower/isa/fptrans/fatanpi.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATANPI
+
+X-Form
+
+* fatanpi FRT,FRB (Rc=0)
+* fatanpi. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatanpi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatanpi_code.mdwn b/openpower/isa/fptrans/fatanpi_code.mdwn
new file mode 100644 (file)
index 0000000..7867b89
--- /dev/null
+++ b/openpower/isa/fptrans/fatanpi_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ATANPI(FRB)

diff --git a/openpower/isa/fptrans/fatanpis.mdwn b/openpower/isa/fptrans/fatanpis.mdwn
new file mode 100644 (file)
index 0000000..4a46277
--- /dev/null
+++ b/openpower/isa/fptrans/fatanpis.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATANPI Single
+
+X-Form
+
+* fatanpis FRT,FRB (Rc=0)
+* fatanpis. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatanpis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatanpis_code.mdwn b/openpower/isa/fptrans/fatanpis_code.mdwn
new file mode 100644 (file)
index 0000000..e92a788
--- /dev/null
+++ b/openpower/isa/fptrans/fatanpis_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ATANPI(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fatans.mdwn b/openpower/isa/fptrans/fatans.mdwn
new file mode 100644 (file)
index 0000000..a034c6a
--- /dev/null
+++ b/openpower/isa/fptrans/fatans.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ATAN Single
+
+X-Form
+
+* fatans FRT,FRB (Rc=0)
+* fatans. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fatans_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fatans_code.mdwn b/openpower/isa/fptrans/fatans_code.mdwn
new file mode 100644 (file)
index 0000000..86c8771
--- /dev/null
+++ b/openpower/isa/fptrans/fatans_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ATAN(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fcbrt.mdwn b/openpower/isa/fptrans/fcbrt.mdwn
new file mode 100644 (file)
index 0000000..a6d0fab
--- /dev/null
+++ b/openpower/isa/fptrans/fcbrt.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating CBRT
+
+X-Form
+
+* fcbrt FRT,FRB (Rc=0)
+* fcbrt. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fcbrt_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fcbrt_code.mdwn b/openpower/isa/fptrans/fcbrt_code.mdwn
new file mode 100644 (file)
index 0000000..88df72c
--- /dev/null
+++ b/openpower/isa/fptrans/fcbrt_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_CBRT(FRB)

diff --git a/openpower/isa/fptrans/fcbrts.mdwn b/openpower/isa/fptrans/fcbrts.mdwn
new file mode 100644 (file)
index 0000000..916bee5
--- /dev/null
+++ b/openpower/isa/fptrans/fcbrts.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating CBRT Single
+
+X-Form
+
+* fcbrts FRT,FRB (Rc=0)
+* fcbrts. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fcbrts_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fcbrts_code.mdwn b/openpower/isa/fptrans/fcbrts_code.mdwn
new file mode 100644 (file)
index 0000000..1cb6fd6
--- /dev/null
+++ b/openpower/isa/fptrans/fcbrts_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_CBRT(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fcos.mdwn b/openpower/isa/fptrans/fcos.mdwn
new file mode 100644 (file)
index 0000000..0bb6fe2
--- /dev/null
+++ b/openpower/isa/fptrans/fcos.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating COS
+
+X-Form
+
+* fcos FRT,FRB (Rc=0)
+* fcos. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fcos_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fcos_code.mdwn b/openpower/isa/fptrans/fcos_code.mdwn
new file mode 100644 (file)
index 0000000..d5a5f22
--- /dev/null
+++ b/openpower/isa/fptrans/fcos_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_COS(FRB)

diff --git a/openpower/isa/fptrans/fcosh.mdwn b/openpower/isa/fptrans/fcosh.mdwn
new file mode 100644 (file)
index 0000000..d4d42b4
--- /dev/null
+++ b/openpower/isa/fptrans/fcosh.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating COSH
+
+X-Form
+
+* fcosh FRT,FRB (Rc=0)
+* fcosh. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fcosh_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fcosh_code.mdwn b/openpower/isa/fptrans/fcosh_code.mdwn
new file mode 100644 (file)
index 0000000..f32de11
--- /dev/null
+++ b/openpower/isa/fptrans/fcosh_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_COSH(FRB)

diff --git a/openpower/isa/fptrans/fcoshs.mdwn b/openpower/isa/fptrans/fcoshs.mdwn
new file mode 100644 (file)
index 0000000..b6f5282
--- /dev/null
+++ b/openpower/isa/fptrans/fcoshs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating COSH Single
+
+X-Form
+
+* fcoshs FRT,FRB (Rc=0)
+* fcoshs. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fcoshs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fcoshs_code.mdwn b/openpower/isa/fptrans/fcoshs_code.mdwn
new file mode 100644 (file)
index 0000000..3d2cf05
--- /dev/null
+++ b/openpower/isa/fptrans/fcoshs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_COSH(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fcospi.mdwn b/openpower/isa/fptrans/fcospi.mdwn
new file mode 100644 (file)
index 0000000..e3fbf2b
--- /dev/null
+++ b/openpower/isa/fptrans/fcospi.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating COSPI
+
+X-Form
+
+* fcospi FRT,FRB (Rc=0)
+* fcospi. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fcospi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fcospi_code.mdwn b/openpower/isa/fptrans/fcospi_code.mdwn
new file mode 100644 (file)
index 0000000..48d220a
--- /dev/null
+++ b/openpower/isa/fptrans/fcospi_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_COSPI(FRB)

diff --git a/openpower/isa/fptrans/fcospis.mdwn b/openpower/isa/fptrans/fcospis.mdwn
new file mode 100644 (file)
index 0000000..10bcfbd
--- /dev/null
+++ b/openpower/isa/fptrans/fcospis.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating COSPI Single
+
+X-Form
+
+* fcospis FRT,FRB (Rc=0)
+* fcospis. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fcospis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fcospis_code.mdwn b/openpower/isa/fptrans/fcospis_code.mdwn
new file mode 100644 (file)
index 0000000..223341d
--- /dev/null
+++ b/openpower/isa/fptrans/fcospis_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_COSPI(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fcoss.mdwn b/openpower/isa/fptrans/fcoss.mdwn
new file mode 100644 (file)
index 0000000..413ceb3
--- /dev/null
+++ b/openpower/isa/fptrans/fcoss.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating COS Single
+
+X-Form
+
+* fcoss FRT,FRB (Rc=0)
+* fcoss. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fcoss_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fcoss_code.mdwn b/openpower/isa/fptrans/fcoss_code.mdwn
new file mode 100644 (file)
index 0000000..f94edef
--- /dev/null
+++ b/openpower/isa/fptrans/fcoss_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_COS(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fexp.mdwn b/openpower/isa/fptrans/fexp.mdwn
new file mode 100644 (file)
index 0000000..23095ac
--- /dev/null
+++ b/openpower/isa/fptrans/fexp.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP
+
+X-Form
+
+* fexp FRT,FRB (Rc=0)
+* fexp. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp10.mdwn b/openpower/isa/fptrans/fexp10.mdwn
new file mode 100644 (file)
index 0000000..932fb53
--- /dev/null
+++ b/openpower/isa/fptrans/fexp10.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP10
+
+X-Form
+
+* fexp10 FRT,FRB (Rc=0)
+* fexp10. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp10_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp10_code.mdwn b/openpower/isa/fptrans/fexp10_code.mdwn
new file mode 100644 (file)
index 0000000..705bb93
--- /dev/null
+++ b/openpower/isa/fptrans/fexp10_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_EXP10(FRB)

diff --git a/openpower/isa/fptrans/fexp10m1.mdwn b/openpower/isa/fptrans/fexp10m1.mdwn
new file mode 100644 (file)
index 0000000..7bf49d0
--- /dev/null
+++ b/openpower/isa/fptrans/fexp10m1.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP10M1
+
+X-Form
+
+* fexp10m1 FRT,FRB (Rc=0)
+* fexp10m1. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp10m1_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp10m1_code.mdwn b/openpower/isa/fptrans/fexp10m1_code.mdwn
new file mode 100644 (file)
index 0000000..64f8380
--- /dev/null
+++ b/openpower/isa/fptrans/fexp10m1_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_EXP10M1(FRB)

diff --git a/openpower/isa/fptrans/fexp10m1s.mdwn b/openpower/isa/fptrans/fexp10m1s.mdwn
new file mode 100644 (file)
index 0000000..3ff7744
--- /dev/null
+++ b/openpower/isa/fptrans/fexp10m1s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP10M1 Single
+
+X-Form
+
+* fexp10m1s FRT,FRB (Rc=0)
+* fexp10m1s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp10m1s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp10m1s_code.mdwn b/openpower/isa/fptrans/fexp10m1s_code.mdwn
new file mode 100644 (file)
index 0000000..bd7ecfa
--- /dev/null
+++ b/openpower/isa/fptrans/fexp10m1s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_EXP10M1(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fexp10s.mdwn b/openpower/isa/fptrans/fexp10s.mdwn
new file mode 100644 (file)
index 0000000..335d58c
--- /dev/null
+++ b/openpower/isa/fptrans/fexp10s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP10 Single
+
+X-Form
+
+* fexp10s FRT,FRB (Rc=0)
+* fexp10s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp10s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp10s_code.mdwn b/openpower/isa/fptrans/fexp10s_code.mdwn
new file mode 100644 (file)
index 0000000..d818b2a
--- /dev/null
+++ b/openpower/isa/fptrans/fexp10s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_EXP10(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fexp2.mdwn b/openpower/isa/fptrans/fexp2.mdwn
new file mode 100644 (file)
index 0000000..9f22464
--- /dev/null
+++ b/openpower/isa/fptrans/fexp2.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP2
+
+X-Form
+
+* fexp2 FRT,FRB (Rc=0)
+* fexp2. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp2_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp2_code.mdwn b/openpower/isa/fptrans/fexp2_code.mdwn
new file mode 100644 (file)
index 0000000..8d726d0
--- /dev/null
+++ b/openpower/isa/fptrans/fexp2_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_EXP2(FRB)

diff --git a/openpower/isa/fptrans/fexp2m1.mdwn b/openpower/isa/fptrans/fexp2m1.mdwn
new file mode 100644 (file)
index 0000000..7522e30
--- /dev/null
+++ b/openpower/isa/fptrans/fexp2m1.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP2M1
+
+X-Form
+
+* fexp2m1 FRT,FRB (Rc=0)
+* fexp2m1. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp2m1_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp2m1_code.mdwn b/openpower/isa/fptrans/fexp2m1_code.mdwn
new file mode 100644 (file)
index 0000000..926600e
--- /dev/null
+++ b/openpower/isa/fptrans/fexp2m1_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_EXP2M1(FRB)

diff --git a/openpower/isa/fptrans/fexp2m1s.mdwn b/openpower/isa/fptrans/fexp2m1s.mdwn
new file mode 100644 (file)
index 0000000..429ada3
--- /dev/null
+++ b/openpower/isa/fptrans/fexp2m1s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP2M1 Single
+
+X-Form
+
+* fexp2m1s FRT,FRB (Rc=0)
+* fexp2m1s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp2m1s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp2m1s_code.mdwn b/openpower/isa/fptrans/fexp2m1s_code.mdwn
new file mode 100644 (file)
index 0000000..97f26dc
--- /dev/null
+++ b/openpower/isa/fptrans/fexp2m1s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_EXP2M1(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fexp2s.mdwn b/openpower/isa/fptrans/fexp2s.mdwn
new file mode 100644 (file)
index 0000000..17ac621
--- /dev/null
+++ b/openpower/isa/fptrans/fexp2s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP2 Single
+
+X-Form
+
+* fexp2s FRT,FRB (Rc=0)
+* fexp2s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexp2s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexp2s_code.mdwn b/openpower/isa/fptrans/fexp2s_code.mdwn
new file mode 100644 (file)
index 0000000..f8da398
--- /dev/null
+++ b/openpower/isa/fptrans/fexp2s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_EXP2(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fexp_code.mdwn b/openpower/isa/fptrans/fexp_code.mdwn
new file mode 100644 (file)
index 0000000..9846c8a
--- /dev/null
+++ b/openpower/isa/fptrans/fexp_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_EXP(FRB)

diff --git a/openpower/isa/fptrans/fexpm1.mdwn b/openpower/isa/fptrans/fexpm1.mdwn
new file mode 100644 (file)
index 0000000..9fa3e73
--- /dev/null
+++ b/openpower/isa/fptrans/fexpm1.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXPM1
+
+X-Form
+
+* fexpm1 FRT,FRB (Rc=0)
+* fexpm1. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexpm1_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexpm1_code.mdwn b/openpower/isa/fptrans/fexpm1_code.mdwn
new file mode 100644 (file)
index 0000000..3e75fa5
--- /dev/null
+++ b/openpower/isa/fptrans/fexpm1_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_EXPM1(FRB)

diff --git a/openpower/isa/fptrans/fexpm1s.mdwn b/openpower/isa/fptrans/fexpm1s.mdwn
new file mode 100644 (file)
index 0000000..abc6d96
--- /dev/null
+++ b/openpower/isa/fptrans/fexpm1s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXPM1 Single
+
+X-Form
+
+* fexpm1s FRT,FRB (Rc=0)
+* fexpm1s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexpm1s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexpm1s_code.mdwn b/openpower/isa/fptrans/fexpm1s_code.mdwn
new file mode 100644 (file)
index 0000000..2699097
--- /dev/null
+++ b/openpower/isa/fptrans/fexpm1s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_EXPM1(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fexps.mdwn b/openpower/isa/fptrans/fexps.mdwn
new file mode 100644 (file)
index 0000000..8cba177
--- /dev/null
+++ b/openpower/isa/fptrans/fexps.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating EXP Single
+
+X-Form
+
+* fexps FRT,FRB (Rc=0)
+* fexps. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fexps_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fexps_code.mdwn b/openpower/isa/fptrans/fexps_code.mdwn
new file mode 100644 (file)
index 0000000..721cb09
--- /dev/null
+++ b/openpower/isa/fptrans/fexps_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_EXP(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fhypot.mdwn b/openpower/isa/fptrans/fhypot.mdwn
new file mode 100644 (file)
index 0000000..8b0522a
--- /dev/null
+++ b/openpower/isa/fptrans/fhypot.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating HYPOT
+
+X-Form
+
+* fhypot FRT,FRA,FRB (Rc=0)
+* fhypot. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fhypot_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fhypot_code.mdwn b/openpower/isa/fptrans/fhypot_code.mdwn
new file mode 100644 (file)
index 0000000..d6798d8
--- /dev/null
+++ b/openpower/isa/fptrans/fhypot_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_HYPOT(FRA, FRB)

diff --git a/openpower/isa/fptrans/fhypots.mdwn b/openpower/isa/fptrans/fhypots.mdwn
new file mode 100644 (file)
index 0000000..a184f8f
--- /dev/null
+++ b/openpower/isa/fptrans/fhypots.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating HYPOT Single
+
+X-Form
+
+* fhypots FRT,FRA,FRB (Rc=0)
+* fhypots. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fhypots_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fhypots_code.mdwn b/openpower/isa/fptrans/fhypots_code.mdwn
new file mode 100644 (file)
index 0000000..6e68a93
--- /dev/null
+++ b/openpower/isa/fptrans/fhypots_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_HYPOT(SINGLE(FRA), SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/flog.mdwn b/openpower/isa/fptrans/flog.mdwn
new file mode 100644 (file)
index 0000000..be1c7f6
--- /dev/null
+++ b/openpower/isa/fptrans/flog.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG
+
+X-Form
+
+* flog FRT,FRB (Rc=0)
+* flog. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog10.mdwn b/openpower/isa/fptrans/flog10.mdwn
new file mode 100644 (file)
index 0000000..c0bd396
--- /dev/null
+++ b/openpower/isa/fptrans/flog10.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG10
+
+X-Form
+
+* flog10 FRT,FRB (Rc=0)
+* flog10. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog10_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog10_code.mdwn b/openpower/isa/fptrans/flog10_code.mdwn
new file mode 100644 (file)
index 0000000..dacc36e
--- /dev/null
+++ b/openpower/isa/fptrans/flog10_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_LOG10(FRB)

diff --git a/openpower/isa/fptrans/flog10p1.mdwn b/openpower/isa/fptrans/flog10p1.mdwn
new file mode 100644 (file)
index 0000000..8ae725b
--- /dev/null
+++ b/openpower/isa/fptrans/flog10p1.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG10P1
+
+X-Form
+
+* flog10p1 FRT,FRB (Rc=0)
+* flog10p1. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog10p1_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog10p1_code.mdwn b/openpower/isa/fptrans/flog10p1_code.mdwn
new file mode 100644 (file)
index 0000000..c59aa93
--- /dev/null
+++ b/openpower/isa/fptrans/flog10p1_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_LOG10P1(FRB)

diff --git a/openpower/isa/fptrans/flog10p1s.mdwn b/openpower/isa/fptrans/flog10p1s.mdwn
new file mode 100644 (file)
index 0000000..a828c46
--- /dev/null
+++ b/openpower/isa/fptrans/flog10p1s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG10P1 Single
+
+X-Form
+
+* flog10p1s FRT,FRB (Rc=0)
+* flog10p1s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog10p1s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog10p1s_code.mdwn b/openpower/isa/fptrans/flog10p1s_code.mdwn
new file mode 100644 (file)
index 0000000..a60d563
--- /dev/null
+++ b/openpower/isa/fptrans/flog10p1s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_LOG10P1(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/flog10s.mdwn b/openpower/isa/fptrans/flog10s.mdwn
new file mode 100644 (file)
index 0000000..353788b
--- /dev/null
+++ b/openpower/isa/fptrans/flog10s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG10 Single
+
+X-Form
+
+* flog10s FRT,FRB (Rc=0)
+* flog10s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog10s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog10s_code.mdwn b/openpower/isa/fptrans/flog10s_code.mdwn
new file mode 100644 (file)
index 0000000..cb50574
--- /dev/null
+++ b/openpower/isa/fptrans/flog10s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_LOG10(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/flog2.mdwn b/openpower/isa/fptrans/flog2.mdwn
new file mode 100644 (file)
index 0000000..3a04fe5
--- /dev/null
+++ b/openpower/isa/fptrans/flog2.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG2
+
+X-Form
+
+* flog2 FRT,FRB (Rc=0)
+* flog2. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog2_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog2_code.mdwn b/openpower/isa/fptrans/flog2_code.mdwn
new file mode 100644 (file)
index 0000000..36a1e43
--- /dev/null
+++ b/openpower/isa/fptrans/flog2_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_LOG2(FRB)

diff --git a/openpower/isa/fptrans/flog2p1.mdwn b/openpower/isa/fptrans/flog2p1.mdwn
new file mode 100644 (file)
index 0000000..732d1d3
--- /dev/null
+++ b/openpower/isa/fptrans/flog2p1.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG2P1
+
+X-Form
+
+* flog2p1 FRT,FRB (Rc=0)
+* flog2p1. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog2p1_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog2p1_code.mdwn b/openpower/isa/fptrans/flog2p1_code.mdwn
new file mode 100644 (file)
index 0000000..5489464
--- /dev/null
+++ b/openpower/isa/fptrans/flog2p1_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_LOG2P1(FRB)

diff --git a/openpower/isa/fptrans/flog2p1s.mdwn b/openpower/isa/fptrans/flog2p1s.mdwn
new file mode 100644 (file)
index 0000000..8c553e1
--- /dev/null
+++ b/openpower/isa/fptrans/flog2p1s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG2P1 Single
+
+X-Form
+
+* flog2p1s FRT,FRB (Rc=0)
+* flog2p1s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog2p1s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog2p1s_code.mdwn b/openpower/isa/fptrans/flog2p1s_code.mdwn
new file mode 100644 (file)
index 0000000..9fd4e3c
--- /dev/null
+++ b/openpower/isa/fptrans/flog2p1s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_LOG2P1(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/flog2s.mdwn b/openpower/isa/fptrans/flog2s.mdwn
new file mode 100644 (file)
index 0000000..b6d9812
--- /dev/null
+++ b/openpower/isa/fptrans/flog2s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG2 Single
+
+X-Form
+
+* flog2s FRT,FRB (Rc=0)
+* flog2s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flog2s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flog2s_code.mdwn b/openpower/isa/fptrans/flog2s_code.mdwn
new file mode 100644 (file)
index 0000000..204a009
--- /dev/null
+++ b/openpower/isa/fptrans/flog2s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_LOG2(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/flog_code.mdwn b/openpower/isa/fptrans/flog_code.mdwn
new file mode 100644 (file)
index 0000000..340ee42
--- /dev/null
+++ b/openpower/isa/fptrans/flog_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_LOG(FRB)

diff --git a/openpower/isa/fptrans/flogp1.mdwn b/openpower/isa/fptrans/flogp1.mdwn
new file mode 100644 (file)
index 0000000..46a57fd
--- /dev/null
+++ b/openpower/isa/fptrans/flogp1.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOGP1
+
+X-Form
+
+* flogp1 FRT,FRB (Rc=0)
+* flogp1. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flogp1_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flogp1_code.mdwn b/openpower/isa/fptrans/flogp1_code.mdwn
new file mode 100644 (file)
index 0000000..9277180
--- /dev/null
+++ b/openpower/isa/fptrans/flogp1_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_LOGP1(FRB)

diff --git a/openpower/isa/fptrans/flogp1s.mdwn b/openpower/isa/fptrans/flogp1s.mdwn
new file mode 100644 (file)
index 0000000..634a7d3
--- /dev/null
+++ b/openpower/isa/fptrans/flogp1s.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOGP1 Single
+
+X-Form
+
+* flogp1s FRT,FRB (Rc=0)
+* flogp1s. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flogp1s_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flogp1s_code.mdwn b/openpower/isa/fptrans/flogp1s_code.mdwn
new file mode 100644 (file)
index 0000000..ddd99bf
--- /dev/null
+++ b/openpower/isa/fptrans/flogp1s_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_LOGP1(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/flogs.mdwn b/openpower/isa/fptrans/flogs.mdwn
new file mode 100644 (file)
index 0000000..e7b96a7
--- /dev/null
+++ b/openpower/isa/fptrans/flogs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating LOG Single
+
+X-Form
+
+* flogs FRT,FRB (Rc=0)
+* flogs. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/flogs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/flogs_code.mdwn b/openpower/isa/fptrans/flogs_code.mdwn
new file mode 100644 (file)
index 0000000..1d3efe2
--- /dev/null
+++ b/openpower/isa/fptrans/flogs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_LOG(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fminmax.mdwn b/openpower/isa/fptrans/fminmax.mdwn
new file mode 100644 (file)
index 0000000..2017dff
--- /dev/null
+++ b/openpower/isa/fptrans/fminmax.mdwn
@@ -0,0 +1,15 @@
+# [DRAFT] Floating Minimum/Maximum
+
+MM-Form
+
+* fminmax FRT,FRA,FRB,FMM (Rc=0)
+* fminmax. FRT,FRA,FRB,FMM (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fminmax_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FX VXSNAN
+    CR1     (if Rc=1)

diff --git a/openpower/isa/fptrans/fminmax_code.mdwn b/openpower/isa/fptrans/fminmax_code.mdwn
new file mode 100644 (file)
index 0000000..2a45df2
--- /dev/null
+++ b/openpower/isa/fptrans/fminmax_code.mdwn
@@ -0,0 +1,55 @@
+    result <- [0] * 64
+    a <- (FRA)
+    b <- (FRB)
+    abs_a <- 0b0 || a[1:63]
+    abs_b <- 0b0 || b[1:63]
+    a_is_nan <- abs_a >u 0x7FF0_0000_0000_0000
+    a_is_snan <- a_is_nan & (a[12] = 0)
+    b_is_nan <- abs_b >u 0x7FF0_0000_0000_0000
+    b_is_snan <- b_is_nan & (b[12] = 0)
+    any_snan <- a_is_snan | b_is_snan
+    a_quieted <- a
+    a_quieted[12] <- 1
+    b_quieted <- b
+    b_quieted[12] <- 1
+    if a_is_nan | b_is_nan then
+        if FMM[2:3] = 0b00 then  # min/maxnum08
+            if a_is_snan then result <- a_quieted
+            else if b_is_snan then result <- b_quieted
+            else if a_is_nan & b_is_nan then result <- a_quieted
+            else if a_is_nan then result <- b
+            else result <- a
+        if FMM[2:3] = 0b01 then  # min/max19
+            if a_is_nan then result <- a_quieted
+            else result <- b_quieted
+        if FMM[2:3] = 0b10 then  # min/maxnum19
+            if a_is_nan & b_is_nan then result <- a_quieted
+            else if a_is_nan then result <- b
+            else result <- a
+        if FMM[2:3] = 0b11 then  # min/maxc
+            result <- b
+    else
+        cmp_l <- a
+        cmp_r <- b
+        if FMM[1] then  # min/maxmag
+            if abs_a != abs_b then
+                cmp_l <- abs_a
+                cmp_r <- abs_b
+        if FMM[2:3] = 0b11 then  # min/maxc
+            if abs_a = 0 then cmp_l[0:63] <- 0
+            if abs_b = 0 then cmp_r[0:63] <- 0
+        if FMM[0] then  # max
+            # swap cmp_* so comparison goes the other way
+            cmp_l, cmp_r <- cmp_r, cmp_l
+        if cmp_l[0] = 1 then
+            if cmp_r[0] = 0 then result <- a
+            else if cmp_l >u cmp_r then
+                # IEEE 754 is sign-magnitude,
+                # so bigger magnitude negative is smaller
+                result <- a
+            else result <- b
+        else if cmp_r[0] = 1 then result <- b
+        else if cmp_l <u cmp_r then result <- a
+        else result <- b
+    if any_snan then SetFX(FPSCR.VXSNAN)
+    if (FPSCR.VE = 0) | ¬any_snan then (FRT) <- result

diff --git a/openpower/isa/fptrans/fmod.mdwn b/openpower/isa/fptrans/fmod.mdwn
new file mode 100644 (file)
index 0000000..c40b063
--- /dev/null
+++ b/openpower/isa/fptrans/fmod.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating MOD
+
+X-Form
+
+* fmod FRT,FRA,FRB (Rc=0)
+* fmod. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fmod_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fmod_code.mdwn b/openpower/isa/fptrans/fmod_code.mdwn
new file mode 100644 (file)
index 0000000..1510f71
--- /dev/null
+++ b/openpower/isa/fptrans/fmod_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_MOD(FRA, FRB)

diff --git a/openpower/isa/fptrans/fmods.mdwn b/openpower/isa/fptrans/fmods.mdwn
new file mode 100644 (file)
index 0000000..a16a00b
--- /dev/null
+++ b/openpower/isa/fptrans/fmods.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating MOD Single
+
+X-Form
+
+* fmods FRT,FRA,FRB (Rc=0)
+* fmods. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fmods_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fmods_code.mdwn b/openpower/isa/fptrans/fmods_code.mdwn
new file mode 100644 (file)
index 0000000..16d6601
--- /dev/null
+++ b/openpower/isa/fptrans/fmods_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_MOD(SINGLE(FRA), SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fpow.mdwn b/openpower/isa/fptrans/fpow.mdwn
new file mode 100644 (file)
index 0000000..570e4cf
--- /dev/null
+++ b/openpower/isa/fptrans/fpow.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating POW
+
+X-Form
+
+* fpow FRT,FRA,FRB (Rc=0)
+* fpow. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fpow_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fpow_code.mdwn b/openpower/isa/fptrans/fpow_code.mdwn
new file mode 100644 (file)
index 0000000..d99f1e7
--- /dev/null
+++ b/openpower/isa/fptrans/fpow_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_POW(FRA, FRB)

diff --git a/openpower/isa/fptrans/fpown.mdwn b/openpower/isa/fptrans/fpown.mdwn
new file mode 100644 (file)
index 0000000..ee33835
--- /dev/null
+++ b/openpower/isa/fptrans/fpown.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating POWN
+
+X-Form
+
+* fpown FRT,FRA,RB (Rc=0)
+* fpown. FRT,FRA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fpown_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fpown_code.mdwn b/openpower/isa/fptrans/fpown_code.mdwn
new file mode 100644 (file)
index 0000000..e7716da
--- /dev/null
+++ b/openpower/isa/fptrans/fpown_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_POWN(FRA, RB)

diff --git a/openpower/isa/fptrans/fpowns.mdwn b/openpower/isa/fptrans/fpowns.mdwn
new file mode 100644 (file)
index 0000000..8b8858c
--- /dev/null
+++ b/openpower/isa/fptrans/fpowns.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating POWN Single
+
+X-Form
+
+* fpowns FRT,FRA,RB (Rc=0)
+* fpowns. FRT,FRA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fpowns_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fpowns_code.mdwn b/openpower/isa/fptrans/fpowns_code.mdwn
new file mode 100644 (file)
index 0000000..a501e2d
--- /dev/null
+++ b/openpower/isa/fptrans/fpowns_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_POWN(SINGLE(FRA), RB))

diff --git a/openpower/isa/fptrans/fpowr.mdwn b/openpower/isa/fptrans/fpowr.mdwn
new file mode 100644 (file)
index 0000000..b267dc6
--- /dev/null
+++ b/openpower/isa/fptrans/fpowr.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating POWR
+
+X-Form
+
+* fpowr FRT,FRA,FRB (Rc=0)
+* fpowr. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fpowr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fpowr_code.mdwn b/openpower/isa/fptrans/fpowr_code.mdwn
new file mode 100644 (file)
index 0000000..634629a
--- /dev/null
+++ b/openpower/isa/fptrans/fpowr_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_POWR(FRA, FRB)

diff --git a/openpower/isa/fptrans/fpowrs.mdwn b/openpower/isa/fptrans/fpowrs.mdwn
new file mode 100644 (file)
index 0000000..7a74e6c
--- /dev/null
+++ b/openpower/isa/fptrans/fpowrs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating POWR Single
+
+X-Form
+
+* fpowrs FRT,FRA,FRB (Rc=0)
+* fpowrs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fpowrs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fpowrs_code.mdwn b/openpower/isa/fptrans/fpowrs_code.mdwn
new file mode 100644 (file)
index 0000000..d49baaf
--- /dev/null
+++ b/openpower/isa/fptrans/fpowrs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_POWR(SINGLE(FRA), SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fpows.mdwn b/openpower/isa/fptrans/fpows.mdwn
new file mode 100644 (file)
index 0000000..c56e8de
--- /dev/null
+++ b/openpower/isa/fptrans/fpows.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating POW Single
+
+X-Form
+
+* fpows FRT,FRA,FRB (Rc=0)
+* fpows. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fpows_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fpows_code.mdwn b/openpower/isa/fptrans/fpows_code.mdwn
new file mode 100644 (file)
index 0000000..f23673c
--- /dev/null
+++ b/openpower/isa/fptrans/fpows_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_POW(SINGLE(FRA), SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/frecip.mdwn b/openpower/isa/fptrans/frecip.mdwn
new file mode 100644 (file)
index 0000000..6a853e5
--- /dev/null
+++ b/openpower/isa/fptrans/frecip.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating RECIP
+
+X-Form
+
+* frecip FRT,FRB (Rc=0)
+* frecip. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/frecip_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/frecip_code.mdwn b/openpower/isa/fptrans/frecip_code.mdwn
new file mode 100644 (file)
index 0000000..28fb754
--- /dev/null
+++ b/openpower/isa/fptrans/frecip_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_RECIP(FRB)

diff --git a/openpower/isa/fptrans/frecips.mdwn b/openpower/isa/fptrans/frecips.mdwn
new file mode 100644 (file)
index 0000000..d4f3453
--- /dev/null
+++ b/openpower/isa/fptrans/frecips.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating RECIP Single
+
+X-Form
+
+* frecips FRT,FRB (Rc=0)
+* frecips. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/frecips_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/frecips_code.mdwn b/openpower/isa/fptrans/frecips_code.mdwn
new file mode 100644 (file)
index 0000000..d759475
--- /dev/null
+++ b/openpower/isa/fptrans/frecips_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_RECIP(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fremainder.mdwn b/openpower/isa/fptrans/fremainder.mdwn
new file mode 100644 (file)
index 0000000..a67eb64
--- /dev/null
+++ b/openpower/isa/fptrans/fremainder.mdwn
@@ -0,0 +1,18 @@
+# [DRAFT] Floating REMAINDER
+
+X-Form
+
+* fremainder FRT,FRA,FRB (Rc=0)
+* fremainder. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fremainder_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+

diff --git a/openpower/isa/fptrans/fremainder_code.mdwn b/openpower/isa/fptrans/fremainder_code.mdwn
new file mode 100644 (file)
index 0000000..c3b0349
--- /dev/null
+++ b/openpower/isa/fptrans/fremainder_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_REMAINDER(FRA, FRB)

diff --git a/openpower/isa/fptrans/fremainders.mdwn b/openpower/isa/fptrans/fremainders.mdwn
new file mode 100644 (file)
index 0000000..8710594
--- /dev/null
+++ b/openpower/isa/fptrans/fremainders.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating REMAINDER Single
+
+X-Form
+
+* fremainders FRT,FRA,FRB (Rc=0)
+* fremainders. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fremainders_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fremainders_code.mdwn b/openpower/isa/fptrans/fremainders_code.mdwn
new file mode 100644 (file)
index 0000000..f07017e
--- /dev/null
+++ b/openpower/isa/fptrans/fremainders_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_REMAINDER(SINGLE(FRA), SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/frootn.mdwn b/openpower/isa/fptrans/frootn.mdwn
new file mode 100644 (file)
index 0000000..cd03e5c
--- /dev/null
+++ b/openpower/isa/fptrans/frootn.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ROOTN
+
+X-Form
+
+* frootn FRT,FRA,RB (Rc=0)
+* frootn. FRT,FRA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/frootn_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/frootn_code.mdwn b/openpower/isa/fptrans/frootn_code.mdwn
new file mode 100644 (file)
index 0000000..fdfec64
--- /dev/null
+++ b/openpower/isa/fptrans/frootn_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_ROOTN(FRA, RB)

diff --git a/openpower/isa/fptrans/frootns.mdwn b/openpower/isa/fptrans/frootns.mdwn
new file mode 100644 (file)
index 0000000..9f97e0c
--- /dev/null
+++ b/openpower/isa/fptrans/frootns.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating ROOTN Single
+
+X-Form
+
+* frootns FRT,FRA,RB (Rc=0)
+* frootns. FRT,FRA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/frootns_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/frootns_code.mdwn b/openpower/isa/fptrans/frootns_code.mdwn
new file mode 100644 (file)
index 0000000..1cbabbe
--- /dev/null
+++ b/openpower/isa/fptrans/frootns_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_ROOTN(SINGLE(FRA), RB))

diff --git a/openpower/isa/fptrans/frsqrt.mdwn b/openpower/isa/fptrans/frsqrt.mdwn
new file mode 100644 (file)
index 0000000..9343c54
--- /dev/null
+++ b/openpower/isa/fptrans/frsqrt.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating RSQRT
+
+X-Form
+
+* frsqrt FRT,FRB (Rc=0)
+* frsqrt. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/frsqrt_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/frsqrt_code.mdwn b/openpower/isa/fptrans/frsqrt_code.mdwn
new file mode 100644 (file)
index 0000000..a2aeb1f
--- /dev/null
+++ b/openpower/isa/fptrans/frsqrt_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_RSQRT(FRB)

diff --git a/openpower/isa/fptrans/frsqrts.mdwn b/openpower/isa/fptrans/frsqrts.mdwn
new file mode 100644 (file)
index 0000000..d44bc1e
--- /dev/null
+++ b/openpower/isa/fptrans/frsqrts.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating RSQRT Single
+
+X-Form
+
+* frsqrts FRT,FRB (Rc=0)
+* frsqrts. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/frsqrts_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/frsqrts_code.mdwn b/openpower/isa/fptrans/frsqrts_code.mdwn
new file mode 100644 (file)
index 0000000..edd68e1
--- /dev/null
+++ b/openpower/isa/fptrans/frsqrts_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_RSQRT(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fsin.mdwn b/openpower/isa/fptrans/fsin.mdwn
new file mode 100644 (file)
index 0000000..71b673b
--- /dev/null
+++ b/openpower/isa/fptrans/fsin.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating SIN
+
+X-Form
+
+* fsin FRT,FRB (Rc=0)
+* fsin. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fsin_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fsin_code.mdwn b/openpower/isa/fptrans/fsin_code.mdwn
new file mode 100644 (file)
index 0000000..6761bec
--- /dev/null
+++ b/openpower/isa/fptrans/fsin_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_SIN(FRB)

diff --git a/openpower/isa/fptrans/fsinh.mdwn b/openpower/isa/fptrans/fsinh.mdwn
new file mode 100644 (file)
index 0000000..250921b
--- /dev/null
+++ b/openpower/isa/fptrans/fsinh.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating SINH
+
+X-Form
+
+* fsinh FRT,FRB (Rc=0)
+* fsinh. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fsinh_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fsinh_code.mdwn b/openpower/isa/fptrans/fsinh_code.mdwn
new file mode 100644 (file)
index 0000000..6657f6d
--- /dev/null
+++ b/openpower/isa/fptrans/fsinh_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_SINH(FRB)

diff --git a/openpower/isa/fptrans/fsinhs.mdwn b/openpower/isa/fptrans/fsinhs.mdwn
new file mode 100644 (file)
index 0000000..e1d703f
--- /dev/null
+++ b/openpower/isa/fptrans/fsinhs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating SINH Single
+
+X-Form
+
+* fsinhs FRT,FRB (Rc=0)
+* fsinhs. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fsinhs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fsinhs_code.mdwn b/openpower/isa/fptrans/fsinhs_code.mdwn
new file mode 100644 (file)
index 0000000..098c021
--- /dev/null
+++ b/openpower/isa/fptrans/fsinhs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_SINH(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fsinpi.mdwn b/openpower/isa/fptrans/fsinpi.mdwn
new file mode 100644 (file)
index 0000000..afbb750
--- /dev/null
+++ b/openpower/isa/fptrans/fsinpi.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating SINPI
+
+X-Form
+
+* fsinpi FRT,FRB (Rc=0)
+* fsinpi. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fsinpi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fsinpi_code.mdwn b/openpower/isa/fptrans/fsinpi_code.mdwn
new file mode 100644 (file)
index 0000000..8a24ddb
--- /dev/null
+++ b/openpower/isa/fptrans/fsinpi_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_SINPI(FRB)

diff --git a/openpower/isa/fptrans/fsinpis.mdwn b/openpower/isa/fptrans/fsinpis.mdwn
new file mode 100644 (file)
index 0000000..2216eb5
--- /dev/null
+++ b/openpower/isa/fptrans/fsinpis.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating SINPI Single
+
+X-Form
+
+* fsinpis FRT,FRB (Rc=0)
+* fsinpis. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fsinpis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fsinpis_code.mdwn b/openpower/isa/fptrans/fsinpis_code.mdwn
new file mode 100644 (file)
index 0000000..c910743
--- /dev/null
+++ b/openpower/isa/fptrans/fsinpis_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_SINPI(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/fsins.mdwn b/openpower/isa/fptrans/fsins.mdwn
new file mode 100644 (file)
index 0000000..fb3c1c5
--- /dev/null
+++ b/openpower/isa/fptrans/fsins.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating SIN Single
+
+X-Form
+
+* fsins FRT,FRB (Rc=0)
+* fsins. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/fsins_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/fsins_code.mdwn b/openpower/isa/fptrans/fsins_code.mdwn
new file mode 100644 (file)
index 0000000..73416a3
--- /dev/null
+++ b/openpower/isa/fptrans/fsins_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_SIN(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/ftan.mdwn b/openpower/isa/fptrans/ftan.mdwn
new file mode 100644 (file)
index 0000000..9adf94b
--- /dev/null
+++ b/openpower/isa/fptrans/ftan.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating TAN
+
+X-Form
+
+* ftan FRT,FRB (Rc=0)
+* ftan. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/ftan_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/ftan_code.mdwn b/openpower/isa/fptrans/ftan_code.mdwn
new file mode 100644 (file)
index 0000000..0283010
--- /dev/null
+++ b/openpower/isa/fptrans/ftan_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_TAN(FRB)

diff --git a/openpower/isa/fptrans/ftanh.mdwn b/openpower/isa/fptrans/ftanh.mdwn
new file mode 100644 (file)
index 0000000..e6b8a77
--- /dev/null
+++ b/openpower/isa/fptrans/ftanh.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating TANH
+
+X-Form
+
+* ftanh FRT,FRB (Rc=0)
+* ftanh. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/ftanh_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/ftanh_code.mdwn b/openpower/isa/fptrans/ftanh_code.mdwn
new file mode 100644 (file)
index 0000000..af1596a
--- /dev/null
+++ b/openpower/isa/fptrans/ftanh_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_TANH(FRB)

diff --git a/openpower/isa/fptrans/ftanhs.mdwn b/openpower/isa/fptrans/ftanhs.mdwn
new file mode 100644 (file)
index 0000000..ce2aa95
--- /dev/null
+++ b/openpower/isa/fptrans/ftanhs.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating TANH Single
+
+X-Form
+
+* ftanhs FRT,FRB (Rc=0)
+* ftanhs. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/ftanhs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/ftanhs_code.mdwn b/openpower/isa/fptrans/ftanhs_code.mdwn
new file mode 100644 (file)
index 0000000..c9257c8
--- /dev/null
+++ b/openpower/isa/fptrans/ftanhs_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_TANH(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/ftanpi.mdwn b/openpower/isa/fptrans/ftanpi.mdwn
new file mode 100644 (file)
index 0000000..8b439b5
--- /dev/null
+++ b/openpower/isa/fptrans/ftanpi.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating TANPI
+
+X-Form
+
+* ftanpi FRT,FRB (Rc=0)
+* ftanpi. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/ftanpi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/ftanpi_code.mdwn b/openpower/isa/fptrans/ftanpi_code.mdwn
new file mode 100644 (file)
index 0000000..07a6c97
--- /dev/null
+++ b/openpower/isa/fptrans/ftanpi_code.mdwn
@@ -0,0 +1 @@
+    FRT <- bfp64_TANPI(FRB)

diff --git a/openpower/isa/fptrans/ftanpis.mdwn b/openpower/isa/fptrans/ftanpis.mdwn
new file mode 100644 (file)
index 0000000..692b122
--- /dev/null
+++ b/openpower/isa/fptrans/ftanpis.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating TANPI Single
+
+X-Form
+
+* ftanpis FRT,FRB (Rc=0)
+* ftanpis. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/ftanpis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/ftanpis_code.mdwn b/openpower/isa/fptrans/ftanpis_code.mdwn
new file mode 100644 (file)
index 0000000..c1600b4
--- /dev/null
+++ b/openpower/isa/fptrans/ftanpis_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_TANPI(SINGLE(FRB)))

diff --git a/openpower/isa/fptrans/ftans.mdwn b/openpower/isa/fptrans/ftans.mdwn
new file mode 100644 (file)
index 0000000..9e823c4
--- /dev/null
+++ b/openpower/isa/fptrans/ftans.mdwn
@@ -0,0 +1,17 @@
+# [DRAFT] Floating TAN Single
+
+X-Form
+
+* ftans FRT,FRB (Rc=0)
+* ftans. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fptrans/ftans_code" raw="yes"]]
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)

diff --git a/openpower/isa/fptrans/ftans_code.mdwn b/openpower/isa/fptrans/ftans_code.mdwn
new file mode 100644 (file)
index 0000000..63ead94
--- /dev/null
+++ b/openpower/isa/fptrans/ftans_code.mdwn
@@ -0,0 +1 @@
+    FRT <- DOUBLE(bfp32_TAN(SINGLE(FRB)))