class dst_reg;
+class vec4_live_variables;
+
unsigned
swizzle_for_size(int size);
unsigned int max_grf;
int *virtual_grf_start;
int *virtual_grf_end;
+ brw::vec4_live_variables *live_intervals;
dst_reg userplane[MAX_CLIP_PLANES];
/**
/** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
int *virtual_grf_reg_map;
- bool live_intervals_valid;
-
dst_reg *variable_storage(ir_variable *var);
void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
void
vec4_visitor::calculate_live_intervals()
{
- if (this->live_intervals_valid)
+ if (this->live_intervals)
return;
int *start = ralloc_array(mem_ctx, int, this->virtual_grf_count * 4);
* The control flow-aware analysis was done at a channel level, while at
* this point we're distilling it down to vgrfs.
*/
- vec4_live_variables livevars(this, cfg);
+ this->live_intervals = new(mem_ctx) vec4_live_variables(this, cfg);
foreach_block (block, cfg) {
- for (int i = 0; i < livevars.num_vars; i++) {
- if (BITSET_TEST(livevars.bd[block->num].livein, i)) {
+ for (int i = 0; i < live_intervals->num_vars; i++) {
+ if (BITSET_TEST(live_intervals->bd[block->num].livein, i)) {
start[i] = MIN2(start[i], block->start_ip);
end[i] = MAX2(end[i], block->start_ip);
}
- if (BITSET_TEST(livevars.bd[block->num].liveout, i)) {
+ if (BITSET_TEST(live_intervals->bd[block->num].liveout, i)) {
start[i] = MIN2(start[i], block->end_ip);
end[i] = MAX2(end[i], block->end_ip);
}
}
}
-
- this->live_intervals_valid = true;
}
void
vec4_visitor::invalidate_live_intervals()
{
- live_intervals_valid = false;
+ ralloc_free(live_intervals);
+ live_intervals = NULL;
}
bool
this->virtual_grf_reg_map = NULL;
this->virtual_grf_reg_count = 0;
this->virtual_grf_array_size = 0;
- this->live_intervals_valid = false;
+ this->live_intervals = NULL;
this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;