Use PLI to load up large constants if -mcpu=future.

2019-12-17  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (num_insns_constant_gpr): Return 1 if the
	constant can be loaded with PLI if -mcpu=future.
	* config/rs6000/rs6000.md (movdi_internal64): Add alternative to
	use PLI to load up 34-bit constants if -mcpu=future.

From-SVN: r279474

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6267594928576aa92f5e12d94bad24571a7f399a..233771c4f83497d1712429ee4b932ec214ee03de 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-12-17  Michael Meissner  <meissner@linux.ibm.com>
+
+       * config/rs6000/rs6000.c (num_insns_constant_gpr): Return 1 if the
+       constant can be loaded with PLI if -mcpu=future.
+       * config/rs6000/rs6000.md (movdi_internal64): Add alternative to
+       use PLI to load up 34-bit constants if -mcpu=future.
+
 2019-12-17  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/92841

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 6f0c7fa2db951a2872065f6c9b57485ff5a20968..002a8d89ccd56bafeb549961f5fb6f0aea751227 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -5565,6 +5565,10 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
           && (value >> 31 == -1 || value >> 31 == 0))
     return 1;
 
+  /* PADDI can support up to 34 bit signed integers.  */
+  else if (TARGET_PREFIXED_ADDR && SIGNED_34BIT_OFFSET_P (value))
+    return 1;
+
   else if (TARGET_POWERPC64)
     {
       HOST_WIDE_INT low  = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4a6416ef5c282cede3077dd8d2795cb97e3ae38a..31819837f7e0ad406dd1cdcafeb6ab53de8b3c31 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8828,7 +8828,7 @@
 })
 
 ;;        GPR store   GPR load    GPR move
-;;        GPR li      GPR lis     GPR #
+;;        GPR li      GPR lis     GPR pli     GPR #
 ;;        FPR store   FPR load    FPR move
 ;;        AVX store   AVX store   AVX load    AVX load    VSX move
 ;;        P9 0        P9 -1       AVX 0/-1    VSX 0       VSX -1
@@ -8838,7 +8838,7 @@
 (define_insn "*movdi_internal64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
          "=YZ,        r,          r,
-          r,          r,          r,
+          r,          r,          r,          r,
           m,          ^d,         ^d,
           wY,         Z,          $v,         $v,         ^wa,
           wa,         wa,         v,          wa,         wa,
@@ -8847,7 +8847,7 @@
           ?r,         ?wa")
        (match_operand:DI 1 "input_operand"
          "r,          YZ,         r,
-          I,          L,          nF,
+          I,          L,          eI,         nF,
           ^d,         m,          ^d,
           ^v,         $v,         wY,         Z,          ^wa,
           Oj,         wM,         OjwM,       Oj,         wM,
@@ -8863,6 +8863,7 @@
    mr %0,%1
    li %0,%1
    lis %0,%v1
+   li %0,%1
    #
    stfd%U0%X0 %1,%0
    lfd%U1%X1 %0,%1
@@ -8886,7 +8887,7 @@
    mtvsrd %x0,%1"
   [(set_attr "type"
          "store,      load,       *,
-          *,          *,          *,
+          *,          *,          *,          *,
           fpstore,    fpload,     fpsimple,
           fpstore,    fpstore,    fpload,     fpload,     veclogical,
           vecsimple,  vecsimple,  vecsimple,  veclogical, veclogical,
@@ -8896,7 +8897,7 @@
    (set_attr "size" "64")
    (set_attr "length"
          "*,          *,          *,
-          *,          *,          20,
+          *,          *,          *,          20,
           *,          *,          *,
           *,          *,          *,          *,          *,
           *,          *,          *,          *,          *,
@@ -8905,7 +8906,7 @@
           *,          *")
    (set_attr "isa"
          "*,          *,          *,
-          *,          *,          *,
+          *,          *,          fut,        *,
           *,          *,          *,
           p9v,        p7v,        p9v,        p7v,        *,
           p9v,        p9v,        p7v,        *,          *,