src_offset += csize << shift;
size -= csize;
}
+ r600_dma_emit_wait_idle(&rctx->b);
}
/* The max number of bytes to copy per packet. */
addr += cheight * pitch;
y += cheight;
}
+ r600_dma_emit_wait_idle(&rctx->b);
}
static void evergreen_dma_copy(struct pipe_context *ctx,
src_offset += csize << 2;
size -= csize;
}
+ r600_dma_emit_wait_idle(&rctx->b);
}
addr += cheight * pitch;
y += cheight;
}
+ r600_dma_emit_wait_idle(&rctx->b);
return TRUE;
}
}
}
+/* This is required to prevent read-after-write hazards. */
+void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
+{
+ struct radeon_winsys_cs *cs = rctx->dma.cs;
+
+ /* done at the end of DMA calls, so increment this. */
+ rctx->num_dma_calls++;
+
+ r600_need_dma_space(rctx, 1);
+
+ if (cs->cdw == 0) /* empty queue */
+ return;
+
+ /* NOP waits for idle on Evergreen and later. */
+ if (rctx->chip_class >= CIK)
+ radeon_emit(cs, 0x00000000); /* NOP */
+ else if (rctx->chip_class >= EVERGREEN)
+ radeon_emit(cs, 0xf0000000); /* NOP */
+ else {
+ /* TODO: R600-R700 should use the FENCE packet.
+ * CS checker support is required. */
+ }
+}
+
static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
{
}
const struct pipe_resource *templ);
const char *r600_get_llvm_processor_name(enum radeon_family family);
void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
+void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
/* r600_gpu_load.c */
void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
dst_offset + size);
cik_sdma_do_copy_buffer(ctx, dst, src, dst_offset, src_offset, size);
+ r600_dma_emit_wait_idle(&ctx->b);
}
static void cik_sdma_copy(struct pipe_context *ctx,
src_offset += csize << shift;
size -= csize;
}
+ r600_dma_emit_wait_idle(&ctx->b);
}
static void si_dma_copy_tile(struct si_context *ctx,
addr += cheight * pitch;
tiled_y += cheight;
}
+ r600_dma_emit_wait_idle(&ctx->b);
}
static void si_dma_copy(struct pipe_context *ctx,