ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex)
ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex)
-ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, cortex)
-ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, cortex)
-ARM_CORE("cortex-m0plus", cortexm0plus, 6M, FL_LDSCHED, cortex)
+ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, v6m)
+ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, v6m)
+ARM_CORE("cortex-m0plus", cortexm0plus, 6M, FL_LDSCHED, v6m)
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};
const struct tune_params arm_fastmul_tune =
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};
/* StrongARM has early execution of branches, so a sequence that is worth
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};
const struct tune_params arm_xscale_tune =
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};
const struct tune_params arm_9e_tune =
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};
const struct tune_params arm_v6t2_tune =
ARM_PREFETCH_NOT_BENEFICIAL,
false, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};
/* Generic Cortex tuning. Use more specific tunings if appropriate. */
ARM_PREFETCH_NOT_BENEFICIAL,
false, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};
const struct tune_params arm_cortex_a15_tune =
ARM_PREFETCH_NOT_BENEFICIAL,
false, /* Prefer constant pool. */
arm_default_branch_cost,
- true /* Prefer LDRD/STRD. */
+ true, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};
/* Branches can be dual-issued on Cortex-A5, so conditional execution is
ARM_PREFETCH_NOT_BENEFICIAL,
false, /* Prefer constant pool. */
arm_cortex_a5_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {false, false}, /* Prefer non short circuit. */
};
const struct tune_params arm_cortex_a9_tune =
ARM_PREFETCH_BENEFICIAL(4,32,32),
false, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
+};
+
+/* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
+ arm_v6t2_tune. It is used for cortex-m0, cortex-m1 and cortex-m0plus. */
+const struct tune_params arm_v6m_tune =
+{
+ arm_9e_rtx_costs,
+ NULL,
+ 1, /* Constant limit. */
+ 5, /* Max cond insns. */
+ ARM_PREFETCH_NOT_BENEFICIAL,
+ false, /* Prefer constant pool. */
+ arm_default_branch_cost,
+ false, /* Prefer LDRD/STRD. */
+ {false, false}, /* Prefer non short circuit. */
};
const struct tune_params arm_fa726te_tune =
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
arm_default_branch_cost,
- false /* Prefer LDRD/STRD. */
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
};