slicc: Controllers attached to Sequencers no longer have to be named L1Cache.

diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 85df3f9e883c01b9be251d207c6ef8b2e3f7df0f..7d863e349d587f5a0d9356165f7b4dcc16656d69 100644 (file)
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -499,6 +499,13 @@ $c_ident::$c_ident(const Params *p)
                 code('''
 m_${{seq}}_ptr->setController(this);
     ''')
+
+        else:
+            for seq in sequencers:
+                code('''
+m_${{seq}}_ptr->setController(this);
+    ''')
+
         #
         # For the DMA controller, pass the sequencer a pointer to the
         # controller.