(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 754b510da3b74331fe984a797a0625f650bf77d9..33743af8ff01f2bd22071797b8f78a8e8a013e0a 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -11,6 +11,14 @@ That said, there are a few exceptional places where these rules get
 bent, and others where the rules take some explaining,
 and this page tracks them.
 
+*(An experiment was attempted to modify LD-immediate instructions
+to include a
+third RC register i.e. reinterpret the normal
+v3.0 32-bit instruction as a
+different encoding if SVP64-prefixed: it did not go well.
+The complexity that resulted
+in the decode phase was too great)*
+
 # CR weird instructions
 
 [[sv/int_cr_predication]] is by far the biggest violator of the SVP64