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diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 70a7ab0a0b2d9df27f0f6f8b6b47f58f166f9527..f76d8b8a911a8131933d8120bf2b05e8138b6b4e 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2308,8 +2308,9 @@ and VL need to be set.
 
 By contrast, the VLIW prefix is only 16 bits, the VL/MAX/SubVL block is
 only 16 bits, and as long as not too many predicates and register vector
-qualifiers are specified, several 32-bit and 16-bit opcodes can fit into the
-format. If the full flexibility of the 16 bit block formats are not needed, more space is saved by using the 8 bit formats.
+qualifiers are specified, several 32-bit and 16-bit opcodes can fit into
+the format. If the full flexibility of the 16 bit block formats are not
+needed, more space is saved by using the 8 bit formats.
 
 In this light, embedding the VL/MAXVL, PredCam and RegCam CSR entries into
 a VLIW format makes a lot of sense.