LLVMValueRef z = ac_to_float(&ctx->ac,
llvm_extract_elem(&ctx->ac, comparator, 0));
- /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
+ /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
* so the depth comparison value isn't clamped for Z16 and
* Z24 anymore. Do it manually here.
*
* It's unnecessary if the original texture format was
* Z32_FLOAT, but we don't know that here.
*/
- if (ctx->ac.chip_class == VI)
+ if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
z = ac_build_clamp(&ctx->ac, z);
address[count++] = z;
ctx.abi.emit_outputs = handle_shader_outputs_post;
ctx.abi.load_ssbo = radv_load_ssbo;
ctx.abi.load_sampler_desc = radv_get_sampler_desc;
+ ctx.abi.clamp_shadow_reference = false;
if (shader_count >= 2)
ac_init_exec_full_mask(&ctx.ac);
struct ac_shader_variant_key key;
bool unsafe_math;
bool supports_spill;
+ bool clamp_shadow_reference;
enum radeon_family family;
enum chip_class chip_class;
};
LLVMValueRef index,
enum ac_descriptor_type desc_type,
bool image, bool write);
+
+ /* Whether to clamp the shadow reference value to [0,1]on VI. Radeonsi currently
+ * uses it due to promoting D16 to D32, but radv needs it off. */
+ bool clamp_shadow_reference;
};
#endif /* AC_SHADER_ABI_H */
ctx->abi.inputs = &ctx->inputs[0];
ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
+ ctx->abi.clamp_shadow_reference = true;
ctx->num_samplers = util_last_bit(info->samplers_declared);
ctx->num_images = util_last_bit(info->images_declared);