radv: only emit dfsm packets if dfsm is allowed.

radeonsi only emits these when dfsm is enabled, so for now
just hinge them on a flag we never set.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ba382c8691bdad93f0d61b37edf8fd985117227a..807283be1d8133ccd9122d4fa260d343329b54ef 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -551,7 +551,7 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
        radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 
        /* GFX9: Flush DFSM when the AA mode changes. */
-       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+       if (cmd_buffer->device->dfsm_allowed) {
                radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
                radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
        }
@@ -956,7 +956,7 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
        radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
        radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
 
-       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+       if (cmd_buffer->device->dfsm_allowed) {
                /* optimise this? */
                radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
                radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
@@ -1443,7 +1443,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
                               S_028208_BR_X(framebuffer->width) |
                               S_028208_BR_Y(framebuffer->height));
 
-       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+       if (cmd_buffer->device->dfsm_allowed) {
                radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
                radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
        }

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index a4e52b253066997aff3f8ae910d84f42cf372609..83529015c5dfa07db2c1acbe741f76c44f3455fb 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -531,6 +531,7 @@ struct radv_device {
 
        bool llvm_supports_spill;
        bool has_distributed_tess;
+       bool dfsm_allowed;
        uint32_t tess_offchip_block_dw_size;
        uint32_t scratch_waves;