utils/litex_sim: handle cpu_endianness for rom-init/ram-init

diff --git a/litex/utils/litex_sim.py b/litex/utils/litex_sim.py
index 868dbb19724e895354b0280d4d4093a68cf1480d..3a485a97cbcc166ff4e00104d729a64ef940a1af 100755 (executable)
--- a/litex/utils/litex_sim.py
+++ b/litex/utils/litex_sim.py
@@ -215,12 +215,18 @@ def main():
 
     sim_config = SimConfig(default_clk="sys_clk")
     sim_config.add_module("serial2console", "serial")
+
+    cpu_endianness = "big"
+    if "cpu_type" in soc_kwargs:
+        if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]:
+            cpu_endianness = "little"
+
     if args.rom_init:
-        soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
+        soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
     if not args.with_sdram:
         soc_kwargs["integrated_main_ram_size"] = 0x1000000 # 256 MB
         if args.ram_init is not None:
-            soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
+            soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
     else:
         assert args.ram_init is None
         soc_kwargs["integrated_main_ram_size"] = 0x0