testsuite: Fix gcc.target/i386/zero-scratch-regs-*.c scan-asm directives

Improve zero-scratch-regs-*.c scan-asm regexps
and add target selectors for 32bit targets.

2020-11-03  Uroš Bizjak  <ubizjak@gmail.com>

gcc/testsuite/ChangeLog:

	* gcc.target/i386/zero-scratch-regs-1.c: Add ia32 target
	selector where appropriate.  Improve scan-assembler regexp.
	* gcc.target/i386/zero-scratch-regs-2.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-3.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-4.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-5.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-6.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-7.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-8.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-9.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-10.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-13.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-14.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-15.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-16.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-17.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-18.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-19.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-20.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-21.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-22.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-23.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-24.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-25.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-26.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-27.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-28.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-29.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-30.c: Ditto.
	* gcc.target/i386/zero-scratch-regs-31.c: Ditto.

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c
index 9f61dc4c863277856e5acad158f36a8c68817b6c..1ea6de880aa475698e116571cfce15e47b44fb02 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c
@@ -8,5 +8,5 @@ foo (void)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
-/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */
+/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c
index 09048e57f9460890d0766a6cb58bfd053adbb2ec..389b11422642e3e811be519f8cdfcc5fdfc0605d 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c
@@ -11,11 +11,11 @@ foo (int x)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edx, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c
index 8b058e35540d3d08a6958c7f7282c2f08e7bff0a..07d8de7c66fa5b1ecc69ac1f2a293e117d44bab1 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c
@@ -7,15 +7,15 @@ foo (void)
 }
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
-/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm0, %xmm0" } } */
-/* { dg-final { scan-assembler-times "movaps\[ \t\]*%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */
-/* { dg-final { scan-assembler-times "movaps\[ \t\]*%xmm0, %xmm\[0-9\]+" 15 { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */
+/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */
+/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 15 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c
index d4eaaf7f383eb556e15aeec07753f0e595f97a9c..55a272cc53fcdb1a85dd957985ef3f9813db9090 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c
@@ -8,12 +8,12 @@ foo (void)
 
 /* { dg-final { scan-assembler-times "vzeroall" 1 } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c
index dd3bb90aa7dd39e277276c27439526ab4ec6e92b..d0e975cb3d3a48d5123891f7a9ff2d1991d9df35 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c
@@ -10,5 +10,5 @@ foo (void)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
-/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */
+/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c
index e2274f66a5ef769e62aa5c0cb6f4652919669e62..d41a2557d109f990ad92c5ef8b2b962977e4ca23 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c
@@ -10,5 +10,5 @@ foo (void)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
-/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */
+/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c
index 7f5d153088f1cba62a21a23c3c11a8c722f6304e..c79fcd39d7b12b3bb579cf0a8cb30fcdd2e68e52 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c
@@ -9,5 +9,5 @@ foo (int x)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" { target ia32 } } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" { target ia32 } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c
index fe13d2b4f133eaf353eb6534ab5d1d6ad1617f53..6f90723cc8eee7e862a39707114eee802a75169d 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c
@@ -8,6 +8,6 @@ foo (float z, float y, float x)
 }
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
-/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm1, %xmm1" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm1, %xmm2" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c
index 205a5323c560c5c2a5f784b986d1c67882410514..491d2d567748e4802ee4ffcb5498748425a21b58 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c
@@ -8,5 +8,5 @@ foo (float z, float y, float x)
 }
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
-/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm2, %xmm2" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c
index e046684dc78351a264a6c15213a14af80d46d436..52406fc70aaf2756c2aa5f42540c9d4e97c3c80f 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c
@@ -8,12 +8,12 @@ foo (void)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c
index 4be8ff6e65a1dd05948818a4841dfd6e493121d4..ccd491775c2d8eed8ac6b0d2cb7d426f348383b7 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c
@@ -8,16 +8,16 @@ foo (float z, float y, float x)
 }
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
-/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm0, %xmm0" { target { ia32 } } } } */
-/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm1, %xmm1" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler-times "movaps\[ \t\]*%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */
-/* { dg-final { scan-assembler-times "movaps\[ \t\]*%xmm1, %xmm\[0-9\]+" 14 { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" { target { ia32 } } } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */
+/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm1, %xmm\[0-9\]+" 14 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c
index 0eb34e086dbede1c7684989deaa84d61463d8d52..b3570f318c149498e9b03c22dc59d106bdec74bd 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c
@@ -9,6 +9,6 @@ foo (float z, float y, float x)
 }
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
-/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm1, %xmm1" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm1, %xmm2" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c
index 0258c707a8627852b54f6b074b25693a15cfd4d1..b25342065e9b4e4eb8ec00c0dfb8bc6c0046306e 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c
@@ -8,14 +8,14 @@ foo (void)
 
 /* { dg-final { scan-assembler "vzeroall" } } */
 /* { dg-final { scan-assembler-times "fldz" 8 } } */
-/* { dg-final { scan-assembler-times "fstp" 8 } } */
+/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c
index 0625eb534b8a578a006e5064cb96e5294a175c64..69d42d732fdebfbda18f4c30a0eda0addf8d8284 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c
@@ -8,22 +8,22 @@ foo (void)
 
 /* { dg-final { scan-assembler "vzeroall" } } */
 /* { dg-final { scan-assembler-times "fldz" 8 } } */
-/* { dg-final { scan-assembler-times "fstp" 8 } } */
+/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "kxorw\[ \t\]*%k0, %k0, %k0" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k1" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k2" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k3" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k4" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k5" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k6" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k7" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "kxorw\[ \t\]+%k0, %k0, %k0" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k1" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k2" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k3" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k4" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k5" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k6" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k7" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-24.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-24.c
index 208633e8d9dab212f1735911759b39fab600c1e4..5c682879266ed733d67e6ec98774719b43ef5d02 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-24.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-24.c
@@ -7,4 +7,4 @@ foo (int x)
   return x;
 }
 
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-25.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-25.c
index 21e82c6d3c9619b7dddb6f5799c487c602c0bba7..902d3ac1976cd27f95fa8d82d2bd79b5c517134b 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-25.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-25.c
@@ -7,4 +7,4 @@ foo (int x)
   return x;
 }
 
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c
index 293d2fec7f7a6e700f36abd62e4372e932a17d49..8fb5299be567112e8e04c4b9fc1bae46e703d5e5 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target *-*-linux* } } */
-/* { dg-options "-O2 -fzero-call-used-regs=all-arg" } */
+/* { dg-options "-O2 -msse2 -fzero-call-used-regs=all-arg" } */
 
 int 
 foo (int x)
@@ -7,17 +7,17 @@ foo (int x)
   return x;
 }
 
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edx, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %esi" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %edi" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r8d" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r9d" } } */
-/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm0, %xmm0" } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm1" } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm2" } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm3" } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm4" } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm5" } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm6" } } */
-/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm7" } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm1" } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm2" } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm3" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm4" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm5" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm6" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm7" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c
index c34e6af21634e17e92a0efd694ebbf494745eb3f..26ceacf435dbe0e5a5bf7d75198756afa50bc763 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c
@@ -7,9 +7,9 @@ foo (int x)
   return x;
 }
 
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edx, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %esi" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %edi" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r8d" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r9d" } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c
index 48b1f019a28291632d221879d3d70decad6f0bdc..044e4af10f09488f07ef3ce27e8504167e5b69ab 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c
@@ -2,15 +2,17 @@
 /* { dg-options "-O2 -mmmx -fzero-call-used-regs=all" } */
 /* { dg-require-effective-target ia32 } */
 
+typedef int __v2si __attribute__ ((vector_size (8)));
+
 __v2si ret_mmx (void)
 {
   return (__v2si) { 123, 345 };
 }
 
-/* { dg-final { scan-assembler "pxor\[ \t\]*%mm1, %mm1" } } */
-/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm2" } } */
-/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm3" } } */
-/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm4" } } */
-/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm5" } } */
-/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm6" } } */
-/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm7" } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */
+/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */
+/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm3" } } */
+/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm4" } } */
+/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm5" } } */
+/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm6" } } */
+/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm7" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-29.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-29.c
index 8b5e1cd16027a8176de2196333c312c886893355..62706454f6c49c17a2ec51f8b7f884186e5fb9af 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-29.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-29.c
@@ -7,4 +7,4 @@ long double ret_x87 (void)
 }
 
 /* { dg-final { scan-assembler-times "fldz" 7 } } */
-/* { dg-final { scan-assembler-times "fstp" 7 } } */
+/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 7 } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c
index de71223bb58b806741627db5bf8a79f9764a6140..89e69b8ba72b18111f0b562cb1aefa2636477827 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c
@@ -8,5 +8,5 @@ foo (void)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
-/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */
+/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-30.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-30.c
index 2a6f38f366320a9600c243b5a2f8128d88c02b34..c4e99303d22251ef7e30c970db979f58c09bf614 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-30.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-30.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target *-*-linux* } } */
-/* { dg-options "-O2  -fzero-call-used-regs=all" } */
+/* { dg-options "-O2 -fzero-call-used-regs=all" } */
 
 _Complex long double ret_x87_cplx (void)
 {
@@ -7,6 +7,6 @@ _Complex long double ret_x87_cplx (void)
 }
 
 /* { dg-final { scan-assembler-times "fldz" 8 { target ia32 } } } */
-/* { dg-final { scan-assembler-times "fstp" 8 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 { target ia32 } } } */
 /* { dg-final { scan-assembler-times "fldz" 6 { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler-times "fstp" 6 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 6 { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c
index df712860f504a010d83e3429abb280b0e04d5b0a..afa8b337b3696ffb56ad8e4acbd810899c3a12fa 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c
@@ -2,11 +2,13 @@
 /* { dg-options "-O2 -mmmx -fzero-call-used-regs=all-arg" } */
 /* { dg-require-effective-target ia32 } */
 
+typedef int __v2si __attribute__ ((vector_size (8)));
+
 __v2si ret_mmx (void)
 {
   return (__v2si) { 123, 345 };
 }
 
-/* { dg-final { scan-assembler "pxor\[ \t\]*%mm1, %mm1" } } */
-/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm2" } } */
-/* { dg-final { scan-assembler-not "movq\[ \t\]*%mm1, %mm\[34567\]" } } */
+/* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */
+/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */
+/* { dg-final { scan-assembler-not "movq\[ \t\]+%mm1, %mm\[34567\]" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c
index ccfa441bea03f719008df0496ed8c91356f078de..1e98d17df7f84276a7468391e9a2acfb2e623ff4 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c
@@ -10,5 +10,5 @@ foo (void)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
-/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */
+/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c
index 6b46ca39a8d968a210b5b51783880cf6d2d2efd3..56aecdafad8dd1bfec0fb9696f8ff9610fe9e2d1 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c
@@ -9,12 +9,12 @@ foo (void)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c
index 0680f38c68dc490a5a4f356b9aa21998b809d60a..fa831857ad83ec464afed0d605ae9b199aa60ebc 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c
@@ -10,5 +10,5 @@ foo (void)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */
-/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */
+/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c
index 534defae162c3fadec5e4cb3f477966ce0464289..0444a21f4da6740829b781847bbc88d568d6007a 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c
@@ -9,5 +9,5 @@ foo (int x)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" { target ia32 } } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" { target ia32 } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c
index 477bb192d0c1baf5c5aac5912a73da42498bffc8..75356db63c3111c2e6c4e2431e037b9ea24eb2df 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c
@@ -9,11 +9,11 @@ foo (int x)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edx, %edx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %ecx" } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %esi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %edi" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r8d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r9d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r10d" { target { ! ia32 } } } } */
-/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r11d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */

diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c
index a305a60deacd9138165a4f48d6eacfc8102d897f..64755b00c39f727667bdcc9e87d3f9fe35c63442 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c
+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c
@@ -11,5 +11,5 @@ foo (int x)
 
 /* { dg-final { scan-assembler-not "vzeroall" } } */
 /* { dg-final { scan-assembler-not "%xmm" } } */
-/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" { target ia32 } } } */
-/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" { target ia32 } } } */
+/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */