aarch64: Make SME instructions use F_STRICT

This patch makes all SME instructions use F_STRICT, so that qualifiers
have to be provided explicitly rather than being inferred from other
operands.  The main change is to move the qualifier setting from the
operand-level decoders to the opcode level.

This is one step towards consolidating the ZA parsing code and
extending it to handle SME2.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d0a0b629d990526e71a1b27501d264f61ea035b7..691247aa9340b679f7ac80212cfc12ad814c9de4 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -659,7 +659,9 @@ enum aarch64_insn_class
   pcreladdr,
   ic_system,
   sme_misc,
+  sme_mov,
   sme_ldr,
+  sme_psel,
   sme_str,
   sme_start,
   sme_stop,

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index e050197e8be7decda776281ae8aa1ce273b1a12e..bfabcb9e3a2b1e0f3aef6533f57924324b4939b1 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1852,6 +1852,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
   int variant = 0;
   switch (inst->opcode->iclass)
     {
+    case sme_mov:
+    case sme_psel:
+      /* The variant is encoded as part of the immediate.  */
+      break;
+
     case sve_cpy:
       insert_fields (&inst->value, aarch64_get_variant (inst),
                     0, 2, FLD_SVE_M_14, FLD_size);
@@ -1872,8 +1877,9 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
         encoding.  */
       break;
 
+    case sme_misc:
     case sve_misc:
-      /* sve_misc instructions have only a single variant.  */
+      /* These instructions have only a single variant.  */
       break;
 
     case sve_movprfx:

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 02ce8345979db25fb1d6b3265a0c1596e98142cb..01881ea377d97dcba0ea67a80c77033a73e976d5 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1785,44 +1785,35 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
 
   /* Deduce qualifier encoded in size and Q fields.  */
   if (fld_size == 0)
-    info->qualifier = AARCH64_OPND_QLF_S_B;
-  else if (fld_size == 1)
-    info->qualifier = AARCH64_OPND_QLF_S_H;
-  else if (fld_size == 2)
-    info->qualifier = AARCH64_OPND_QLF_S_S;
-  else if (fld_size == 3 && fld_q == 0)
-    info->qualifier = AARCH64_OPND_QLF_S_D;
-  else if (fld_size == 3 && fld_q == 1)
-    info->qualifier = AARCH64_OPND_QLF_S_Q;
-
-  info->za_tile_vector.index.regno = fld_rv + 12;
-  info->za_tile_vector.v = fld_v;
-
-  switch (info->qualifier)
     {
-    case AARCH64_OPND_QLF_S_B:
       info->za_tile_vector.regno = 0;
       info->za_tile_vector.index.imm = fld_zan_imm;
-      break;
-    case AARCH64_OPND_QLF_S_H:
+    }
+  else if (fld_size == 1)
+    {
       info->za_tile_vector.regno = fld_zan_imm >> 3;
       info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
-      break;
-    case AARCH64_OPND_QLF_S_S:
+    }
+  else if (fld_size == 2)
+    {
       info->za_tile_vector.regno = fld_zan_imm >> 2;
       info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
-      break;
-    case AARCH64_OPND_QLF_S_D:
+    }
+  else if (fld_size == 3 && fld_q == 0)
+    {
       info->za_tile_vector.regno = fld_zan_imm >> 1;
       info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
-      break;
-    case AARCH64_OPND_QLF_S_Q:
+    }
+  else if (fld_size == 3 && fld_q == 1)
+    {
       info->za_tile_vector.regno = fld_zan_imm;
       info->za_tile_vector.index.imm = 0;
-      break;
-    default:
-      return false;
     }
+  else
+    return false;
+
+  info->za_tile_vector.index.regno = fld_rv + 12;
+  info->za_tile_vector.v = fld_v;
 
   return true;
 }
@@ -1914,26 +1905,14 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
   info->za_tile_vector.regno = fld_pn;
   info->za_tile_vector.index.regno = fld_rm + 12;
 
-  if (fld_tszh == 0x1 && fld_tszl == 0x0)
-    {
-      info->qualifier = AARCH64_OPND_QLF_S_D;
-      imm = fld_i1;
-    }
-  else if (fld_tszl == 0x4)
-    {
-      info->qualifier = AARCH64_OPND_QLF_S_S;
-      imm = (fld_i1 << 1) | fld_tszh;
-    }
-  else if ((fld_tszl & 0x3) == 0x2)
-    {
-      info->qualifier = AARCH64_OPND_QLF_S_H;
-      imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
-    }
-  else if (fld_tszl & 0x1)
-    {
-      info->qualifier = AARCH64_OPND_QLF_S_B;
-      imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
-    }
+  if (fld_tszl & 0x1)
+    imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
+  else if (fld_tszl & 0x2)
+    imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
+  else if (fld_tszl & 0x4)
+    imm = (fld_i1 << 1) | fld_tszh;
+  else if (fld_tszh)
+    imm = fld_i1;
   else
     return false;
 
@@ -2975,6 +2954,25 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
   variant = 0;
   switch (inst->opcode->iclass)
     {
+    case sme_mov:
+      variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_10);
+      if (variant >= 4 && variant < 7)
+       return false;
+      if (variant == 7)
+       variant = 4;
+      break;
+
+    case sme_psel:
+      i = extract_fields (inst->value, 0, 2, FLD_SME_tszh, FLD_SME_tszl);
+      if (i == 0)
+       return false;
+      while ((i & 1) == 0)
+       {
+         i >>= 1;
+         variant += 1;
+       }
+      break;
+
     case sve_cpy:
       variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
       break;
@@ -3002,8 +3000,9 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
        variant = 3;
       break;
 
+    case sme_misc:
     case sve_misc:
-      /* sve_misc instructions have only a single variant.  */
+      /* These instructions have only a single variant.  */
       break;
 
     case sve_movprfx:

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 96e6c13628211ed60f7f754ed2feba2bbdcefcdd..6c2862eacf35834dec5f188fc453ed8d5d6a5e00 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2650,16 +2650,16 @@ static const aarch64_feature_set aarch64_feature_cssc =
     FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
 #define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \
-    FLAGS, 0, TIED, NULL }
+    F_STRICT | FLAGS, 0, TIED, NULL }
 #define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \
-    FLAGS, 0, TIED, NULL }
+    F_STRICT | FLAGS, 0, TIED, NULL }
 #define SME_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SME_I16I64, OPS, QUALS, \
-    FLAGS, 0, TIED, NULL }
+    F_STRICT | FLAGS, 0, TIED, NULL }
 #define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \
-    FLAGS, CONSTRAINTS, TIED, NULL }
+    F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
 #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
@@ -5238,10 +5238,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
   SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
 
-  SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
-  SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
-  SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
-  SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+  SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+  SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+  SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+  SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
 
   SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0),
 
@@ -5275,7 +5275,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
   SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
   SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-  SME_INSN ("psel", 0x25204000, 0xff20c210, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+  SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
 
   /* SIMD Dot Product (optional in v8.2-A).  */
   DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),