[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Sat, 4 Apr 2020 11:15:47 +0000 (11:15 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sat, 4 Apr 2020 11:15:51 +0000 (12:15 +0100)
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+Date: Sat, 04 Apr 2020 11:15:47 +0000
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-276-13-zs7uEZhNqU@http.bugs.libre-riscv.org/>
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+Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
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