Fix warnings

diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys
index 9891b77d6331d9ff00a46e9396520d81f5b14c85..b8c3eb941390c89302f8e6b032ce22df437bea06 100644 (file)
--- a/tests/arch/ice40/mul.ys
+++ b/tests/arch/ice40/mul.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/mul.v
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_MAC16

diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v
index 0a0f41f3754f832f8c35226428d410c01f2e5813..c4c677c1ee04278a7ae8fc7b2f09b9100ba03642 100644 (file)
--- a/tests/arch/ice40/rom.v
+++ b/tests/arch/ice40/rom.v
@@ -2,7 +2,7 @@
 Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
 */
 module top(data, addr);
-output [3:0] data;
+output reg [3:0] data;
 input [4:0] addr;
 always @(addr) begin
 case (addr)