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diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 141939691bc9aaa9998b21c1984d00655bf2d49c..08da103e7df0e92dce7f21bd38478f3131ca47f3 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -42,7 +42,7 @@ The Mode table for Arithmetic and Logical operations
 | --- | --- |---------|-------------------------- |
 | 00  |   0 |  dz  sz | normal mode                      |
 | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
-| 00  |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
+| 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
 | 00  |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
@@ -56,7 +56,6 @@ Fields:
 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
 than the normal 0..VL-1
-* **CRM** affects the CR on reduce mode when Rc=1
 * **SVM** sets "subvector" reduce mode
 * **N** sets signed/unsigned saturation.
 * **RC1** as if Rc=1, stores CRs *but not the result*