+2004-07-09 Paolo Bonzini <bonzini@gnu.org>
+
+ * config/arc/arc.md: Switch to DFA-based scheduler description.
+ * config/arc/arc.c: Switch to DFA-based scheduler description.
+
2004-07-09 Richard Earnshaw <rearnsha@arm.com>
* arm/unknown-elf.h (TARGET_DEFAULT): Don't require an APCS frame
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR arc_gimplify_va_arg_expr
+#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
/* Called by OVERRIDE_OPTIONS to initialize various things. */
(eq_attr "in_delay_slot" "true")
(eq_attr "in_delay_slot" "true")])
\f
-;; Function units of the ARC
+;; Scheduling description for the ARC
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;; {ready-delay} {issue-delay} [{conflict-list}])
+(define_cpu_unit "branch")
+
+(define_insn_reservation "any_insn" 1 (eq_attr "type" "!load,compare,branch")
+ "nothing")
;; 1) A conditional jump cannot immediately follow the insn setting the flags.
;; This isn't a complete solution as it doesn't come with guarantees. That
;; is done in the branch patterns and in arc_print_operand. This exists to
;; avoid inserting a nop when we can.
-(define_function_unit "compare" 1 0 (eq_attr "type" "compare") 2 2 [(eq_attr "type" "branch")])
+
+(define_insn_reservation "compare" 1 (eq_attr "type" "compare")
+ "nothing,branch")
+
+(define_insn_reservation "branch" 1 (eq_attr "type" "branch")
+ "branch")
;; 2) References to loaded registers should wait a cycle.
;; Memory with load-delay of 1 (i.e., 2 cycle load).
-(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
-;; Units that take one cycle do not need to be specified.
+(define_insn_reservation "memory" 2 (eq_attr "type" "load")
+ "nothing")
\f
;; Move instructions.