env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 16 2011 11:08:03
-gem5 started Nov 17 2011 13:09:16
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
-tests
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_seconds 0.586294 # Number of seconds simulated
sim_ticks 586294224000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 112274 # Simulator instruction rate (inst/s)
-host_tick_rate 40595683 # Simulator tick rate (ticks/s)
-host_mem_usage 244844 # Number of bytes of host memory used
-host_seconds 14442.28 # Real time elapsed on the host
+host_inst_rate 115446 # Simulator instruction rate (inst/s)
+host_tick_rate 41742717 # Simulator tick rate (ticks/s)
+host_mem_usage 244900 # Number of bytes of host memory used
+host_seconds 14045.43 # Real time elapsed on the host
sim_insts 1621493982 # Number of instructions simulated
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1172588449 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 142448983 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 142448983 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 142448982 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 142448982 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 7804844 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 134509889 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 134509888 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 133615988 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 143149229 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1143761055 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 142448983 # Number of branches that fetch encountered
+system.cpu.fetch.Insts 1143761054 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 142448982 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 133615988 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 330199440 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 57554993 # Number of cycles fetch has spent squashing
system.cpu.rename.ROBFullEvents 2634 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 278313629 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 129499394 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2031527324 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 4954653616 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 4954649396 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 2031527322 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 4954653611 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 4954649391 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4220 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 413532674 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 413532672 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 91 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 793190427 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 519090632 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 226808407 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 354951645 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 148937435 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1986583518 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1781630005 # Number of instructions issued
+system.cpu.memDep0.conflictingStores 148937436 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1986583516 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 218 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1781630004 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 180825 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 364939190 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 670712331 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 670712329 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 168 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1172439660 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.519592 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.333662 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 271921708 23.19% 23.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 416937500 35.56% 58.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 271921709 23.19% 23.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 416937499 35.56% 58.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234725234 20.02% 78.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 156776493 13.37% 92.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 54385701 4.64% 96.79% # Number of insts issued each cycle
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 26894248 1.51% 1.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1102052870 61.86% 63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1102052869 61.86% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 194697490 10.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1781630005 # Type of FU issued
+system.cpu.iq.FU_type_0::total 1781630004 # Type of FU issued
system.cpu.iq.rate 1.519399 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2598665 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001459 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4738479065 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 4738479063 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2351732069 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1760053766 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses 1760053765 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 95 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 542 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1757334382 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 1757334381 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 205665909 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.predictedTakenIncorrect 4603219 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3388875 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 7992094 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1768232809 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 1768232808 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 452047218 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 13397196 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_branches 112169596 # Number of branches executed
system.cpu.iew.exec_stores 193872240 # Number of stores executed
system.cpu.iew.exec_rate 1.507974 # Inst execution rate
-system.cpu.iew.wb_sent 1766226830 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1760053778 # cumulative count of insts written-back
+system.cpu.iew.wb_sent 1766226829 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1760053777 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1336567337 # num instructions producing a value
system.cpu.iew.wb_consumers 2003494286 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.ipc 1.382833 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.382833 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3273039620 # number of integer regfile reads
-system.cpu.int_regfile_writes 1756091293 # number of integer regfile writes
+system.cpu.int_regfile_writes 1756091292 # number of integer regfile writes
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
-system.cpu.misc_regfile_reads 908871446 # number of misc regfile reads
+system.cpu.misc_regfile_reads 908871445 # number of misc regfile reads
system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.tagsinuse 810.394392 # Cycle average of tags in use
system.cpu.icache.total_refs 137025977 # Total number of references to valid blocks.
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:22:36
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
---------- Begin Simulation Statistics ----------
-host_inst_rate 3280168 # Simulator instruction rate (inst/s)
-host_mem_usage 202508 # Number of bytes of host memory used
-host_seconds 494.33 # Real time elapsed on the host
-host_tick_rate 1950088412 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1621493983 # Number of instructions simulated
sim_seconds 0.963993 # Number of seconds simulated
sim_ticks 963992704000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1220339 # Simulator instruction rate (inst/s)
+host_tick_rate 725502264 # Simulator tick rate (ticks/s)
+host_mem_usage 234168 # Number of bytes of host memory used
+host_seconds 1328.72 # Real time elapsed on the host
+sim_insts 1621493983 # Number of instructions simulated
+system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1927985409 # Number of busy cycles
-system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 1621493983 # Number of instructions executed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354493 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read
system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
-system.cpu.num_load_insts 419042125 # Number of load instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228182 # number of memory refs
+system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_store_insts 188186057 # Number of store instructions
-system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1927985409 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:23:09
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
---------- Begin Simulation Statistics ----------
-host_inst_rate 2023797 # Simulator instruction rate (inst/s)
-host_mem_usage 210248 # Number of bytes of host memory used
-host_seconds 801.21 # Real time elapsed on the host
-host_tick_rate 2250658484 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1621493983 # Number of instructions simulated
sim_seconds 1.803259 # Number of seconds simulated
sim_ticks 1803258587000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 760773 # Simulator instruction rate (inst/s)
+host_tick_rate 846053445 # Simulator tick rate (ticks/s)
+host_mem_usage 242892 # Number of bytes of host memory used
+host_seconds 2131.38 # Real time elapsed on the host
+sim_insts 1621493983 # Number of instructions simulated
+system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.numCycles 3606517174 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 1621493983 # Number of instructions executed
+system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1621354493 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 607228182 # number of memory refs
+system.cpu.num_load_insts 419042125 # Number of load instructions
+system.cpu.num_store_insts 188186057 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 3606517174 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 4 # number of replacements
+system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use
+system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
+system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 1186516018 # number of overall hits
+system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
+system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 722 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 353302 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 89468 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 71208 # number of replacements
-system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 58007 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 3606517174 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 3606517174 # Number of busy cycles
-system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 1621493983 # Number of instructions executed
-system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
-system.cpu.num_int_insts 1621354493 # number of integer instructions
-system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
-system.cpu.num_load_insts 419042125 # Number of load instructions
-system.cpu.num_mem_refs 607228182 # number of memory refs
-system.cpu.num_store_insts 188186057 # Number of store instructions
-system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
readfile=tests/halt.sh
smbios_table=system.smbios_table
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:24:08
-gem5 started Nov 21 2011 23:30:30
-gem5 executing on u200540-lin
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Jan 9 2012 20:47:38
+gem5 started Jan 9 2012 21:13:16
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5145286546500 because m5_exit instruction encountered
+Exiting @ tick 5161177988500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.145287 # Number of seconds simulated
-sim_ticks 5145286546500 # Number of ticks simulated
+sim_seconds 5.161178 # Number of seconds simulated
+sim_ticks 5161177988500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 333179 # Simulator instruction rate (inst/s)
-host_tick_rate 2041066369 # Simulator tick rate (ticks/s)
-host_mem_usage 358476 # Number of bytes of host memory used
-host_seconds 2520.88 # Real time elapsed on the host
-sim_insts 839904894 # Number of instructions simulated
-system.l2c.replacements 171120 # number of replacements
-system.l2c.tagsinuse 38411.926866 # Cycle average of tags in use
-system.l2c.total_refs 3818646 # Total number of references to valid blocks.
-system.l2c.sampled_refs 206013 # Sample count of references to valid blocks.
-system.l2c.avg_refs 18.535947 # Average number of references to valid blocks.
+host_inst_rate 384526 # Simulator instruction rate (inst/s)
+host_tick_rate 2360358751 # Simulator tick rate (ticks/s)
+host_mem_usage 386468 # Number of bytes of host memory used
+host_seconds 2186.61 # Real time elapsed on the host
+sim_insts 840808469 # Number of instructions simulated
+system.l2c.replacements 169467 # number of replacements
+system.l2c.tagsinuse 38339.786444 # Cycle average of tags in use
+system.l2c.total_refs 3812924 # Total number of references to valid blocks.
+system.l2c.sampled_refs 204660 # Sample count of references to valid blocks.
+system.l2c.avg_refs 18.630529 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 11983.527500 # Average occupied blocks per context
-system.l2c.occ_blocks::1 26428.399366 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.182854 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.403265 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 2330328 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 145914 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2476242 # number of ReadReq hits
-system.l2c.Writeback_hits::0 1599020 # number of Writeback hits
-system.l2c.Writeback_hits::total 1599020 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 343 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 343 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 150210 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 150210 # number of ReadExReq hits
-system.l2c.demand_hits::0 2480538 # number of demand (read+write) hits
-system.l2c.demand_hits::1 145914 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2626452 # number of demand (read+write) hits
-system.l2c.overall_hits::0 2480538 # number of overall hits
-system.l2c.overall_hits::1 145914 # number of overall hits
-system.l2c.overall_hits::total 2626452 # number of overall hits
-system.l2c.ReadReq_misses::0 68080 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 84 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 68164 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 3905 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3905 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 142426 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 142426 # number of ReadExReq misses
-system.l2c.demand_misses::0 210506 # number of demand (read+write) misses
-system.l2c.demand_misses::1 84 # number of demand (read+write) misses
-system.l2c.demand_misses::total 210590 # number of demand (read+write) misses
-system.l2c.overall_misses::0 210506 # number of overall misses
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-system.l2c.overall_misses::total 210590 # number of overall misses
-system.l2c.ReadReq_miss_latency 3574844000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 37228000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 7453066500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 11027910500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 11027910500 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2398408 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 145998 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2544406 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 1599020 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1599020 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 4248 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 4248 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 292636 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 292636 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2691044 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 145998 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2837042 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2691044 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 145998 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2837042 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.028385 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.000575 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.028961 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.919256 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.486700 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.078225 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.000575 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.078800 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.078225 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.000575 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.078800 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52509.459459 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 42557666.666667 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 42610176.126126 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 9533.418694 # average UpgradeReq miss latency
+system.l2c.occ_blocks::0 11950.408174 # Average occupied blocks per context
+system.l2c.occ_blocks::1 26389.378270 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.182349 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.402670 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 2335607 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 145488 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 2481095 # number of ReadReq hits
+system.l2c.Writeback_hits::0 1594493 # number of Writeback hits
+system.l2c.Writeback_hits::total 1594493 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 327 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 327 # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0 150672 # number of ReadExReq hits
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+system.l2c.overall_hits::total 2631767 # number of overall hits
+system.l2c.ReadReq_misses::0 66850 # number of ReadReq misses
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+system.l2c.ReadReq_misses::total 66959 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 3932 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 3932 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0 142221 # number of ReadExReq misses
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+system.l2c.demand_misses::0 209071 # number of demand (read+write) misses
+system.l2c.demand_misses::1 109 # number of demand (read+write) misses
+system.l2c.demand_misses::total 209180 # number of demand (read+write) misses
+system.l2c.overall_misses::0 209071 # number of overall misses
+system.l2c.overall_misses::1 109 # number of overall misses
+system.l2c.overall_misses::total 209180 # number of overall misses
+system.l2c.ReadReq_miss_latency 3511861000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency 38996000 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency 7442399000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency 10954260000 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 10954260000 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 2402457 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 145597 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2548054 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 1594493 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1594493 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 4259 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 4259 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 292893 # number of ReadExReq accesses(hits+misses)
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+system.l2c.ReadReq_miss_rate::0 0.027826 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.000749 # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_miss_rate::0 0.923221 # miss rate for UpgradeReq accesses
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+system.l2c.overall_miss_rate::total 0.078316 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0 52533.448018 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 32218908.256881 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 32271441.704899 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 9917.599186 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52329.395616 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52329.817678 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 52387.630281 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 131284648.809524 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 131337036.439805 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 52387.630281 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 131284648.809524 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 131337036.439805 # average overall miss latency
+system.l2c.demand_avg_miss_latency::0 52394.928039 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 100497798.165138 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 100550193.093176 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 52394.928039 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 100497798.165138 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 100550193.093176 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 142550 # number of writebacks
+system.l2c.writebacks 142631 # number of writebacks
system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits 2 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 68162 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 3905 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 142426 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 210588 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 210588 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_misses 66957 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 3932 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses 142221 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses 209178 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 209178 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 2743592500 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 156565000 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 5717024500 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 8460617000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 8460617000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 61532546500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 1222452000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 62754998500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.028420 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 0.466869 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.495289 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.919256 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_latency 2695362500 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency 157637000 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5708607000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 8403969500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 8403969500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency 59978490000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 1230737500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 61209227500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.027870 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.459879 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.487749 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.923221 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 0.486700 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 0.485573 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.078255 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.442403 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 1.520658 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.078255 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 1.442403 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 1.520658 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40251.056307 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.469910 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40140.314971 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency
+system.l2c.demand_mshr_miss_rate::0 0.077607 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 1.436692 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 1.514299 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0.077607 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 1.436692 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 1.514299 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40255.126424 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40090.793489 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40138.987913 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency 40176.163363 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40176.163363 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 47572 # number of replacements
-system.iocache.tagsinuse 0.146650 # Cycle average of tags in use
+system.iocache.replacements 47573 # number of replacements
+system.iocache.tagsinuse 0.195398 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47588 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47589 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4994510051000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 0.146650 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.009166 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 4994542788000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1 0.195398 # Average occupied blocks per context
+system.iocache.occ_percent::1 0.012212 # Average percentage of cache occupancy
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
system.iocache.overall_misses::0 0 # number of overall misses
system.iocache.overall_misses::1 47627 # number of overall misses
system.iocache.overall_misses::total 47627 # number of overall misses
-system.iocache.ReadReq_miss_latency 113785932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency 6369912160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency 6483698092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 6483698092 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency 113669932 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency 6372391160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency 6486061092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 6486061092 # number of overall miss cycles
system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 125453.067255 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 125325.173098 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136342.297945 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 136395.358733 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136134.925399 # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 136184.540114 # average overall miss latency
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136134.925399 # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 136184.540114 # average overall miss latency
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 68669502 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs 68679532 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 11260 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 11251 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6098.534813 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6104.304684 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 46667 # number of writebacks
+system.iocache.writebacks 46668 # number of writebacks
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses 47627 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses 47627 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency 66598982 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency 3940155856 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency 4006754838 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 4006754838 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency 66482982 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency 3942637876 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency 4009120858 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 4009120858 # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 73427.764057 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84335.527740 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 73299.869901 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 84388.653168 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 84177.480379 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 84177.480379 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 449021643 # number of cpu cycles simulated
+system.cpu.numCycles 449878562 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 91138491 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 91138491 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1248082 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 89857544 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 83686998 # Number of BTB hits
+system.cpu.BPredUnit.lookups 91189820 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 91189820 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1250253 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 90006318 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 83822675 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 28288670 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 450771327 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 91138491 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 83686998 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 171087914 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6045536 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 191873 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 82674920 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 36392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 54951 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9822160 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 542562 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4016 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 287044907 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.085924 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.403637 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28390554 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 451032028 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 91189820 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 83822675 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 171638033 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6092005 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 127923 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 86885537 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 36685 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 38090 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9866979 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 541048 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3553 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 291873782 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.039474 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.398963 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 116472661 40.58% 40.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1490084 0.52% 41.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72800190 25.36% 66.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1427390 0.50% 66.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1806479 0.63% 67.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3992507 1.39% 68.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1571582 0.55% 69.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2063795 0.72% 70.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 85420219 29.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 120818032 41.39% 41.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1855546 0.64% 42.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72826244 24.95% 66.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1422491 0.49% 67.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1829890 0.63% 68.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4020066 1.38% 69.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1590838 0.55% 70.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1683069 0.58% 70.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 85827606 29.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 287044907 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.202971 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.003897 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 33370892 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 79040686 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 165533455 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4389968 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4709906 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 881886507 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 578 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4709906 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37547254 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 52554502 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10077381 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 165462513 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 16693351 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 877383155 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 14371 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 11668719 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2142745 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 879650717 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1723132927 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1723132383 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 544 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 843287047 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36363663 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 486686 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 487762 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 43318784 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 19666821 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10717044 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1121000 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1013044 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 870450598 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 900193 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 866206507 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 178001 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 30597956 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 44655599 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 144106 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 287044907 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.017669 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.373774 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 291873782 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.202699 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.002564 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 33589176 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 83124342 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 166020087 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4383500 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4756677 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 883216023 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 571 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4756677 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37852860 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 55892656 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9911063 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 165583689 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 17876837 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 878703692 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 12652 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 12602978 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 2126989 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 880098416 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1724229495 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1724229039 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 843418783 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 36679626 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 488930 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 489908 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 44000804 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19727758 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10753359 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1338256 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1089668 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 870922009 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1727938 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 867227375 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 177419 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 30993538 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 45221667 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 207753 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 291873782 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.971241 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.381572 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 82633676 28.79% 28.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 22379993 7.80% 36.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 14042555 4.89% 41.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 9676323 3.37% 44.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 79535811 27.71% 72.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 5032653 1.75% 74.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72954170 25.42% 99.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 636902 0.22% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 152824 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 86148709 29.52% 29.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 24105973 8.26% 37.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 13574297 4.65% 42.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 9676822 3.32% 45.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 79595279 27.27% 73.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 5022101 1.72% 74.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72958833 25.00% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 636421 0.22% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 155347 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 287044907 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 291873782 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 195893 8.77% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1841396 82.43% 91.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 196729 8.81% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 202428 8.97% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1851752 82.02% 90.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 203495 9.01% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 302784 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 830728417 95.90% 95.94% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 306567 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 831752185 95.91% 95.94% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.94% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25630184 2.96% 98.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9545122 1.10% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25621043 2.95% 98.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9547580 1.10% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 866206507 # Type of FU issued
-system.cpu.iq.rate 1.929097 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2234018 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.002579 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2022023513 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 901959019 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 855369267 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 868137651 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1362479 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 867227375 # Type of FU issued
+system.cpu.iq.rate 1.927692 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2257675 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.002603 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2028918942 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 903653765 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 856397776 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 869178395 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1343949 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4321864 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 17926 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11344 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2286443 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4393917 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 17180 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11337 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2321478 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 7817280 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 160300 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 7817249 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 160526 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4709906 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 33528904 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6021560 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 871350791 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 302780 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 19666821 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10717077 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 894230 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 5567968 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 26441 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11344 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 900317 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 526461 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1426778 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 864071451 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25139822 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2135055 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4756677 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 34884624 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 6122535 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 872649947 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 301193 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19727758 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10753386 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 894363 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 5389997 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 26295 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11337 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 906001 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 524480 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1430481 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 865094857 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25131798 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2132517 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 34444060 # number of memory reference insts executed
-system.cpu.iew.exec_branches 86704764 # Number of branches executed
-system.cpu.iew.exec_stores 9304238 # Number of stores executed
-system.cpu.iew.exec_rate 1.924343 # Inst execution rate
-system.cpu.iew.wb_sent 863434483 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 855369319 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 671433691 # num instructions producing a value
-system.cpu.iew.wb_consumers 1171953644 # num instructions consuming a value
+system.cpu.iew.exec_refs 34436194 # number of memory reference insts executed
+system.cpu.iew.exec_branches 86723634 # Number of branches executed
+system.cpu.iew.exec_stores 9304396 # Number of stores executed
+system.cpu.iew.exec_rate 1.922952 # Inst execution rate
+system.cpu.iew.wb_sent 864455877 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 856397826 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 671292665 # num instructions producing a value
+system.cpu.iew.wb_consumers 1171999804 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.904962 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.572918 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.903620 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.572775 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 839904894 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 31338704 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 756085 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1254700 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 282350978 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.974684 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.863709 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 840808469 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 31735206 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1520183 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1254406 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 287133088 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.928288 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.869814 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 102836465 36.42% 36.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 12523164 4.44% 40.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4697520 1.66% 42.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 76975529 27.26% 69.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4042949 1.43% 71.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1857352 0.66% 71.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1067382 0.38% 72.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 71607681 25.36% 97.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6742936 2.39% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 107529680 37.45% 37.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13316862 4.64% 42.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3946452 1.37% 43.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 76651474 26.70% 70.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4051645 1.41% 71.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1852261 0.65% 72.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1054561 0.37% 72.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71992194 25.07% 97.65% # Number of insts commited each cycle
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 22302306 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.179407 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.222516 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.195685 # miss rate for demand accesses
+system.cpu.dcache.overall_accesses::total 22328067 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.179234 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.222664 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.195616 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.195685 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0 0.195616 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15097.817532 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15062.981576 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 33871.585154 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 33834.435792 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 23158.772790 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 23122.976863 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 23158.772790 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 23122.976863 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 1083244649 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 6672500 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 73213 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 1083233153 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 6672000 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 73547 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 14795.796498 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 17065.217391 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 14728.447836 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 17063.938619 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 1547981 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 1120147 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 1577106 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 2697253 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 2697253 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 1370199 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 296778 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 1666977 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 1666977 # number of overall MSHR misses
+system.cpu.dcache.writebacks 1548983 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 1121085 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 1578340 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 2699425 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 2699425 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 1371255 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 297058 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 1668313 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 1668313 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 18186929000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 9757421649 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 27944350649 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 27944350649 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947016500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1386048000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 88333064500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098711 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency 18154950000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 9754920653 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 27909870653 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 27909870653 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85210888500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1394917000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 86605805500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098612 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035241 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.074745 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::0 0.074718 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.074745 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::0 0.074718 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13273.202652 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32877.846906 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13239.660019 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32838.437790 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 16729.397093 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 16729.397093 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
Initializing CPU#0\r
PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 2000.004 MHz processor.\r
+time.c: Detected 2000.000 MHz processor.\r
Console: colour dummy device 80x25\r
console handover: boot [earlyser0] -> real [ttyS0]\r
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
ACPI: Unable to load the System Description Tables\r
Using local APIC timer interrupts.\r
-result 7812511\r
+result 7812497\r
Detected 7.812 MHz APIC timer.\r
NET: Registered protocol family 16\r
PCI: Using configuration type 1\r
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 16 2011 11:08:03
-gem5 started Nov 17 2011 13:09:16
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
-tests
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_seconds 0.070313 # Number of seconds simulated
sim_ticks 70312944500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125815 # Simulator instruction rate (inst/s)
-host_tick_rate 31799589 # Simulator tick rate (ticks/s)
-host_mem_usage 378944 # Number of bytes of host memory used
-host_seconds 2211.13 # Real time elapsed on the host
+host_inst_rate 109444 # Simulator instruction rate (inst/s)
+host_tick_rate 27661822 # Simulator tick rate (ticks/s)
+host_mem_usage 378996 # Number of bytes of host memory used
+host_seconds 2541.88 # Real time elapsed on the host
sim_insts 278192519 # Number of instructions simulated
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 140625890 # number of cpu cycles simulated
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:39:34
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 3107267 # Simulator instruction rate (inst/s)
-host_mem_usage 337076 # Number of bytes of host memory used
-host_seconds 89.53 # Real time elapsed on the host
-host_tick_rate 1887081425 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.168950 # Number of seconds simulated
sim_ticks 168950072000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1147935 # Simulator instruction rate (inst/s)
+host_tick_rate 697156581 # Simulator tick rate (ticks/s)
+host_mem_usage 368676 # Number of bytes of host memory used
+host_seconds 242.34 # Real time elapsed on the host
+sim_insts 278192520 # Number of instructions simulated
+system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900145 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 337900145 # Number of busy cycles
-system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
-system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 278192520 # Number of instructions executed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186228 # number of integer instructions
+system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
-system.cpu.num_load_insts 90779388 # Number of load instructions
+system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_mem_refs 122219139 # number of memory refs
+system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
-system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 337900145 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:41:14
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1776708 # Simulator instruction rate (inst/s)
-host_mem_usage 344820 # Number of bytes of host memory used
-host_seconds 156.58 # Real time elapsed on the host
-host_tick_rate 2363113199 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.370011 # Number of seconds simulated
sim_ticks 370010840000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 588786 # Simulator instruction rate (inst/s)
+host_tick_rate 783116445 # Simulator tick rate (ticks/s)
+host_mem_usage 377276 # Number of bytes of host memory used
+host_seconds 472.49 # Real time elapsed on the host
+sim_insts 278192520 # Number of instructions simulated
+system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.numCycles 740021680 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 278192520 # Number of instructions executed
+system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
+system.cpu.num_int_insts 278186228 # number of integer instructions
+system.cpu.num_fp_insts 40 # number of float instructions
+system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
+system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
+system.cpu.num_mem_refs 122219139 # number of memory refs
+system.cpu.num_load_insts 90779388 # Number of load instructions
+system.cpu.num_store_insts 31439751 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 740021680 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 24 # number of replacements
+system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
+system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
+system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 217695401 # number of overall hits
+system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
+system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 808 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits
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system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1991062 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 76575 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 49212 # number of replacements
-system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 29460 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 740021680 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 740021680 # Number of busy cycles
-system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
-system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 278192520 # Number of instructions executed
-system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
-system.cpu.num_int_insts 278186228 # number of integer instructions
-system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
-system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
-system.cpu.num_load_insts 90779388 # Number of load instructions
-system.cpu.num_mem_refs 122219139 # number of memory refs
-system.cpu.num_store_insts 31439751 # Number of store instructions
-system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 16 2011 11:08:03
-gem5 started Nov 17 2011 13:09:16
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
-tests
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 494093841000 because target called exit()
+Exiting @ tick 493912286000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.494094 # Number of seconds simulated
-sim_ticks 494093841000 # Number of ticks simulated
+sim_seconds 0.493912 # Number of seconds simulated
+sim_ticks 493912286000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 111156 # Simulator instruction rate (inst/s)
-host_tick_rate 35920075 # Simulator tick rate (ticks/s)
-host_mem_usage 281020 # Number of bytes of host memory used
-host_seconds 13755.37 # Real time elapsed on the host
+host_inst_rate 108889 # Simulator instruction rate (inst/s)
+host_tick_rate 35174673 # Simulator tick rate (ticks/s)
+host_mem_usage 280548 # Number of bytes of host memory used
+host_seconds 14041.70 # Real time elapsed on the host
sim_insts 1528988756 # Number of instructions simulated
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 988187683 # number of cpu cycles simulated
+system.cpu.numCycles 987824573 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits
+system.cpu.BPredUnit.lookups 245766486 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 245766486 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 16576996 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 236474058 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 218464201 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 205503020 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1343384866 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 245766486 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 218464201 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 436676837 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 119986236 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 218554807 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 341323 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 194710374 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 4099618 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 964252463 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.599701 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.317490 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 531629837 55.13% 55.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 32377332 3.36% 58.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 38827894 4.03% 62.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 32536894 3.37% 65.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 21844251 2.27% 68.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 36448993 3.78% 71.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 49128972 5.10% 77.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 36937786 3.83% 80.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 184520504 19.14% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 964252463 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.248796 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.359943 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 264509435 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 174554141 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 373011587 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 49033211 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 103144089 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2445932072 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 103144089 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 301738657 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 40282868 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 12225 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 383467875 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 135606749 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2393375507 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 2559 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 25131978 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 92224846 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2227188673 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5629907069 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5629667957 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 239112 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 799889646 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1309 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1288 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 318947403 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 577879232 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 226530900 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 227222440 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 65937432 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2286709085 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 12489 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1922370305 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1306641 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 755226802 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1190125426 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 11936 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 964252463 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.993638 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.811521 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 282911384 29.34% 29.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 160280603 16.62% 45.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 162550496 16.86% 62.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 148847741 15.44% 78.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 109081156 11.31% 89.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 60080329 6.23% 95.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 30822605 3.20% 99.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 8641604 0.90% 99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1036545 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 964252463 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2246339 14.60% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 10026447 65.19% 79.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3108042 20.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2420122 0.13% 0.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1274712167 66.31% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 463703127 24.12% 90.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 181534884 9.44% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued
-system.cpu.iq.rate 1.945459 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1922370305 # Type of FU issued
+system.cpu.iq.rate 1.946064 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 15380828 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008001 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4825675637 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3042139517 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1874661917 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 4905 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 81824 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 136 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1935329448 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1563 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 158391521 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 193777072 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 372742 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 283642 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 77371112 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2379 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 103144089 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 9045659 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1404502 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2286721574 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1118432 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 577879232 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 226531297 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 6081 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1006586 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 29974 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 283642 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 15693422 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 2344063 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18037485 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1889150749 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 454748002 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 33219556 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed
-system.cpu.iew.exec_branches 176731992 # Number of branches executed
-system.cpu.iew.exec_stores 174531259 # Number of stores executed
-system.cpu.iew.exec_rate 1.911862 # Inst execution rate
-system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1440755706 # num instructions producing a value
-system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value
+system.cpu.iew.exec_refs 629271939 # number of memory reference insts executed
+system.cpu.iew.exec_branches 176719729 # Number of branches executed
+system.cpu.iew.exec_stores 174523937 # Number of stores executed
+system.cpu.iew.exec_rate 1.912435 # Inst execution rate
+system.cpu.iew.wb_sent 1882531239 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1874662053 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1440606287 # num instructions producing a value
+system.cpu.iew.wb_consumers 2134778201 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.897768 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.674827 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 757743569 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16604349 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 861108374 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.775605 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.288022 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 338327816 39.29% 39.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 210551706 24.45% 63.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 75360819 8.75% 72.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 92562974 10.75% 83.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 34054041 3.95% 87.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 27955182 3.25% 90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 16032820 1.86% 92.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 12266632 1.42% 93.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 53996384 6.27% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 861108374 # Number of insts commited each cycle
system.cpu.commit.count 1528988756 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 533262345 # Number of memory references committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 53996384 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3094435758 # The number of ROB reads
-system.cpu.rob.rob_writes 4677260376 # The number of ROB writes
-system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3093844315 # The number of ROB reads
+system.cpu.rob.rob_writes 4676786954 # The number of ROB writes
+system.cpu.timesIdled 606516 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 23572110 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
-system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads
-system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes
-system.cpu.fp_regfile_reads 109 # number of floating regfile reads
-system.cpu.fp_regfile_writes 3 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads
-system.cpu.icache.replacements 9996 # number of replacements
-system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use
-system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks.
+system.cpu.cpi 0.646064 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.646064 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.547834 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.547834 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3179044858 # number of integer regfile reads
+system.cpu.int_regfile_writes 1744829680 # number of integer regfile writes
+system.cpu.fp_regfile_reads 145 # number of floating regfile reads
+system.cpu.fp_regfile_writes 5 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1039286160 # number of misc regfile reads
+system.cpu.icache.replacements 10045 # number of replacements
+system.cpu.icache.tagsinuse 976.337758 # Cycle average of tags in use
+system.cpu.icache.total_refs 194480398 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 11548 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 16841.045895 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits
-system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 194495909 # number of overall hits
-system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses
-system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 223856 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency
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+system.cpu.l2cache.demand_mshr_misses 585763 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 585763 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 10503665500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6475353000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666739500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 18170405000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 18170405000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191102 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994098 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320331 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.230303 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.230303 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.859071 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.943143 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.341733 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:30:34
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 3416660 # Simulator instruction rate (inst/s)
-host_mem_usage 206360 # Number of bytes of host memory used
-host_seconds 447.51 # Real time elapsed on the host
-host_tick_rate 1978121798 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1528988757 # Number of instructions simulated
sim_seconds 0.885229 # Number of seconds simulated
sim_ticks 885229360000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1063398 # Simulator instruction rate (inst/s)
+host_tick_rate 615669149 # Simulator tick rate (ticks/s)
+host_mem_usage 237896 # Number of bytes of host memory used
+host_seconds 1437.83 # Real time elapsed on the host
+sim_insts 1528988757 # Number of instructions simulated
+system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1770458721 # Number of busy cycles
-system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 1528988757 # Number of instructions executed
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317615 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read
system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
-system.cpu.num_load_insts 384102160 # Number of load instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 533262345 # number of memory refs
+system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_store_insts 149160185 # Number of store instructions
-system.cpu.workload.num_syscalls 551 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1770458721 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:27:05
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2070048 # Simulator instruction rate (inst/s)
-host_mem_usage 214112 # Number of bytes of host memory used
-host_seconds 738.62 # Real time elapsed on the host
-host_tick_rate 2245699490 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1528988757 # Number of instructions simulated
sim_seconds 1.658730 # Number of seconds simulated
sim_ticks 1658729604000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 746220 # Simulator instruction rate (inst/s)
+host_tick_rate 809539282 # Simulator tick rate (ticks/s)
+host_mem_usage 246668 # Number of bytes of host memory used
+host_seconds 2048.98 # Real time elapsed on the host
+sim_insts 1528988757 # Number of instructions simulated
+system.cpu.workload.num_syscalls 551 # Number of system calls
+system.cpu.numCycles 3317459208 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 1528988757 # Number of instructions executed
+system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1528317615 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 533262345 # number of memory refs
+system.cpu.num_load_insts 384102160 # Number of load instructions
+system.cpu.num_store_insts 149160185 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 3317459208 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 1253 # number of replacements
+system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use
+system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits
+system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 1068344296 # number of overall hits
+system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
+system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 2814 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2514362 # number of replacements
+system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
+system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits
+system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 530743932 # number of overall hits
+system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses
+system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 2518458 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 530743932 # number of overall hits
-system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2518458 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 2514362 # number of replacements
-system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
-system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2223170 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
-system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1068344296 # number of overall hits
-system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
-system.cpu.icache.overall_misses 2814 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 1253 # number of replacements
-system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use
-system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 568906 # number of replacements
+system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 543011 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 1941663 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 248033 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 579609 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 411709 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1941663 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 579609 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 568906 # number of replacements
-system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 411709 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 3317459208 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 3317459208 # Number of busy cycles
-system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 1528988757 # Number of instructions executed
-system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
-system.cpu.num_int_insts 1528317615 # number of integer instructions
-system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
-system.cpu.num_load_insts 384102160 # Number of load instructions
-system.cpu.num_mem_refs 533262345 # number of memory refs
-system.cpu.num_store_insts 149160185 # Number of store instructions
-system.cpu.workload.num_syscalls 551 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:22:46
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
---------- Begin Simulation Statistics ----------
-host_inst_rate 2952357 # Simulator instruction rate (inst/s)
-host_mem_usage 202444 # Number of bytes of host memory used
-host_seconds 1587.50 # Real time elapsed on the host
-host_tick_rate 1792761763 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 4686862651 # Number of instructions simulated
sim_seconds 2.846007 # Number of seconds simulated
sim_ticks 2846007259500 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1508697 # Simulator instruction rate (inst/s)
+host_tick_rate 916127309 # Simulator tick rate (ticks/s)
+host_mem_usage 234076 # Number of bytes of host memory used
+host_seconds 3106.56 # Real time elapsed on the host
+sim_insts 4686862651 # Number of instructions simulated
+system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 5692014520 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 5692014520 # Number of busy cycles
-system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 4686862651 # Number of instructions executed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862580 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
-system.cpu.num_load_insts 1239184749 # Number of load instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1677713086 # number of memory refs
+system.cpu.num_load_insts 1239184749 # Number of load instructions
system.cpu.num_store_insts 438528337 # Number of store instructions
-system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 5692014520 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:36:40
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
---------- Begin Simulation Statistics ----------
-host_inst_rate 1878760 # Simulator instruction rate (inst/s)
-host_mem_usage 210192 # Number of bytes of host memory used
-host_seconds 2494.66 # Real time elapsed on the host
-host_tick_rate 2374493636 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 4686862651 # Number of instructions simulated
sim_seconds 5.923548 # Number of seconds simulated
sim_ticks 5923548078000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 871353 # Simulator instruction rate (inst/s)
+host_tick_rate 1101269643 # Simulator tick rate (ticks/s)
+host_mem_usage 242804 # Number of bytes of host memory used
+host_seconds 5378.84 # Real time elapsed on the host
+sim_insts 4686862651 # Number of instructions simulated
+system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.numCycles 11847096156 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 4686862651 # Number of instructions executed
+system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4686862580 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 1677713086 # number of memory refs
+system.cpu.num_load_insts 1239184749 # Number of load instructions
+system.cpu.num_store_insts 438528337 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 11847096156 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 10 # number of replacements
+system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use
+system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits
+system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 4013232252 # number of overall hits
+system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
+system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 675 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9108581 # number of replacements
+system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits
+system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 1668600409 # number of overall hits
+system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses
+system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 9112677 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses
+system.cpu.dcache.writebacks 3053391 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency
+system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1668600409 # number of overall hits
-system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9112677 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 9108581 # number of replacements
-system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 3053391 # number of writebacks
-system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 4013232252 # number of overall hits
-system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.overall_misses 675 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 10 # number of replacements
-system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use
-system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 2706631 # number of replacements
+system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 6396007 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 2717345 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 1174631 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 6396007 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2717345 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 2706631 # number of replacements
-system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1174631 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 11847096156 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 11847096156 # Number of busy cycles
-system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 4686862651 # Number of instructions executed
-system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
-system.cpu.num_int_insts 4686862580 # number of integer instructions
-system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
-system.cpu.num_load_insts 1239184749 # Number of load instructions
-system.cpu.num_mem_refs 1677713086 # number of memory refs
-system.cpu.num_store_insts 438528337 # Number of store instructions
-system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 16 2011 11:08:03
-gem5 started Nov 17 2011 13:09:16
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
-tests
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_seconds 0.096690 # Number of seconds simulated
sim_ticks 96689893000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 89575 # Simulator instruction rate (inst/s)
-host_tick_rate 39125952 # Simulator tick rate (ticks/s)
-host_mem_usage 253168 # Number of bytes of host memory used
-host_seconds 2471.25 # Real time elapsed on the host
+host_inst_rate 71082 # Simulator instruction rate (inst/s)
+host_tick_rate 31048201 # Simulator tick rate (ticks/s)
+host_mem_usage 253148 # Number of bytes of host memory used
+host_seconds 3114.19 # Real time elapsed on the host
sim_insts 221363017 # Number of instructions simulated
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 193379787 # number of cpu cycles simulated
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:38:23
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 3098099 # Simulator instruction rate (inst/s)
-host_mem_usage 209904 # Number of bytes of host memory used
-host_seconds 71.45 # Real time elapsed on the host
-host_tick_rate 1838915708 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 221363018 # Number of instructions simulated
sim_seconds 0.131393 # Number of seconds simulated
sim_ticks 131393100000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 733183 # Simulator instruction rate (inst/s)
+host_tick_rate 435191133 # Simulator tick rate (ticks/s)
+host_mem_usage 241232 # Number of bytes of host memory used
+host_seconds 301.92 # Real time elapsed on the host
+sim_insts 221363018 # Number of instructions simulated
+system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 262786201 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 262786201 # Number of busy cycles
-system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
-system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 221363018 # Number of instructions executed
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339607 # number of integer instructions
+system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
-system.cpu.num_load_insts 56649590 # Number of load instructions
+system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_mem_refs 77165306 # number of memory refs
+system.cpu.num_load_insts 56649590 # Number of load instructions
system.cpu.num_store_insts 20515716 # Number of store instructions
-system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 262786201 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:30:33
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1944621 # Simulator instruction rate (inst/s)
-host_mem_usage 217656 # Number of bytes of host memory used
-host_seconds 113.83 # Real time elapsed on the host
-host_tick_rate 2204625935 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 221363018 # Number of instructions simulated
sim_seconds 0.250961 # Number of seconds simulated
sim_ticks 250960631000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 461238 # Simulator instruction rate (inst/s)
+host_tick_rate 522908265 # Simulator tick rate (ticks/s)
+host_mem_usage 250008 # Number of bytes of host memory used
+host_seconds 479.93 # Real time elapsed on the host
+sim_insts 221363018 # Number of instructions simulated
+system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.numCycles 501921262 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 221363018 # Number of instructions executed
+system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
+system.cpu.num_int_insts 220339607 # number of integer instructions
+system.cpu.num_fp_insts 2162459 # number of float instructions
+system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
+system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
+system.cpu.num_mem_refs 77165306 # number of memory refs
+system.cpu.num_load_insts 56649590 # Number of load instructions
+system.cpu.num_store_insts 20515716 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 501921262 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 2836 # number of replacements
+system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use
+system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
+system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 173489718 # number of overall hits
+system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
+system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 4694 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 41 # number of replacements
+system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use
+system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits
+system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 77195833 # number of overall hits
+system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses
+system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 1905 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses
+system.cpu.dcache.writebacks 7 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 77195833 # number of overall hits
-system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1905 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 41 # number of replacements
-system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use
-system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 7 # number of writebacks
-system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
-system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
-system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 173489718 # number of overall hits
-system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
-system.cpu.icache.overall_misses 4694 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 2836 # number of replacements
-system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use
-system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 1864 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 4735 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1864 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4735 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 501921262 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 501921262 # Number of busy cycles
-system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
-system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 221363018 # Number of instructions executed
-system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
-system.cpu.num_int_insts 220339607 # number of integer instructions
-system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
-system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
-system.cpu.num_load_insts 56649590 # Number of load instructions
-system.cpu.num_mem_refs 77165306 # number of memory refs
-system.cpu.num_store_insts 20515716 # Number of store instructions
-system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 13:24:14
-gem5 started Aug 20 2011 13:24:28
-gem5 executing on zizzer
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:28:31
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 11087000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 51481 # Simulator instruction rate (inst/s)
-host_tick_rate 58182623 # Simulator tick rate (ticks/s)
-host_mem_usage 209228 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 74834 # Simulator instruction rate (inst/s)
+host_tick_rate 84571612 # Simulator tick rate (ticks/s)
+host_mem_usage 239776 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 9809 # Number of instructions simulated
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 22175 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 3057 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3057 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 3056 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3056 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2732 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 2731 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 995 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 5895 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14000 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3057 # Number of branches that fetch encountered
+system.cpu.fetch.Insts 13997 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3056 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2221 # Number of cycles fetch has spent squashing
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 13088 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.137858 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.631342 # Number of inst fetches per cycle
+system.cpu.fetch.branchRate 0.137813 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.631206 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3565 # Number of cycles decode is running
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 272 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 21252 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 47663 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 47647 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 21246 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 47645 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 47629 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 11884 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 11878 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 1613 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2239 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1783 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads 2238 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1782 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 20542 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 16960 # Number of instructions issued
+system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 20539 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 16958 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 12997 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 12992 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.295844 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.003369 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.295691 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.003315 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1107 8.46% 69.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1108 8.47% 69.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1006 7.69% 77.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 734 5.61% 82.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 13642 80.44% 80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1844 10.87% 91.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1843 10.87% 91.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 16960 # Type of FU issued
-system.cpu.iq.rate 0.764825 # Inst issue rate
+system.cpu.iq.FU_type_0::total 16958 # Type of FU issued
+system.cpu.iq.rate 0.764735 # Inst issue rate
system.cpu.iq.fu_busy_cnt 141 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008314 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 47204 # Number of integer instruction queue reads
+system.cpu.iq.fu_busy_rate 0.008315 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 47200 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 30804 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 15755 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 17093 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 17091 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1183 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 848 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 23 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2239 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1783 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispLoadInsts 2238 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1782 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 16100 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 860 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 858 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3105 # number of memory reference insts executed
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:22:35
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:28:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
---------- Begin Simulation Statistics ----------
-host_inst_rate 918185 # Simulator instruction rate (inst/s)
-host_mem_usage 200072 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 520394424 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
sim_ticks 5651000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 855797 # Simulator instruction rate (inst/s)
+host_tick_rate 492033087 # Simulator tick rate (ticks/s)
+host_mem_usage 229652 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+sim_insts 9810 # Number of instructions simulated
+system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 11303 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 11303 # Number of busy cycles
-system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 9810 # Number of instructions executed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
system.cpu.num_int_insts 9715 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
-system.cpu.num_load_insts 1056 # Number of load instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1990 # number of memory refs
+system.cpu.num_load_insts 1056 # Number of load instructions
system.cpu.num_store_insts 934 # Number of store instructions
-system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 11303 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=X86TLB
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
type=Directory_Controller
children=directory memBuffer
buffer_size=0
+cntrl_id=1
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
+children=cacheMemory sequencer
buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
cache_response_latency=12
+cntrl_id=0
issue_latency=2
number_of_TBEs=256
recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.physmem]
type=PhysicalMemory
file=
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler tracer
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
adaptive_routing=false
buffer_size=0
control_msg_size=8
-endpoint_bandwidth=10000
-link_latency=1
+endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
-children=ext_links0 ext_links1 int_links0 int_links1
+children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
-num_int_nodes=3
print_config=false
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
ext_node=system.l1_cntrl0
-int_node=0
+int_node=system.ruby.network.topology.routers0
latency=1
+link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
ext_node=system.dir_cntrl0
-int_node=1
+int_node=system.ruby.network.topology.routers1
latency=1
+link_id=1
weight=1
[system.ruby.network.topology.int_links0]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
latency=1
-node_a=0
-node_b=2
+link_id=2
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links1]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
latency=1
-node_a=1
-node_b=2
+link_id=3
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers2
weight=1
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
[system.ruby.tracer]
type=RubyTracer
+ruby_system=system.ruby
warmup_length=100000
================ End RubySystem Configuration Print ================
-Real time: Apr/19/2011 12:26:55
+Real time: Jan/09/2012 14:28:32
Profiler Stats
--------------
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.17
-Virtual_time_in_minutes: 0.00283333
-Virtual_time_in_hours: 4.72222e-05
-Virtual_time_in_days: 1.96759e-06
+Virtual_time_in_seconds: 0.31
+Virtual_time_in_minutes: 0.00516667
+Virtual_time_in_hours: 8.61111e-05
+Virtual_time_in_days: 3.58796e-06
Ruby_current_time: 276484
Ruby_start_time: 0
Ruby_cycles: 276484
-mbytes_resident: 39.5938
-mbytes_total: 212.965
-resident_ratio: 0.185935
+mbytes_resident: 40.0625
+mbytes_total: 241.918
+resident_ratio: 0.165652
ruby_cycles_executed: [ 276485 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10428
-page_faults: 0
+page_reclaims: 11175
+page_faults: 4
swaps: 0
block_inputs: 0
-block_outputs: 64
+block_outputs: 0
Network Stats
-------------
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.155303
- links_utilized_percent_switch_0_link_0: 0.0622369 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.248369 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 2.48658
+ links_utilized_percent_switch_0_link_0: 2.48947 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 2.48369 bw: 16000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.15552
- links_utilized_percent_switch_1_link_0: 0.0620922 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.248947 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 2.48658
+ links_utilized_percent_switch_1_link_0: 2.48369 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 2.48947 bw: 16000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.248658
- links_utilized_percent_switch_2_link_0: 0.248947 bw: 160000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.248369 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 2.48658
+ links_utilized_percent_switch_2_link_0: 2.48947 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 2.48369 bw: 16000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
- system.ruby.cpu_ruby_ports.dcache_total_misses: 1377
- system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1377
- system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.cacheMemory
+ system.l1_cntrl0.cacheMemory_total_misses: 1377
+ system.l1_cntrl0.cacheMemory_total_demand_misses: 1377
+ system.l1_cntrl0.cacheMemory_total_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
- system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382%
- system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185%
- system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433%
+ system.l1_cntrl0.cacheMemory_request_type_LD: 36.2382%
+ system.l1_cntrl0.cacheMemory_request_type_ST: 18.5185%
+ system.l1_cntrl0.cacheMemory_request_type_IFETCH: 45.2433%
- system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 1377 100%
+ system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1377 100%
--- L1Cache ---
- Event Counts -
memory_reads: 1377
memory_writes: 1373
memory_refreshes: 576
- memory_total_request_delays: 3664
- memory_delays_per_request: 1.33236
- memory_delays_in_input_queue: 1372
+ memory_total_request_delays: 3035
+ memory_delays_per_request: 1.10364
+ memory_delays_in_input_queue: 743
memory_delays_behind_head_of_bank_queue: 6
memory_delays_stalled_at_head_of_bank_queue: 2286
memory_stalls_for_bank_busy: 791
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
-ID_W Memory_Ack
\ No newline at end of file
+ID_W Memory_Ack [0 ] 0
+
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simout
+Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:26:55
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:28:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
---------- Begin Simulation Statistics ----------
-host_inst_rate 147176 # Simulator instruction rate (inst/s)
-host_mem_usage 218080 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-host_tick_rate 4140017 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000276 # Number of seconds simulated
sim_ticks 276484 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 73084 # Simulator instruction rate (inst/s)
+host_tick_rate 2059440 # Simulator tick rate (ticks/s)
+host_mem_usage 247728 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+sim_insts 9810 # Number of instructions simulated
+system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 276484 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 276484 # Number of busy cycles
-system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 9810 # Number of instructions executed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
system.cpu.num_int_insts 9715 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
-system.cpu.num_load_insts 1056 # Number of load instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1990 # number of memory refs
+system.cpu.num_load_insts 1056 # Number of load instructions
system.cpu.num_store_insts 934 # Number of store instructions
-system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 276484 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:39:44
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:28:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
---------- Begin Simulation Statistics ----------
-host_inst_rate 743049 # Simulator instruction rate (inst/s)
-host_mem_usage 207784 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2149305775 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000029 # Number of seconds simulated
sim_ticks 28768000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 524711 # Simulator instruction rate (inst/s)
+host_tick_rate 1537080573 # Simulator tick rate (ticks/s)
+host_mem_usage 238628 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+sim_insts 9810 # Number of instructions simulated
+system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.numCycles 57536 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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+system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
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system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits
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-system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
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-system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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-system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
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+system.cpu.l2cache.overall_misses 361 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 361 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 57536 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 57536 # Number of busy cycles
-system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 9810 # Number of instructions executed
-system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
-system.cpu.num_int_insts 9715 # number of integer instructions
-system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
-system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
-system.cpu.num_load_insts 1056 # Number of load instructions
-system.cpu.num_mem_refs 1990 # number of memory refs
-system.cpu.num_store_insts 934 # Number of store instructions
-system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
readfile=tests/halt.sh
smbios_table=system.smbios_table
[system.membus.badaddr_responder]
type=IsaFake
+fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
[system.pc.behind_pci]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854779128
pio_latency=1000
pio_size=8
[system.pc.com_1]
type=Uart8250
+children=terminal
pio_addr=9223372036854776824
pio_latency=1000
platform=system.pc
system=system
-terminal=system.pc.terminal
+terminal=system.pc.com_1.terminal
pio=system.iobus.port[13]
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
[system.pc.fake_com_2]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776568
pio_latency=1000
pio_size=8
[system.pc.fake_com_3]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776808
pio_latency=1000
pio_size=8
[system.pc.fake_com_4]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776552
pio_latency=1000
pio_size=8
[system.pc.fake_floppy]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776818
pio_latency=1000
pio_size=2
[system.pc.i_dont_exist]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854775936
pio_latency=1000
pio_size=1
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
cmos=system.pc.south_bridge.cmos
dma1=system.pc.south_bridge.dma1
-int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
io_apic=system.pc.south_bridge.io_apic
keyboard=system.pc.south_bridge.keyboard
pic1=system.pc.south_bridge.pic1
[system.pc.south_bridge.cmos]
type=Cmos
-int_pin=system.pc.south_bridge.int_lines2.source
+children=int_pin
+int_pin=system.pc.south_bridge.cmos.int_pin
pio_addr=9223372036854775920
pio_latency=1000
platform=system.pc
time=Sun Jan 1 00:00:00 2012
pio=system.iobus.port[1]
+[system.pc.south_bridge.cmos.int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.dma1]
type=I8237
pio_addr=9223372036854775808
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.int_lines0.source
+source=system.pc.south_bridge.pic1.output
[system.pc.south_bridge.int_lines0.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=0
-[system.pc.south_bridge.int_lines0.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines1]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.int_lines1.source
+source=system.pc.south_bridge.pic2.output
[system.pc.south_bridge.int_lines1.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
number=2
-[system.pc.south_bridge.int_lines1.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines2]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.int_lines2.source
+source=system.pc.south_bridge.cmos.int_pin
[system.pc.south_bridge.int_lines2.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic2
number=0
-[system.pc.south_bridge.int_lines2.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines3]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.int_lines3.source
+source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines3.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
number=0
-[system.pc.south_bridge.int_lines3.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines4]
type=X86IntLine
children=sink
sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.int_lines3.source
+source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines4.sink]
type=X86IntSinkPin
[system.pc.south_bridge.int_lines5]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.int_lines5.source
+source=system.pc.south_bridge.keyboard.keyboard_int_pin
[system.pc.south_bridge.int_lines5.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=1
-[system.pc.south_bridge.int_lines5.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines6]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.int_lines6.source
+source=system.pc.south_bridge.keyboard.mouse_int_pin
[system.pc.south_bridge.int_lines6.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=12
-[system.pc.south_bridge.int_lines6.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.io_apic]
type=I82094AA
apic_id=1
[system.pc.south_bridge.keyboard]
type=I8042
+children=keyboard_int_pin mouse_int_pin
command_port=9223372036854775908
data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.int_lines5.source
-mouse_int_pin=system.pc.south_bridge.int_lines6.source
+keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
+mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[4]
+[system.pc.south_bridge.keyboard.keyboard_int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.keyboard.mouse_int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pic1]
type=I8259
+children=output
mode=I8259Master
-output=system.pc.south_bridge.int_lines0.source
+output=system.pc.south_bridge.pic1.output
pio_addr=9223372036854775840
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[5]
+[system.pc.south_bridge.pic1.output]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pic2]
type=I8259
+children=output
mode=I8259Slave
-output=system.pc.south_bridge.int_lines1.source
+output=system.pc.south_bridge.pic2.output
pio_addr=9223372036854775968
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[6]
+[system.pc.south_bridge.pic2.output]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pit]
type=I8254
-int_pin=system.pc.south_bridge.int_lines3.source
+children=int_pin
+int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[7]
+[system.pc.south_bridge.pit.int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.speaker]
type=PcSpeaker
i8254=system.pc.south_bridge.pit
system=system
pio=system.iobus.port[8]
-[system.pc.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
[system.physmem]
type=PhysicalMemory
file=
warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
warn: Reading current count from inactive timer.
-For more information see: http://www.m5sim.org/warn/1ea2be46
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: Don't know what interrupt to clear for console.
-For more information see: http://www.m5sim.org/warn/7fe1004f
warn: instruction 'fxsave' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: Tried to clear PCI interrupt 14
-For more information see: http://www.m5sim.org/warn/77378d57
warn: Unknown mouse command 0xe1.
-For more information see: http://www.m5sim.org/warn/2447512a
warn: instruction 'wbinvd' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:44:38
-M5 started Apr 19 2011 12:44:44
-M5 executing on maize
-command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
+gem5 compiled Jan 9 2012 20:47:38
+gem5 started Jan 9 2012 21:03:15
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
+warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112051446000 because m5_exit instruction encountered
+Exiting @ tick 5112043255000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.112037 # Number of seconds simulated
-sim_ticks 5112036996000 # Number of ticks simulated
+sim_seconds 5.112043 # Number of seconds simulated
+sim_ticks 5112043255000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2883648 # Simulator instruction rate (inst/s)
-host_tick_rate 36256565088 # Simulator tick rate (ticks/s)
-host_mem_usage 375496 # Number of bytes of host memory used
-host_seconds 141.00 # Real time elapsed on the host
-sim_insts 406583262 # Number of instructions simulated
-system.l2c.replacements 163860 # number of replacements
-system.l2c.tagsinuse 36838.766351 # Cycle average of tags in use
-system.l2c.total_refs 3334365 # Total number of references to valid blocks.
-system.l2c.sampled_refs 195829 # Sample count of references to valid blocks.
-system.l2c.avg_refs 17.026921 # Average number of references to valid blocks.
+host_inst_rate 2860366 # Simulator instruction rate (inst/s)
+host_tick_rate 35739722021 # Simulator tick rate (ticks/s)
+host_mem_usage 375540 # Number of bytes of host memory used
+host_seconds 143.04 # Real time elapsed on the host
+sim_insts 409133277 # Number of instructions simulated
+system.l2c.replacements 164044 # number of replacements
+system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
+system.l2c.total_refs 3332458 # Total number of references to valid blocks.
+system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
+system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 9696.304444 # Average occupied blocks per context
-system.l2c.occ_blocks::1 27142.461907 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.147954 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.414161 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 2042982 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 10263 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2053245 # number of ReadReq hits
-system.l2c.Writeback_hits::0 1528802 # number of Writeback hits
-system.l2c.Writeback_hits::total 1528802 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 168885 # number of ReadExReq hits
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
readfile=tests/halt.sh
smbios_table=system.smbios_table
[system.membus.badaddr_responder]
type=IsaFake
+fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
[system.pc.behind_pci]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854779128
pio_latency=1000
pio_size=8
[system.pc.com_1]
type=Uart8250
+children=terminal
pio_addr=9223372036854776824
pio_latency=1000
platform=system.pc
system=system
-terminal=system.pc.terminal
+terminal=system.pc.com_1.terminal
pio=system.iobus.port[13]
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
[system.pc.fake_com_2]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776568
pio_latency=1000
pio_size=8
[system.pc.fake_com_3]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776808
pio_latency=1000
pio_size=8
[system.pc.fake_com_4]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776552
pio_latency=1000
pio_size=8
[system.pc.fake_floppy]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854776818
pio_latency=1000
pio_size=2
[system.pc.i_dont_exist]
type=IsaFake
+fake_mem=false
pio_addr=9223372036854775936
pio_latency=1000
pio_size=1
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
cmos=system.pc.south_bridge.cmos
dma1=system.pc.south_bridge.dma1
-int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
io_apic=system.pc.south_bridge.io_apic
keyboard=system.pc.south_bridge.keyboard
pic1=system.pc.south_bridge.pic1
[system.pc.south_bridge.cmos]
type=Cmos
-int_pin=system.pc.south_bridge.int_lines2.source
+children=int_pin
+int_pin=system.pc.south_bridge.cmos.int_pin
pio_addr=9223372036854775920
pio_latency=1000
platform=system.pc
time=Sun Jan 1 00:00:00 2012
pio=system.iobus.port[1]
+[system.pc.south_bridge.cmos.int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.dma1]
type=I8237
pio_addr=9223372036854775808
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.int_lines0.source
+source=system.pc.south_bridge.pic1.output
[system.pc.south_bridge.int_lines0.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=0
-[system.pc.south_bridge.int_lines0.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines1]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.int_lines1.source
+source=system.pc.south_bridge.pic2.output
[system.pc.south_bridge.int_lines1.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
number=2
-[system.pc.south_bridge.int_lines1.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines2]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.int_lines2.source
+source=system.pc.south_bridge.cmos.int_pin
[system.pc.south_bridge.int_lines2.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic2
number=0
-[system.pc.south_bridge.int_lines2.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines3]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.int_lines3.source
+source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines3.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.pic1
number=0
-[system.pc.south_bridge.int_lines3.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines4]
type=X86IntLine
children=sink
sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.int_lines3.source
+source=system.pc.south_bridge.pit.int_pin
[system.pc.south_bridge.int_lines4.sink]
type=X86IntSinkPin
[system.pc.south_bridge.int_lines5]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.int_lines5.source
+source=system.pc.south_bridge.keyboard.keyboard_int_pin
[system.pc.south_bridge.int_lines5.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=1
-[system.pc.south_bridge.int_lines5.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.int_lines6]
type=X86IntLine
-children=sink source
+children=sink
sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.int_lines6.source
+source=system.pc.south_bridge.keyboard.mouse_int_pin
[system.pc.south_bridge.int_lines6.sink]
type=X86IntSinkPin
device=system.pc.south_bridge.io_apic
number=12
-[system.pc.south_bridge.int_lines6.source]
-type=X86IntSourcePin
-
[system.pc.south_bridge.io_apic]
type=I82094AA
apic_id=1
[system.pc.south_bridge.keyboard]
type=I8042
+children=keyboard_int_pin mouse_int_pin
command_port=9223372036854775908
data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.int_lines5.source
-mouse_int_pin=system.pc.south_bridge.int_lines6.source
+keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
+mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[4]
+[system.pc.south_bridge.keyboard.keyboard_int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.keyboard.mouse_int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pic1]
type=I8259
+children=output
mode=I8259Master
-output=system.pc.south_bridge.int_lines0.source
+output=system.pc.south_bridge.pic1.output
pio_addr=9223372036854775840
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[5]
+[system.pc.south_bridge.pic1.output]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pic2]
type=I8259
+children=output
mode=I8259Slave
-output=system.pc.south_bridge.int_lines1.source
+output=system.pc.south_bridge.pic2.output
pio_addr=9223372036854775968
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[6]
+[system.pc.south_bridge.pic2.output]
+type=X86IntSourcePin
+
[system.pc.south_bridge.pit]
type=I8254
-int_pin=system.pc.south_bridge.int_lines3.source
+children=int_pin
+int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872
pio_latency=1000
platform=system.pc
system=system
pio=system.iobus.port[7]
+[system.pc.south_bridge.pit.int_pin]
+type=X86IntSourcePin
+
[system.pc.south_bridge.speaker]
type=PcSpeaker
i8254=system.pc.south_bridge.pit
system=system
pio=system.iobus.port[8]
-[system.pc.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
[system.physmem]
type=PhysicalMemory
file=
warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
warn: Reading current count from inactive timer.
-For more information see: http://www.m5sim.org/warn/1ea2be46
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: Don't know what interrupt to clear for console.
-For more information see: http://www.m5sim.org/warn/7fe1004f
warn: instruction 'fxsave' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: Tried to clear PCI interrupt 14
-For more information see: http://www.m5sim.org/warn/77378d57
warn: Unknown mouse command 0xe1.
-For more information see: http://www.m5sim.org/warn/2447512a
warn: instruction 'wbinvd' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:44:38
-M5 started Apr 19 2011 12:46:29
-M5 executing on maize
-command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
+gem5 compiled Jan 9 2012 20:47:38
+gem5 started Jan 9 2012 21:05:49
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
+warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5195470393000 because m5_exit instruction encountered
sim_seconds 5.195470 # Number of seconds simulated
sim_ticks 5195470393000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1914891 # Simulator instruction rate (inst/s)
-host_tick_rate 37635937594 # Simulator tick rate (ticks/s)
-host_mem_usage 372104 # Number of bytes of host memory used
-host_seconds 138.05 # Real time elapsed on the host
-sim_insts 264342001 # Number of instructions simulated
+host_inst_rate 1858401 # Simulator instruction rate (inst/s)
+host_tick_rate 36414646229 # Simulator tick rate (ticks/s)
+host_mem_usage 372180 # Number of bytes of host memory used
+host_seconds 142.68 # Real time elapsed on the host
+sim_insts 265147881 # Number of instructions simulated
system.l2c.replacements 136133 # number of replacements
system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
system.l2c.total_refs 3363370 # Total number of references to valid blocks.
system.cpu.numCycles 10390940786 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 264342001 # Number of instructions executed
+system.cpu.num_insts 265147881 # Number of instructions executed
system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
projects / gem5.git / commitdiff