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arch-arm: Fix Trap to EL1 on register DC CVAU
authorJordi Vaquero <jordi.vaquero@metempsy.com>
Fri, 24 Jul 2020 08:26:15 +0000 (10:26 +0200)
committerJordi Vaquero <jordi.vaquero@metempsy.com>
Fri, 24 Jul 2020 12:04:12 +0000 (12:04 +0000)
Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31774
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/insts/misc64.cc patch | blob | history

diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 49cc6b0f87f04bc123428aa50f1383c6c01d32da..f9f00f06a80281ebc8342a2ac8b3ed16696a6f8b 100644 (file)
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -146,7 +146,7 @@ MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
         break;
       case MISCREG_DC_CVAU_Xt:
         trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
-            el == EL1;
+            el == EL0;
         break;
       case MISCREG_CTR_EL0:
         trap_to_sup = el == EL0 && !sctlr.uct &&