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 # Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)!
 
-LibreSOC strives to deliver a fully capable and competitive Libre integrated System on Chip. We want to maximize the degree of trust a customer can place in his or her processor. We do this by providing the customer the freedom to  study, modify, and redistribute the SOC source from HDL to VLSI.
+LibreSOC strives to deliver a fully capable and competitive mass volume Libre integrated System on Chip for use in chromebooks, smartphone, tablets and industrial boards. We want to maximize the degree of trust a customer can place in their processor. We do this by providing the customer the freedom to study, modify, and redistribute the the bootloader and Operating System full source code *and* the full SoC source from HDL to VLSI.
 
 Right now, we're targeting a (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC.
 
 ## Why a Libre SOC?
 
-Its quite hard to guarantee that a performant processors(think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com).
+Its quite hard to guarantee that a performant processors (think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com).
 
-There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline(this doesn’t even consider out of order execution).
+There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline (this doesn’t even consider out of order execution).
 
 Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them.
 
@@ -17,19 +17,19 @@ Such a processor is referred to as a Libre processor. However, processors themse
 ## Benefits: Privacy, Safety-Critical, Peace of Mind...
 Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html).
 
-There is a very real need for reliable safety critical processors(think airplane, smart car, pacemaker...).
-LibreSOC poses to you that it is impossible to trust a processor in a safety critical environment without both access
+There is a very real need for reliable safety critical processors (think airplane, smart car, nuclear power plant, pacemaker...).
+LibreSOC posits that it is impossible to trust a processor in a safety critical environment without both access
 to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they 
 expect. An ISA level simulator is no longer satisfactory.
 
 Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.
 
 ## Still Have Questions?
+
 Read about the business and practical benefits of a LibreSOC below.
 
 [[why_a_libresoc]]
 
-
 # Join us in Realizing the First Market Ready LibreSOC!
 
 First. join the