add get on subvl

diff --git a/riscv/processor.cc b/riscv/processor.cc
index c6d604a67d3cc703992adf39f08589b222d3debb..c93c2e52329c899c9bdbee7927cc877ebe9c7cfd 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -894,6 +894,8 @@ reg_t processor_t::get_csr(int which)
              (state.sv().ssvoffs<<26)     | (state.sv().dsvoffs<<28);
     case CSR_USVMVL:
       return state.sv().mvl;
+    case CSR_USVSUBVL:
+      return state.sv().subvl;
     case CSR_SVREGTOP:
     case CSR_SVREGBOT:
       return 0;// XXX TODO: return correct entry