(no commit message)

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 5220ea635fa7fc51e3546d6861428d3b32a5a7d1..0e74eab3ffe6074573f7a3b1a92a01e517de00b5 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -96,6 +96,15 @@ as noted by Intel in their notes on mulx,
 RA*RB+RC+RD cannot overflow, so does not require
 setting an additional CA flag.
 
+Combined with a Vectorised big-int `sv.addeo` the key inner loop of
+Knuth's Algorithm M may be achieved in four instructions:
+
+    li r16, 0               # carry-accululator to zero
+    addicc r16, r16, 0      # CA to zero as well
+    sv.mulx r0.v, r8.v, r16 # mul vector using r16
+    sv.addeo 
+    
+
 Normally, in a Scalar ISA, the use of a register as both a source
 and destination like this would create costly Dependency Hazards, so
 such an instruction would never be proposed.  However: it turns out