arch-power: Added support for Program Interrupt

Added supoort for program interrupt for Privileged type instruction.

* Added flag IsPrivileged to check wheather instruction is
  privileged or not.
* Define bit number to be set in MSR for corresponding interrupt.
* Added Program interrupt handler with privileged type interrupt handler.
* Add IsPrivileged flag in all privileged instructions
* Add checker for PR bit inorder to verify mode for privilege instructions
  and raise interrupt if needed.

Change-Id: I2aeb1a603568a6f80cd074bf67d4a528ebb6a5bd
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>

diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index 5e57d1ec31e4f97c74c8ee006049bad7d0e6f5e1..863b3f7b9b37086f8a4a8b8442a9120749bb3bce 100644 (file)
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -33,6 +33,8 @@
 #include "cpu/thread_context.hh"
 #include "sim/faults.hh"
 
+#define SRR1_PRI_BIT      17
+
 #define setbit(shift, mask) ( (uint64_t)1 << shift | mask)
 #define unsetbit(shift,mask) ( ~((uint64_t)1 << shift) & mask)
 #define setBitMask(shift) ( (uint64_t)1 << shift)
@@ -135,6 +137,35 @@ class PowerInterrupt : public PowerFaultBase
 
 };
 
+//TODO: Need to add Floating point and TM Bad thing fault handler
+class ProgramInterrupt : public PowerInterrupt
+{
+  public:
+    ProgramInterrupt()
+    {
+    }
+    virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+                       StaticInst::nullStaticInstPtr ,uint64_t bitSet = 0)
+    {
+      tc->setIntReg(INTREG_SRR0, tc->instAddr() + 4);
+      PowerInterrupt::updateSRR1(tc, bitSet);
+      PowerInterrupt::updateMsr(tc);
+      tc->pcState(ProgramPCSet);
+    }
+};
+
+class ProgramPriInterrupt : public ProgramInterrupt
+{
+  public:
+    ProgramPriInterrupt()
+    {
+    }
+    virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+                       StaticInst::nullStaticInstPtr)
+    {
+      ProgramInterrupt::invoke(tc, inst, setBitMask(SRR1_PRI_BIT));
+    }
+};
 
 class SystemCallInterrupt : public PowerInterrupt
 {

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index a08e10d5e65e37b0cdefb38cf183909b403e1cb3..1912316d82081be8e3449cc0a51fce2540716aaf 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -139,7 +139,7 @@ decode PO default Unknown::unknown() {
                 MSR = insertBits(MSR,11,6,bits(SRR1,11,6));
                 MSR = insertBits(MSR,3,0,bits(SRR1,3,0));
                 NIA = SRR0 & -4ULL;
-            }});
+            }}, [ IsPrivileged ]);
             274:  hrfid({{
                 if((bits(MSR,34,32)!=0x02)|(bits(HSRR1,34,32)!=0x00))
                     MSR = insertBits(MSR,34,32,bits(HSRR1,34,32));
@@ -625,7 +625,9 @@ decode PO default Unknown::unknown() {
                 0x2c9: mthdec({{HDEC = Rs;}});
                 0x24a: mtpcr({{PCR = Rs;}});
             }
-            83: mfmsr({{ Rt = MSR }});
+
+            83: mfmsr({{ Rt = MSR; }}, [ IsPrivileged ]);
+
             178: mtmsrd({{
                 if (L == 0 ) {
                     uint64_t val = bits(Rs, 34, 32);
@@ -665,7 +667,7 @@ decode PO default Unknown::unknown() {
                      MSR = insertBits(MSR,15,bits(Rs,15));
                      MSR = insertBits(MSR,1,bits(Rs,1));
                  }
-            }});
+            }}, [ IsPrivileged ]);
         }
 
         // Integer logic instructions use source registers Rs and Rb,
@@ -886,9 +888,9 @@ decode PO default Unknown::unknown() {
             54:  dcbst({{ }});
             982: icbi({{ }});
             306: tlbie({{ }});
-            274: tlbiel({{ }});
+            274: tlbiel({{ }}, [ IsPrivileged ]);
             566: tlbsync({{ }});
-            498: slbia({{ }});
+            498: slbia({{ }}, [ IsPrivileged ]);
         }
 
         // These instructions are of XO form with bit 21 as the OE bit.

diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa
index b2c516b42d136193f8e40b512a89f1a0a937064f..68f0d09c42bfa85ff5a083082dd750ee9f67f0d5 100644 (file)
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -127,9 +127,25 @@ setOVCode = '''
 
 }};
 
+// Check the PR bit in MSR (which is bit number 14 of MSR)
+// to see if Program interrupt is there.
+
+let {{
+
+def GetPriCode(code):
+    cond_code =  'if (bits(MSR,14)==1) {\n'
+    cond_code += 'fault=std::make_shared<ProgramPriInterrupt>();\n'
+    cond_code += '} else {\n'
+    cond_code += code + '\n'
+    cond_code += '}\n'
+    return cond_code
+
+}};
 
 // A basic integer instruction.
-def format IntOp(code, inst_flags = []) {{
+def format IntOp(code,inst_flags = []) {{
+    if 'IsPrivileged' in inst_flags:
+        code = GetPriCode(code)
     (header_output, decoder_output, decode_block, exec_output) = \
         GenAluOp(name, Name, 'IntOp', code, inst_flags, BasicDecode,
                  BasicConstructor)

diff --git a/src/arch/power/isa/formats/misc.isa b/src/arch/power/isa/formats/misc.isa
index 877ac634de9b0f387c13f40890a3a6042b590115..49235950de94211a11bed3b7c3169d9afd548783 100644 (file)
--- a/src/arch/power/isa/formats/misc.isa
+++ b/src/arch/power/isa/formats/misc.isa
@@ -49,7 +49,23 @@ def template MiscOpExecute {{
     }
 }};
 
+// Check the PR bit in MSR (which is bit number 14 of MSR)
+// to see if Program interrupt is there.
+
+let {{
+
+def GetPriCode(code):
+    cond_code =  'if (bits(MSR,14)==1) {\n'
+    cond_code += 'fault=std::make_shared<ProgramPriInterrupt>();\n'
+    cond_code += '} else {\n'
+    cond_code += code + '\n'
+    cond_code += '}\n'
+    return cond_code
+
+}};
 def format MiscOp(code, opt_flags = []) {{
+    if 'IsPrivileged' in opt_flags:
+        code = GetPriCode(code)
     iop = InstObjParams(name, Name, 'IntOp',
                         {"code": code},
                         opt_flags)

diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 1c2b63a2b5ee33eb07f1f7ba3563a844177a3538..99b2fae81400ced2bebadb4510d1c69df07199d5 100644 (file)
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -99,6 +99,7 @@ class StaticInstFlags(Enum):
 
         'IsSyscall',        # Causes a system call to be emulated in syscall
                             # emulation mode.
+        'IsPrivileged',     # Is flag to check instruction is privileged or not
 
         # Flags for microcode
         'IsMacroop',        # Is a macroop containing microops

diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 146be8c72d0a7859c5ebcdbce12f90245537c11d..15a25a2c133daacd8523ad4788ebf35178c4091e 100644 (file)
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -195,6 +195,7 @@ class StaticInst : public RefCounted, public StaticInstFlags
     bool isIprAccess() const { return flags[IsIprAccess]; }
     bool isUnverifiable() const { return flags[IsUnverifiable]; }
     bool isSyscall() const { return flags[IsSyscall]; }
+    bool isPrivileged() const { return flags[IsPrivileged]; }
     bool isMacroop() const { return flags[IsMacroop]; }
     bool isMicroop() const { return flags[IsMicroop]; }
     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }