winsys/radeon: drop support for DRM 2.12.0 (kernel < 3.2)

in order to make some winsys interface changes easier

This distros should use new DRM if they want to use new Mesa:
  Distro    kernel  mesa    eol
  SLES 10   2.6.16  6.4.2   2016-07
  SLED 11   3.0     9.0.3   2022-03
  RHEL 5    2.6.18  6.5.1   2017-03
  RHEL 6    2.6.32  10.4.3  2020-11
  Debian 6  2.6.32  7.7.1   2016-02

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 7329ceedf04a484b2c8f279378a8217e02653c20..1160d235062c10709bf63a201b56e55787c72aa1 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -26,24 +26,10 @@
 
 /* The public winsys interface header for the radeon driver. */
 
-/* R300 features in DRM.
- *
- * 2.6.0:
- * - Hyper-Z
- * - GB_Z_PEQ_CONFIG on rv350->r4xx
- * - R500 FG_ALPHA_VALUE
- *
- * 2.8.0:
- * - R500 US_FORMAT regs
- * - R500 ARGB2101010 colorbuffer
- * - CMask and AA regs
- * - R16F/RG16F
- */
-
 #include "pipebuffer/pb_buffer.h"
 
 #define RADEON_FLUSH_ASYNC             (1 << 0)
-#define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1) /* needs DRM 2.12.0 */
+#define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1)
 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
 
 /* Tiling flags. */

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 8151c44706509b62f241bda1a7cf6ec6d60a3e85..1accc6a1863900fbbde0b27b5a6438aa80d6a246 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -174,9 +174,9 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
     /* Get DRM version. */
     version = drmGetVersion(ws->fd);
     if (version->version_major != 2 ||
-        version->version_minor < 3) {
+        version->version_minor < 12) {
         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
-                "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
+                "only compatible with 2.12.0 (kernel 3.2) or later.\n",
                 __FUNCTION__,
                 version->version_major,
                 version->version_minor,
@@ -374,8 +374,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
     else if (ws->gen >= DRV_R600) {
         uint32_t tiling_config = 0;
 
-        if (ws->info.drm_minor >= 9 &&
-            !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
+        if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
                                   "num backends",
                                   &ws->info.num_render_backends))
             return FALSE;
@@ -401,27 +400,20 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
             ws->info.pipe_interleave_bytes =
                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 
-        if (ws->info.drm_minor >= 11) {
-            radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
-                                 &ws->info.num_tile_pipes);
-
-            /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
-             * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
-             * reports a different value (12). Fix it by setting what's in the
-             * GB_TILE_MODE array (8).
-             */
-            if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
-                ws->info.num_tile_pipes = 8;
-
-            if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
-                                      &ws->info.r600_gb_backend_map))
-                ws->info.r600_gb_backend_map_valid = TRUE;
-        } else {
-            ws->info.num_tile_pipes =
-                ws->info.chip_class >= EVERGREEN ?
-                    1 << (tiling_config & 0xf) :
-                    1 << ((tiling_config & 0xe) >> 1);
-        }
+        radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
+                             &ws->info.num_tile_pipes);
+
+        /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
+         * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
+         * reports a different value (12). Fix it by setting what's in the
+         * GB_TILE_MODE array (8).
+         */
+        if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
+            ws->info.num_tile_pipes = 8;
+
+        if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
+                                  &ws->info.r600_gb_backend_map))
+            ws->info.r600_gb_backend_map_valid = TRUE;
 
         ws->info.has_virtual_memory = FALSE;
         if (ws->info.drm_minor >= 13) {